s5p_mfc.c revision b27a23be0d1de44ab2cc01495b4f9149f4f762d5
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 181{ 182 struct video_device *vdev = video_devdata(file); 183 184 if (!vdev) { 185 mfc_err("failed to get video_device"); 186 return MFCNODE_INVALID; 187 } 188 if (vdev->index == 0) 189 return MFCNODE_DECODER; 190 else if (vdev->index == 1) 191 return MFCNODE_ENCODER; 192 return MFCNODE_INVALID; 193} 194 195static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 196{ 197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 200} 201 202static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 203{ 204 struct s5p_mfc_buf *dst_buf; 205 struct s5p_mfc_dev *dev = ctx->dev; 206 207 ctx->state = MFCINST_FINISHED; 208 ctx->sequence++; 209 while (!list_empty(&ctx->dst_queue)) { 210 dst_buf = list_entry(ctx->dst_queue.next, 211 struct s5p_mfc_buf, list); 212 mfc_debug(2, "Cleaning up buffer: %d\n", 213 dst_buf->b->v4l2_buf.index); 214 vb2_set_plane_payload(dst_buf->b, 0, 0); 215 vb2_set_plane_payload(dst_buf->b, 1, 0); 216 list_del(&dst_buf->list); 217 ctx->dst_queue_cnt--; 218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 219 220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 223 else 224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 225 226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 228 } 229} 230 231static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 232{ 233 struct s5p_mfc_dev *dev = ctx->dev; 234 struct s5p_mfc_buf *dst_buf, *src_buf; 235 size_t dec_y_addr; 236 unsigned int frame_type; 237 238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 240 241 /* Copy timestamp / timecode from decoded src to dst and set 242 appropraite flags */ 243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 246 memcpy(&dst_buf->b->v4l2_buf.timecode, 247 &src_buf->b->v4l2_buf.timecode, 248 sizeof(struct v4l2_timecode)); 249 memcpy(&dst_buf->b->v4l2_buf.timestamp, 250 &src_buf->b->v4l2_buf.timestamp, 251 sizeof(struct timeval)); 252 switch (frame_type) { 253 case S5P_FIMV_DECODE_FRAME_I_FRAME: 254 dst_buf->b->v4l2_buf.flags |= 255 V4L2_BUF_FLAG_KEYFRAME; 256 break; 257 case S5P_FIMV_DECODE_FRAME_P_FRAME: 258 dst_buf->b->v4l2_buf.flags |= 259 V4L2_BUF_FLAG_PFRAME; 260 break; 261 case S5P_FIMV_DECODE_FRAME_B_FRAME: 262 dst_buf->b->v4l2_buf.flags |= 263 V4L2_BUF_FLAG_BFRAME; 264 break; 265 } 266 break; 267 } 268 } 269} 270 271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 272{ 273 struct s5p_mfc_dev *dev = ctx->dev; 274 struct s5p_mfc_buf *dst_buf; 275 size_t dspl_y_addr; 276 unsigned int frame_type; 277 unsigned int index; 278 279 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 280 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 281 282 /* If frame is same as previous then skip and do not dequeue */ 283 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 284 if (!ctx->after_packed_pb) 285 ctx->sequence++; 286 ctx->after_packed_pb = 0; 287 return; 288 } 289 ctx->sequence++; 290 /* The MFC returns address of the buffer, now we have to 291 * check which videobuf does it correspond to */ 292 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 293 /* Check if this is the buffer we're looking for */ 294 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 295 list_del(&dst_buf->list); 296 ctx->dst_queue_cnt--; 297 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 298 if (s5p_mfc_hw_call(dev->mfc_ops, 299 get_pic_type_top, ctx) == 300 s5p_mfc_hw_call(dev->mfc_ops, 301 get_pic_type_bot, ctx)) 302 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 303 else 304 dst_buf->b->v4l2_buf.field = 305 V4L2_FIELD_INTERLACED; 306 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 307 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 308 clear_bit(dst_buf->b->v4l2_buf.index, 309 &ctx->dec_dst_flag); 310 311 vb2_buffer_done(dst_buf->b, 312 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 313 314 index = dst_buf->b->v4l2_buf.index; 315 break; 316 } 317 } 318} 319 320/* Handle frame decoding interrupt */ 321static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 322 unsigned int reason, unsigned int err) 323{ 324 struct s5p_mfc_dev *dev = ctx->dev; 325 unsigned int dst_frame_status; 326 struct s5p_mfc_buf *src_buf; 327 unsigned long flags; 328 unsigned int res_change; 329 330 unsigned int index; 331 332 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 333 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 334 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 335 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 336 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 337 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 338 if (ctx->state == MFCINST_RES_CHANGE_INIT) 339 ctx->state = MFCINST_RES_CHANGE_FLUSH; 340 if (res_change == S5P_FIMV_RES_INCREASE || 341 res_change == S5P_FIMV_RES_DECREASE) { 342 ctx->state = MFCINST_RES_CHANGE_INIT; 343 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 344 wake_up_ctx(ctx, reason, err); 345 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 346 BUG(); 347 s5p_mfc_clock_off(); 348 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 349 return; 350 } 351 if (ctx->dpb_flush_flag) 352 ctx->dpb_flush_flag = 0; 353 354 spin_lock_irqsave(&dev->irqlock, flags); 355 /* All frames remaining in the buffer have been extracted */ 356 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 357 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 358 s5p_mfc_handle_frame_all_extracted(ctx); 359 ctx->state = MFCINST_RES_CHANGE_END; 360 goto leave_handle_frame; 361 } else { 362 s5p_mfc_handle_frame_all_extracted(ctx); 363 } 364 } 365 366 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 367 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 368 s5p_mfc_handle_frame_copy_time(ctx); 369 370 /* A frame has been decoded and is in the buffer */ 371 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 372 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 373 s5p_mfc_handle_frame_new(ctx, err); 374 } else { 375 mfc_debug(2, "No frame decode\n"); 376 } 377 /* Mark source buffer as complete */ 378 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 379 && !list_empty(&ctx->src_queue)) { 380 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 381 list); 382 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 383 get_consumed_stream, dev); 384 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 385 ctx->consumed_stream + STUFF_BYTE < 386 src_buf->b->v4l2_planes[0].bytesused) { 387 /* Run MFC again on the same buffer */ 388 mfc_debug(2, "Running again the same buffer\n"); 389 ctx->after_packed_pb = 1; 390 } else { 391 index = src_buf->b->v4l2_buf.index; 392 mfc_debug(2, "MFC needs next buffer\n"); 393 ctx->consumed_stream = 0; 394 list_del(&src_buf->list); 395 ctx->src_queue_cnt--; 396 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 397 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 398 else 399 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 400 } 401 } 402leave_handle_frame: 403 spin_unlock_irqrestore(&dev->irqlock, flags); 404 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 405 || ctx->dst_queue_cnt < ctx->dpb_count) 406 clear_work_bit(ctx); 407 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 408 wake_up_ctx(ctx, reason, err); 409 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 410 BUG(); 411 s5p_mfc_clock_off(); 412 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 413} 414 415/* Error handling for interrupt */ 416static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx, 417 unsigned int reason, unsigned int err) 418{ 419 struct s5p_mfc_dev *dev; 420 unsigned long flags; 421 422 /* If no context is available then all necessary 423 * processing has been done. */ 424 if (ctx == NULL) 425 return; 426 427 dev = ctx->dev; 428 mfc_err("Interrupt Error: %08x\n", err); 429 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 430 wake_up_dev(dev, reason, err); 431 432 /* Error recovery is dependent on the state of context */ 433 switch (ctx->state) { 434 case MFCINST_INIT: 435 /* This error had to happen while acquireing instance */ 436 case MFCINST_GOT_INST: 437 /* This error had to happen while parsing the header */ 438 case MFCINST_HEAD_PARSED: 439 /* This error had to happen while setting dst buffers */ 440 case MFCINST_RETURN_INST: 441 /* This error had to happen while releasing instance */ 442 clear_work_bit(ctx); 443 wake_up_ctx(ctx, reason, err); 444 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 445 BUG(); 446 s5p_mfc_clock_off(); 447 ctx->state = MFCINST_ERROR; 448 break; 449 case MFCINST_FINISHING: 450 case MFCINST_FINISHED: 451 case MFCINST_RUNNING: 452 /* It is higly probable that an error occured 453 * while decoding a frame */ 454 clear_work_bit(ctx); 455 ctx->state = MFCINST_ERROR; 456 /* Mark all dst buffers as having an error */ 457 spin_lock_irqsave(&dev->irqlock, flags); 458 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 459 &ctx->vq_dst); 460 /* Mark all src buffers as having an error */ 461 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 462 &ctx->vq_src); 463 spin_unlock_irqrestore(&dev->irqlock, flags); 464 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 465 BUG(); 466 s5p_mfc_clock_off(); 467 break; 468 default: 469 mfc_err("Encountered an error interrupt which had not been handled\n"); 470 break; 471 } 472 return; 473} 474 475/* Header parsing interrupt handling */ 476static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 477 unsigned int reason, unsigned int err) 478{ 479 struct s5p_mfc_dev *dev; 480 481 if (ctx == NULL) 482 return; 483 dev = ctx->dev; 484 if (ctx->c_ops->post_seq_start) { 485 if (ctx->c_ops->post_seq_start(ctx)) 486 mfc_err("post_seq_start() failed\n"); 487 } else { 488 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 489 dev); 490 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 491 dev); 492 493 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 494 495 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 496 dev); 497 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 498 dev); 499 if (ctx->img_width == 0 || ctx->img_height == 0) 500 ctx->state = MFCINST_ERROR; 501 else 502 ctx->state = MFCINST_HEAD_PARSED; 503 504 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 505 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 506 !list_empty(&ctx->src_queue)) { 507 struct s5p_mfc_buf *src_buf; 508 src_buf = list_entry(ctx->src_queue.next, 509 struct s5p_mfc_buf, list); 510 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 511 dev) < 512 src_buf->b->v4l2_planes[0].bytesused) 513 ctx->head_processed = 0; 514 else 515 ctx->head_processed = 1; 516 } else { 517 ctx->head_processed = 1; 518 } 519 } 520 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 521 clear_work_bit(ctx); 522 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 523 BUG(); 524 s5p_mfc_clock_off(); 525 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 526 wake_up_ctx(ctx, reason, err); 527} 528 529/* Header parsing interrupt handling */ 530static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 531 unsigned int reason, unsigned int err) 532{ 533 struct s5p_mfc_buf *src_buf; 534 struct s5p_mfc_dev *dev; 535 unsigned long flags; 536 537 if (ctx == NULL) 538 return; 539 dev = ctx->dev; 540 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 541 ctx->int_type = reason; 542 ctx->int_err = err; 543 ctx->int_cond = 1; 544 clear_work_bit(ctx); 545 if (err == 0) { 546 ctx->state = MFCINST_RUNNING; 547 if (!ctx->dpb_flush_flag && ctx->head_processed) { 548 spin_lock_irqsave(&dev->irqlock, flags); 549 if (!list_empty(&ctx->src_queue)) { 550 src_buf = list_entry(ctx->src_queue.next, 551 struct s5p_mfc_buf, list); 552 list_del(&src_buf->list); 553 ctx->src_queue_cnt--; 554 vb2_buffer_done(src_buf->b, 555 VB2_BUF_STATE_DONE); 556 } 557 spin_unlock_irqrestore(&dev->irqlock, flags); 558 } else { 559 ctx->dpb_flush_flag = 0; 560 } 561 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 562 BUG(); 563 564 s5p_mfc_clock_off(); 565 566 wake_up(&ctx->queue); 567 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 568 } else { 569 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 570 BUG(); 571 572 s5p_mfc_clock_off(); 573 574 wake_up(&ctx->queue); 575 } 576} 577 578static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 579 unsigned int reason, unsigned int err) 580{ 581 struct s5p_mfc_dev *dev = ctx->dev; 582 struct s5p_mfc_buf *mb_entry; 583 584 mfc_debug(2, "Stream completed"); 585 586 s5p_mfc_clear_int_flags(dev); 587 ctx->int_type = reason; 588 ctx->int_err = err; 589 ctx->state = MFCINST_FINISHED; 590 591 spin_lock(&dev->irqlock); 592 if (!list_empty(&ctx->dst_queue)) { 593 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 594 list); 595 list_del(&mb_entry->list); 596 ctx->dst_queue_cnt--; 597 vb2_set_plane_payload(mb_entry->b, 0, 0); 598 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 599 } 600 spin_unlock(&dev->irqlock); 601 602 clear_work_bit(ctx); 603 604 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 605 WARN_ON(1); 606 607 s5p_mfc_clock_off(); 608 wake_up(&ctx->queue); 609 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 610} 611 612/* Interrupt processing */ 613static irqreturn_t s5p_mfc_irq(int irq, void *priv) 614{ 615 struct s5p_mfc_dev *dev = priv; 616 struct s5p_mfc_ctx *ctx; 617 unsigned int reason; 618 unsigned int err; 619 620 mfc_debug_enter(); 621 /* Reset the timeout watchdog */ 622 atomic_set(&dev->watchdog_cnt, 0); 623 ctx = dev->ctx[dev->curr_ctx]; 624 /* Get the reason of interrupt and the error code */ 625 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 626 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 627 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 628 switch (reason) { 629 case S5P_MFC_R2H_CMD_ERR_RET: 630 /* An error has occured */ 631 if (ctx->state == MFCINST_RUNNING && 632 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 633 dev->warn_start) 634 s5p_mfc_handle_frame(ctx, reason, err); 635 else 636 s5p_mfc_handle_error(ctx, reason, err); 637 clear_bit(0, &dev->enter_suspend); 638 break; 639 640 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 641 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 642 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 643 if (ctx->c_ops->post_frame_start) { 644 if (ctx->c_ops->post_frame_start(ctx)) 645 mfc_err("post_frame_start() failed\n"); 646 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 647 wake_up_ctx(ctx, reason, err); 648 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 649 BUG(); 650 s5p_mfc_clock_off(); 651 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 652 } else { 653 s5p_mfc_handle_frame(ctx, reason, err); 654 } 655 break; 656 657 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 658 s5p_mfc_handle_seq_done(ctx, reason, err); 659 break; 660 661 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 662 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 663 ctx->state = MFCINST_GOT_INST; 664 clear_work_bit(ctx); 665 wake_up(&ctx->queue); 666 goto irq_cleanup_hw; 667 668 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 669 clear_work_bit(ctx); 670 ctx->state = MFCINST_FREE; 671 wake_up(&ctx->queue); 672 goto irq_cleanup_hw; 673 674 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 675 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 676 case S5P_MFC_R2H_CMD_SLEEP_RET: 677 case S5P_MFC_R2H_CMD_WAKEUP_RET: 678 if (ctx) 679 clear_work_bit(ctx); 680 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 681 wake_up_dev(dev, reason, err); 682 clear_bit(0, &dev->hw_lock); 683 clear_bit(0, &dev->enter_suspend); 684 break; 685 686 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 687 s5p_mfc_handle_init_buffers(ctx, reason, err); 688 break; 689 690 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 691 s5p_mfc_handle_stream_complete(ctx, reason, err); 692 break; 693 694 default: 695 mfc_debug(2, "Unknown int reason\n"); 696 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 697 } 698 mfc_debug_leave(); 699 return IRQ_HANDLED; 700irq_cleanup_hw: 701 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 702 ctx->int_type = reason; 703 ctx->int_err = err; 704 ctx->int_cond = 1; 705 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 706 mfc_err("Failed to unlock hw\n"); 707 708 s5p_mfc_clock_off(); 709 710 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 711 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 712 return IRQ_HANDLED; 713} 714 715/* Open an MFC node */ 716static int s5p_mfc_open(struct file *file) 717{ 718 struct s5p_mfc_dev *dev = video_drvdata(file); 719 struct s5p_mfc_ctx *ctx = NULL; 720 struct vb2_queue *q; 721 int ret = 0; 722 723 mfc_debug_enter(); 724 if (mutex_lock_interruptible(&dev->mfc_mutex)) 725 return -ERESTARTSYS; 726 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 727 /* Allocate memory for context */ 728 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 729 if (!ctx) { 730 mfc_err("Not enough memory\n"); 731 ret = -ENOMEM; 732 goto err_alloc; 733 } 734 v4l2_fh_init(&ctx->fh, video_devdata(file)); 735 file->private_data = &ctx->fh; 736 v4l2_fh_add(&ctx->fh); 737 ctx->dev = dev; 738 INIT_LIST_HEAD(&ctx->src_queue); 739 INIT_LIST_HEAD(&ctx->dst_queue); 740 ctx->src_queue_cnt = 0; 741 ctx->dst_queue_cnt = 0; 742 /* Get context number */ 743 ctx->num = 0; 744 while (dev->ctx[ctx->num]) { 745 ctx->num++; 746 if (ctx->num >= MFC_NUM_CONTEXTS) { 747 mfc_err("Too many open contexts\n"); 748 ret = -EBUSY; 749 goto err_no_ctx; 750 } 751 } 752 /* Mark context as idle */ 753 clear_work_bit_irqsave(ctx); 754 dev->ctx[ctx->num] = ctx; 755 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 756 ctx->type = MFCINST_DECODER; 757 ctx->c_ops = get_dec_codec_ops(); 758 s5p_mfc_dec_init(ctx); 759 /* Setup ctrl handler */ 760 ret = s5p_mfc_dec_ctrls_setup(ctx); 761 if (ret) { 762 mfc_err("Failed to setup mfc controls\n"); 763 goto err_ctrls_setup; 764 } 765 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 766 ctx->type = MFCINST_ENCODER; 767 ctx->c_ops = get_enc_codec_ops(); 768 /* only for encoder */ 769 INIT_LIST_HEAD(&ctx->ref_queue); 770 ctx->ref_queue_cnt = 0; 771 s5p_mfc_enc_init(ctx); 772 /* Setup ctrl handler */ 773 ret = s5p_mfc_enc_ctrls_setup(ctx); 774 if (ret) { 775 mfc_err("Failed to setup mfc controls\n"); 776 goto err_ctrls_setup; 777 } 778 } else { 779 ret = -ENOENT; 780 goto err_bad_node; 781 } 782 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 783 ctx->inst_no = -1; 784 /* Load firmware if this is the first instance */ 785 if (dev->num_inst == 1) { 786 dev->watchdog_timer.expires = jiffies + 787 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 788 add_timer(&dev->watchdog_timer); 789 ret = s5p_mfc_power_on(); 790 if (ret < 0) { 791 mfc_err("power on failed\n"); 792 goto err_pwr_enable; 793 } 794 s5p_mfc_clock_on(); 795 ret = s5p_mfc_alloc_and_load_firmware(dev); 796 if (ret) 797 goto err_alloc_fw; 798 /* Init the FW */ 799 ret = s5p_mfc_init_hw(dev); 800 if (ret) 801 goto err_init_hw; 802 s5p_mfc_clock_off(); 803 } 804 /* Init videobuf2 queue for CAPTURE */ 805 q = &ctx->vq_dst; 806 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 807 q->drv_priv = &ctx->fh; 808 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 809 q->io_modes = VB2_MMAP; 810 q->ops = get_dec_queue_ops(); 811 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 812 q->io_modes = VB2_MMAP | VB2_USERPTR; 813 q->ops = get_enc_queue_ops(); 814 } else { 815 ret = -ENOENT; 816 goto err_queue_init; 817 } 818 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 819 ret = vb2_queue_init(q); 820 if (ret) { 821 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 822 goto err_queue_init; 823 } 824 /* Init videobuf2 queue for OUTPUT */ 825 q = &ctx->vq_src; 826 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 827 q->io_modes = VB2_MMAP; 828 q->drv_priv = &ctx->fh; 829 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 830 q->io_modes = VB2_MMAP; 831 q->ops = get_dec_queue_ops(); 832 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 833 q->io_modes = VB2_MMAP | VB2_USERPTR; 834 q->ops = get_enc_queue_ops(); 835 } else { 836 ret = -ENOENT; 837 goto err_queue_init; 838 } 839 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 840 ret = vb2_queue_init(q); 841 if (ret) { 842 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 843 goto err_queue_init; 844 } 845 init_waitqueue_head(&ctx->queue); 846 mutex_unlock(&dev->mfc_mutex); 847 mfc_debug_leave(); 848 return ret; 849 /* Deinit when failure occured */ 850err_queue_init: 851err_init_hw: 852 s5p_mfc_release_firmware(dev); 853err_alloc_fw: 854 dev->ctx[ctx->num] = NULL; 855 del_timer_sync(&dev->watchdog_timer); 856 s5p_mfc_clock_off(); 857err_pwr_enable: 858 if (dev->num_inst == 1) { 859 if (s5p_mfc_power_off() < 0) 860 mfc_err("power off failed\n"); 861 s5p_mfc_release_firmware(dev); 862 } 863err_ctrls_setup: 864 s5p_mfc_dec_ctrls_delete(ctx); 865err_bad_node: 866err_no_ctx: 867 v4l2_fh_del(&ctx->fh); 868 v4l2_fh_exit(&ctx->fh); 869 kfree(ctx); 870err_alloc: 871 dev->num_inst--; 872 mutex_unlock(&dev->mfc_mutex); 873 mfc_debug_leave(); 874 return ret; 875} 876 877/* Release MFC context */ 878static int s5p_mfc_release(struct file *file) 879{ 880 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 881 struct s5p_mfc_dev *dev = ctx->dev; 882 883 mfc_debug_enter(); 884 mutex_lock(&dev->mfc_mutex); 885 s5p_mfc_clock_on(); 886 vb2_queue_release(&ctx->vq_src); 887 vb2_queue_release(&ctx->vq_dst); 888 /* Mark context as idle */ 889 clear_work_bit_irqsave(ctx); 890 /* If instance was initialised then 891 * return instance and free reosurces */ 892 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 893 mfc_debug(2, "Has to free instance\n"); 894 ctx->state = MFCINST_RETURN_INST; 895 set_work_bit_irqsave(ctx); 896 s5p_mfc_clean_ctx_int_flags(ctx); 897 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 898 /* Wait until instance is returned or timeout occured */ 899 if (s5p_mfc_wait_for_done_ctx 900 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 901 s5p_mfc_clock_off(); 902 mfc_err("Err returning instance\n"); 903 } 904 mfc_debug(2, "After free instance\n"); 905 /* Free resources */ 906 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 907 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 908 if (ctx->type == MFCINST_DECODER) 909 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 910 ctx); 911 912 ctx->inst_no = MFC_NO_INSTANCE_SET; 913 } 914 /* hardware locking scheme */ 915 if (dev->curr_ctx == ctx->num) 916 clear_bit(0, &dev->hw_lock); 917 dev->num_inst--; 918 if (dev->num_inst == 0) { 919 mfc_debug(2, "Last instance - release firmware\n"); 920 /* reset <-> F/W release */ 921 s5p_mfc_reset(dev); 922 s5p_mfc_deinit_hw(dev); 923 s5p_mfc_release_firmware(dev); 924 del_timer_sync(&dev->watchdog_timer); 925 if (s5p_mfc_power_off() < 0) 926 mfc_err("Power off failed\n"); 927 } 928 mfc_debug(2, "Shutting down clock\n"); 929 s5p_mfc_clock_off(); 930 dev->ctx[ctx->num] = NULL; 931 s5p_mfc_dec_ctrls_delete(ctx); 932 v4l2_fh_del(&ctx->fh); 933 v4l2_fh_exit(&ctx->fh); 934 kfree(ctx); 935 mfc_debug_leave(); 936 mutex_unlock(&dev->mfc_mutex); 937 return 0; 938} 939 940/* Poll */ 941static unsigned int s5p_mfc_poll(struct file *file, 942 struct poll_table_struct *wait) 943{ 944 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 945 struct s5p_mfc_dev *dev = ctx->dev; 946 struct vb2_queue *src_q, *dst_q; 947 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 948 unsigned int rc = 0; 949 unsigned long flags; 950 951 mutex_lock(&dev->mfc_mutex); 952 src_q = &ctx->vq_src; 953 dst_q = &ctx->vq_dst; 954 /* 955 * There has to be at least one buffer queued on each queued_list, which 956 * means either in driver already or waiting for driver to claim it 957 * and start processing. 958 */ 959 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 960 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 961 rc = POLLERR; 962 goto end; 963 } 964 mutex_unlock(&dev->mfc_mutex); 965 poll_wait(file, &ctx->fh.wait, wait); 966 poll_wait(file, &src_q->done_wq, wait); 967 poll_wait(file, &dst_q->done_wq, wait); 968 mutex_lock(&dev->mfc_mutex); 969 if (v4l2_event_pending(&ctx->fh)) 970 rc |= POLLPRI; 971 spin_lock_irqsave(&src_q->done_lock, flags); 972 if (!list_empty(&src_q->done_list)) 973 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 974 done_entry); 975 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 976 || src_vb->state == VB2_BUF_STATE_ERROR)) 977 rc |= POLLOUT | POLLWRNORM; 978 spin_unlock_irqrestore(&src_q->done_lock, flags); 979 spin_lock_irqsave(&dst_q->done_lock, flags); 980 if (!list_empty(&dst_q->done_list)) 981 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 982 done_entry); 983 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 984 || dst_vb->state == VB2_BUF_STATE_ERROR)) 985 rc |= POLLIN | POLLRDNORM; 986 spin_unlock_irqrestore(&dst_q->done_lock, flags); 987end: 988 mutex_unlock(&dev->mfc_mutex); 989 return rc; 990} 991 992/* Mmap */ 993static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 994{ 995 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 996 struct s5p_mfc_dev *dev = ctx->dev; 997 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 998 int ret; 999 1000 if (mutex_lock_interruptible(&dev->mfc_mutex)) 1001 return -ERESTARTSYS; 1002 if (offset < DST_QUEUE_OFF_BASE) { 1003 mfc_debug(2, "mmaping source\n"); 1004 ret = vb2_mmap(&ctx->vq_src, vma); 1005 } else { /* capture */ 1006 mfc_debug(2, "mmaping destination\n"); 1007 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 1008 ret = vb2_mmap(&ctx->vq_dst, vma); 1009 } 1010 mutex_unlock(&dev->mfc_mutex); 1011 return ret; 1012} 1013 1014/* v4l2 ops */ 1015static const struct v4l2_file_operations s5p_mfc_fops = { 1016 .owner = THIS_MODULE, 1017 .open = s5p_mfc_open, 1018 .release = s5p_mfc_release, 1019 .poll = s5p_mfc_poll, 1020 .unlocked_ioctl = video_ioctl2, 1021 .mmap = s5p_mfc_mmap, 1022}; 1023 1024static int match_child(struct device *dev, void *data) 1025{ 1026 if (!dev_name(dev)) 1027 return 0; 1028 return !strcmp(dev_name(dev), (char *)data); 1029} 1030 1031static void *mfc_get_drv_data(struct platform_device *pdev); 1032 1033/* MFC probe function */ 1034static int s5p_mfc_probe(struct platform_device *pdev) 1035{ 1036 struct s5p_mfc_dev *dev; 1037 struct video_device *vfd; 1038 struct resource *res; 1039 int ret; 1040 unsigned int mem_info[2]; 1041 1042 pr_debug("%s++\n", __func__); 1043 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1044 if (!dev) { 1045 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1046 return -ENOMEM; 1047 } 1048 1049 spin_lock_init(&dev->irqlock); 1050 spin_lock_init(&dev->condlock); 1051 dev->plat_dev = pdev; 1052 if (!dev->plat_dev) { 1053 dev_err(&pdev->dev, "No platform data specified\n"); 1054 return -ENODEV; 1055 } 1056 1057 dev->variant = mfc_get_drv_data(pdev); 1058 1059 ret = s5p_mfc_init_pm(dev); 1060 if (ret < 0) { 1061 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1062 return ret; 1063 } 1064 1065 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1066 1067 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res); 1068 if (dev->regs_base == NULL) { 1069 dev_err(&pdev->dev, "Failed to obtain io memory\n"); 1070 return -ENOENT; 1071 } 1072 1073 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1074 if (res == NULL) { 1075 dev_err(&pdev->dev, "failed to get irq resource\n"); 1076 ret = -ENOENT; 1077 goto err_res; 1078 } 1079 dev->irq = res->start; 1080 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1081 IRQF_DISABLED, pdev->name, dev); 1082 if (ret) { 1083 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1084 goto err_res; 1085 } 1086 1087 if (pdev->dev.of_node) { 1088 dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL); 1089 if (!dev->mem_dev_l) { 1090 mfc_err("Not enough memory\n"); 1091 ret = -ENOMEM; 1092 goto err_res; 1093 } 1094 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-l", 1095 mem_info, 2); 1096 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1097 mem_info[0], mem_info[1], 1098 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1099 mfc_err("Failed to declare coherent memory for\n" 1100 "MFC device\n"); 1101 ret = -ENOMEM; 1102 goto err_res; 1103 } 1104 1105 dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL); 1106 if (!dev->mem_dev_r) { 1107 mfc_err("Not enough memory\n"); 1108 ret = -ENOMEM; 1109 goto err_res; 1110 } 1111 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-r", 1112 mem_info, 2); 1113 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1114 mem_info[0], mem_info[1], 1115 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1116 pr_err("Failed to declare coherent memory for\n" 1117 "MFC device\n"); 1118 ret = -ENOMEM; 1119 goto err_res; 1120 } 1121 } else { 1122 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1123 "s5p-mfc-l", match_child); 1124 if (!dev->mem_dev_l) { 1125 mfc_err("Mem child (L) device get failed\n"); 1126 ret = -ENODEV; 1127 goto err_res; 1128 } 1129 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1130 "s5p-mfc-r", match_child); 1131 if (!dev->mem_dev_r) { 1132 mfc_err("Mem child (R) device get failed\n"); 1133 ret = -ENODEV; 1134 goto err_res; 1135 } 1136 } 1137 1138 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1139 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) { 1140 ret = PTR_ERR(dev->alloc_ctx[0]); 1141 goto err_res; 1142 } 1143 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1144 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) { 1145 ret = PTR_ERR(dev->alloc_ctx[1]); 1146 goto err_mem_init_ctx_1; 1147 } 1148 1149 mutex_init(&dev->mfc_mutex); 1150 1151 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1152 if (ret) 1153 goto err_v4l2_dev_reg; 1154 init_waitqueue_head(&dev->queue); 1155 1156 /* decoder */ 1157 vfd = video_device_alloc(); 1158 if (!vfd) { 1159 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1160 ret = -ENOMEM; 1161 goto err_dec_alloc; 1162 } 1163 vfd->fops = &s5p_mfc_fops, 1164 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1165 vfd->release = video_device_release, 1166 vfd->lock = &dev->mfc_mutex; 1167 vfd->v4l2_dev = &dev->v4l2_dev; 1168 vfd->vfl_dir = VFL_DIR_M2M; 1169 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1170 dev->vfd_dec = vfd; 1171 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1172 if (ret) { 1173 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1174 video_device_release(vfd); 1175 goto err_dec_reg; 1176 } 1177 v4l2_info(&dev->v4l2_dev, 1178 "decoder registered as /dev/video%d\n", vfd->num); 1179 video_set_drvdata(vfd, dev); 1180 1181 /* encoder */ 1182 vfd = video_device_alloc(); 1183 if (!vfd) { 1184 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1185 ret = -ENOMEM; 1186 goto err_enc_alloc; 1187 } 1188 vfd->fops = &s5p_mfc_fops, 1189 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1190 vfd->release = video_device_release, 1191 vfd->lock = &dev->mfc_mutex; 1192 vfd->v4l2_dev = &dev->v4l2_dev; 1193 vfd->vfl_dir = VFL_DIR_M2M; 1194 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1195 dev->vfd_enc = vfd; 1196 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1197 if (ret) { 1198 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1199 video_device_release(vfd); 1200 goto err_enc_reg; 1201 } 1202 v4l2_info(&dev->v4l2_dev, 1203 "encoder registered as /dev/video%d\n", vfd->num); 1204 video_set_drvdata(vfd, dev); 1205 platform_set_drvdata(pdev, dev); 1206 1207 dev->hw_lock = 0; 1208 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1209 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1210 atomic_set(&dev->watchdog_cnt, 0); 1211 init_timer(&dev->watchdog_timer); 1212 dev->watchdog_timer.data = (unsigned long)dev; 1213 dev->watchdog_timer.function = s5p_mfc_watchdog; 1214 1215 /* Initialize HW ops and commands based on MFC version */ 1216 s5p_mfc_init_hw_ops(dev); 1217 s5p_mfc_init_hw_cmds(dev); 1218 1219 pr_debug("%s--\n", __func__); 1220 return 0; 1221 1222/* Deinit MFC if probe had failed */ 1223err_enc_reg: 1224 video_device_release(dev->vfd_enc); 1225err_enc_alloc: 1226 video_unregister_device(dev->vfd_dec); 1227err_dec_reg: 1228 video_device_release(dev->vfd_dec); 1229err_dec_alloc: 1230 v4l2_device_unregister(&dev->v4l2_dev); 1231err_v4l2_dev_reg: 1232 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1233err_mem_init_ctx_1: 1234 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1235err_res: 1236 s5p_mfc_final_pm(dev); 1237 1238 pr_debug("%s-- with error\n", __func__); 1239 return ret; 1240 1241} 1242 1243/* Remove the driver */ 1244static int __devexit s5p_mfc_remove(struct platform_device *pdev) 1245{ 1246 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1247 1248 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1249 1250 del_timer_sync(&dev->watchdog_timer); 1251 flush_workqueue(dev->watchdog_workqueue); 1252 destroy_workqueue(dev->watchdog_workqueue); 1253 1254 video_unregister_device(dev->vfd_enc); 1255 video_unregister_device(dev->vfd_dec); 1256 v4l2_device_unregister(&dev->v4l2_dev); 1257 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1258 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1259 1260 s5p_mfc_final_pm(dev); 1261 return 0; 1262} 1263 1264#ifdef CONFIG_PM_SLEEP 1265 1266static int s5p_mfc_suspend(struct device *dev) 1267{ 1268 struct platform_device *pdev = to_platform_device(dev); 1269 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1270 int ret; 1271 1272 if (m_dev->num_inst == 0) 1273 return 0; 1274 1275 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1276 mfc_err("Error: going to suspend for a second time\n"); 1277 return -EIO; 1278 } 1279 1280 /* Check if we're processing then wait if it necessary. */ 1281 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1282 /* Try and lock the HW */ 1283 /* Wait on the interrupt waitqueue */ 1284 ret = wait_event_interruptible_timeout(m_dev->queue, 1285 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1286 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1287 1288 if (ret == 0) { 1289 mfc_err("Waiting for hardware to finish timed out\n"); 1290 return -EIO; 1291 } 1292 } 1293 1294 return s5p_mfc_sleep(m_dev); 1295} 1296 1297static int s5p_mfc_resume(struct device *dev) 1298{ 1299 struct platform_device *pdev = to_platform_device(dev); 1300 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1301 1302 if (m_dev->num_inst == 0) 1303 return 0; 1304 return s5p_mfc_wakeup(m_dev); 1305} 1306#endif 1307 1308#ifdef CONFIG_PM_RUNTIME 1309static int s5p_mfc_runtime_suspend(struct device *dev) 1310{ 1311 struct platform_device *pdev = to_platform_device(dev); 1312 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1313 1314 atomic_set(&m_dev->pm.power, 0); 1315 return 0; 1316} 1317 1318static int s5p_mfc_runtime_resume(struct device *dev) 1319{ 1320 struct platform_device *pdev = to_platform_device(dev); 1321 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1322 int pre_power; 1323 1324 if (!m_dev->alloc_ctx) 1325 return 0; 1326 pre_power = atomic_read(&m_dev->pm.power); 1327 atomic_set(&m_dev->pm.power, 1); 1328 return 0; 1329} 1330#endif 1331 1332/* Power management */ 1333static const struct dev_pm_ops s5p_mfc_pm_ops = { 1334 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1335 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1336 NULL) 1337}; 1338 1339struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1340 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1341 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1342 .dsc = DESC_BUF_SIZE, 1343 .shm = SHARED_BUF_SIZE, 1344}; 1345 1346struct s5p_mfc_buf_size buf_size_v5 = { 1347 .fw = MAX_FW_SIZE, 1348 .cpb = MAX_CPB_SIZE, 1349 .priv = &mfc_buf_size_v5, 1350}; 1351 1352struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1353 .base = MFC_BASE_ALIGN_ORDER, 1354}; 1355 1356static struct s5p_mfc_variant mfc_drvdata_v5 = { 1357 .version = MFC_VERSION, 1358 .port_num = MFC_NUM_PORTS, 1359 .buf_size = &buf_size_v5, 1360 .buf_align = &mfc_buf_align_v5, 1361 .mclk_name = "sclk_mfc", 1362 .fw_name = "s5p-mfc.fw", 1363}; 1364 1365struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1366 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1367 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1368 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1369 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1370 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1371}; 1372 1373struct s5p_mfc_buf_size buf_size_v6 = { 1374 .fw = MAX_FW_SIZE_V6, 1375 .cpb = MAX_CPB_SIZE_V6, 1376 .priv = &mfc_buf_size_v6, 1377}; 1378 1379struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1380 .base = 0, 1381}; 1382 1383static struct s5p_mfc_variant mfc_drvdata_v6 = { 1384 .version = MFC_VERSION_V6, 1385 .port_num = MFC_NUM_PORTS_V6, 1386 .buf_size = &buf_size_v6, 1387 .buf_align = &mfc_buf_align_v6, 1388 .mclk_name = "aclk_333", 1389 .fw_name = "s5p-mfc-v6.fw", 1390}; 1391 1392static struct platform_device_id mfc_driver_ids[] = { 1393 { 1394 .name = "s5p-mfc", 1395 .driver_data = (unsigned long)&mfc_drvdata_v5, 1396 }, { 1397 .name = "s5p-mfc-v5", 1398 .driver_data = (unsigned long)&mfc_drvdata_v5, 1399 }, { 1400 .name = "s5p-mfc-v6", 1401 .driver_data = (unsigned long)&mfc_drvdata_v6, 1402 }, 1403 {}, 1404}; 1405MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1406 1407static const struct of_device_id exynos_mfc_match[] = { 1408 { 1409 .compatible = "samsung,mfc-v5", 1410 .data = &mfc_drvdata_v5, 1411 }, { 1412 .compatible = "samsung,mfc-v6", 1413 .data = &mfc_drvdata_v6, 1414 }, 1415 {}, 1416}; 1417MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1418 1419static void *mfc_get_drv_data(struct platform_device *pdev) 1420{ 1421 struct s5p_mfc_variant *driver_data = NULL; 1422 1423 if (pdev->dev.of_node) { 1424 const struct of_device_id *match; 1425 match = of_match_node(of_match_ptr(exynos_mfc_match), 1426 pdev->dev.of_node); 1427 if (match) 1428 driver_data = (struct s5p_mfc_variant *)match->data; 1429 } else { 1430 driver_data = (struct s5p_mfc_variant *) 1431 platform_get_device_id(pdev)->driver_data; 1432 } 1433 return driver_data; 1434} 1435 1436static struct platform_driver s5p_mfc_driver = { 1437 .probe = s5p_mfc_probe, 1438 .remove = __devexit_p(s5p_mfc_remove), 1439 .id_table = mfc_driver_ids, 1440 .driver = { 1441 .name = S5P_MFC_NAME, 1442 .owner = THIS_MODULE, 1443 .pm = &s5p_mfc_pm_ops, 1444 .of_match_table = exynos_mfc_match, 1445 }, 1446}; 1447 1448module_platform_driver(s5p_mfc_driver); 1449 1450MODULE_LICENSE("GPL"); 1451MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1452MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1453 1454