s5p_mfc.c revision d0ce898c39bf070ad59751df36206b5ccd3d1c03
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 181{ 182 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 183 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 184 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 185} 186 187static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 188{ 189 struct s5p_mfc_buf *dst_buf; 190 struct s5p_mfc_dev *dev = ctx->dev; 191 192 ctx->state = MFCINST_FINISHED; 193 ctx->sequence++; 194 while (!list_empty(&ctx->dst_queue)) { 195 dst_buf = list_entry(ctx->dst_queue.next, 196 struct s5p_mfc_buf, list); 197 mfc_debug(2, "Cleaning up buffer: %d\n", 198 dst_buf->b->v4l2_buf.index); 199 vb2_set_plane_payload(dst_buf->b, 0, 0); 200 vb2_set_plane_payload(dst_buf->b, 1, 0); 201 list_del(&dst_buf->list); 202 ctx->dst_queue_cnt--; 203 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 204 205 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 206 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 207 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 208 else 209 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 210 211 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 212 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 213 } 214} 215 216static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 217{ 218 struct s5p_mfc_dev *dev = ctx->dev; 219 struct s5p_mfc_buf *dst_buf, *src_buf; 220 size_t dec_y_addr; 221 unsigned int frame_type; 222 223 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 224 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 225 226 /* Copy timestamp / timecode from decoded src to dst and set 227 appropriate flags */ 228 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 229 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 230 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 231 dst_buf->b->v4l2_buf.timecode = 232 src_buf->b->v4l2_buf.timecode; 233 dst_buf->b->v4l2_buf.timestamp = 234 src_buf->b->v4l2_buf.timestamp; 235 dst_buf->b->v4l2_buf.flags &= 236 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 237 dst_buf->b->v4l2_buf.flags |= 238 src_buf->b->v4l2_buf.flags 239 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 240 switch (frame_type) { 241 case S5P_FIMV_DECODE_FRAME_I_FRAME: 242 dst_buf->b->v4l2_buf.flags |= 243 V4L2_BUF_FLAG_KEYFRAME; 244 break; 245 case S5P_FIMV_DECODE_FRAME_P_FRAME: 246 dst_buf->b->v4l2_buf.flags |= 247 V4L2_BUF_FLAG_PFRAME; 248 break; 249 case S5P_FIMV_DECODE_FRAME_B_FRAME: 250 dst_buf->b->v4l2_buf.flags |= 251 V4L2_BUF_FLAG_BFRAME; 252 break; 253 } 254 break; 255 } 256 } 257} 258 259static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 260{ 261 struct s5p_mfc_dev *dev = ctx->dev; 262 struct s5p_mfc_buf *dst_buf; 263 size_t dspl_y_addr; 264 unsigned int frame_type; 265 266 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 267 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_disp_frame_type, ctx); 268 269 /* If frame is same as previous then skip and do not dequeue */ 270 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 271 if (!ctx->after_packed_pb) 272 ctx->sequence++; 273 ctx->after_packed_pb = 0; 274 return; 275 } 276 ctx->sequence++; 277 /* The MFC returns address of the buffer, now we have to 278 * check which videobuf does it correspond to */ 279 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 280 /* Check if this is the buffer we're looking for */ 281 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 282 list_del(&dst_buf->list); 283 ctx->dst_queue_cnt--; 284 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 285 if (s5p_mfc_hw_call(dev->mfc_ops, 286 get_pic_type_top, ctx) == 287 s5p_mfc_hw_call(dev->mfc_ops, 288 get_pic_type_bot, ctx)) 289 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 290 else 291 dst_buf->b->v4l2_buf.field = 292 V4L2_FIELD_INTERLACED; 293 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 294 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 295 clear_bit(dst_buf->b->v4l2_buf.index, 296 &ctx->dec_dst_flag); 297 298 vb2_buffer_done(dst_buf->b, 299 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 300 301 break; 302 } 303 } 304} 305 306/* Handle frame decoding interrupt */ 307static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 308 unsigned int reason, unsigned int err) 309{ 310 struct s5p_mfc_dev *dev = ctx->dev; 311 unsigned int dst_frame_status; 312 struct s5p_mfc_buf *src_buf; 313 unsigned long flags; 314 unsigned int res_change; 315 316 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 317 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 318 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 319 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 320 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 321 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 322 if (ctx->state == MFCINST_RES_CHANGE_INIT) 323 ctx->state = MFCINST_RES_CHANGE_FLUSH; 324 if (res_change == S5P_FIMV_RES_INCREASE || 325 res_change == S5P_FIMV_RES_DECREASE) { 326 ctx->state = MFCINST_RES_CHANGE_INIT; 327 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 328 wake_up_ctx(ctx, reason, err); 329 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 330 BUG(); 331 s5p_mfc_clock_off(); 332 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 333 return; 334 } 335 if (ctx->dpb_flush_flag) 336 ctx->dpb_flush_flag = 0; 337 338 spin_lock_irqsave(&dev->irqlock, flags); 339 /* All frames remaining in the buffer have been extracted */ 340 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 341 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 342 s5p_mfc_handle_frame_all_extracted(ctx); 343 ctx->state = MFCINST_RES_CHANGE_END; 344 goto leave_handle_frame; 345 } else { 346 s5p_mfc_handle_frame_all_extracted(ctx); 347 } 348 } 349 350 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 351 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 352 s5p_mfc_handle_frame_copy_time(ctx); 353 354 /* A frame has been decoded and is in the buffer */ 355 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 356 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 357 s5p_mfc_handle_frame_new(ctx, err); 358 } else { 359 mfc_debug(2, "No frame decode\n"); 360 } 361 /* Mark source buffer as complete */ 362 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 363 && !list_empty(&ctx->src_queue)) { 364 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 365 list); 366 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 367 get_consumed_stream, dev); 368 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 369 ctx->consumed_stream + STUFF_BYTE < 370 src_buf->b->v4l2_planes[0].bytesused) { 371 /* Run MFC again on the same buffer */ 372 mfc_debug(2, "Running again the same buffer\n"); 373 ctx->after_packed_pb = 1; 374 } else { 375 mfc_debug(2, "MFC needs next buffer\n"); 376 ctx->consumed_stream = 0; 377 if (src_buf->flags & MFC_BUF_FLAG_EOS) 378 ctx->state = MFCINST_FINISHING; 379 list_del(&src_buf->list); 380 ctx->src_queue_cnt--; 381 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 382 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 383 else 384 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 385 } 386 } 387leave_handle_frame: 388 spin_unlock_irqrestore(&dev->irqlock, flags); 389 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 390 || ctx->dst_queue_cnt < ctx->pb_count) 391 clear_work_bit(ctx); 392 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 393 wake_up_ctx(ctx, reason, err); 394 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 395 BUG(); 396 s5p_mfc_clock_off(); 397 /* if suspending, wake up device and do not try_run again*/ 398 if (test_bit(0, &dev->enter_suspend)) 399 wake_up_dev(dev, reason, err); 400 else 401 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 402} 403 404/* Error handling for interrupt */ 405static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 406 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 407{ 408 unsigned long flags; 409 410 mfc_err("Interrupt Error: %08x\n", err); 411 412 if (ctx != NULL) { 413 /* Error recovery is dependent on the state of context */ 414 switch (ctx->state) { 415 case MFCINST_RES_CHANGE_INIT: 416 case MFCINST_RES_CHANGE_FLUSH: 417 case MFCINST_RES_CHANGE_END: 418 case MFCINST_FINISHING: 419 case MFCINST_FINISHED: 420 case MFCINST_RUNNING: 421 /* It is highly probable that an error occurred 422 * while decoding a frame */ 423 clear_work_bit(ctx); 424 ctx->state = MFCINST_ERROR; 425 /* Mark all dst buffers as having an error */ 426 spin_lock_irqsave(&dev->irqlock, flags); 427 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 428 &ctx->dst_queue, &ctx->vq_dst); 429 /* Mark all src buffers as having an error */ 430 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 431 &ctx->src_queue, &ctx->vq_src); 432 spin_unlock_irqrestore(&dev->irqlock, flags); 433 wake_up_ctx(ctx, reason, err); 434 break; 435 default: 436 clear_work_bit(ctx); 437 ctx->state = MFCINST_ERROR; 438 wake_up_ctx(ctx, reason, err); 439 break; 440 } 441 } 442 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 443 BUG(); 444 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 445 s5p_mfc_clock_off(); 446 wake_up_dev(dev, reason, err); 447 return; 448} 449 450/* Header parsing interrupt handling */ 451static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 452 unsigned int reason, unsigned int err) 453{ 454 struct s5p_mfc_dev *dev; 455 456 if (ctx == NULL) 457 return; 458 dev = ctx->dev; 459 if (ctx->c_ops->post_seq_start) { 460 if (ctx->c_ops->post_seq_start(ctx)) 461 mfc_err("post_seq_start() failed\n"); 462 } else { 463 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 464 dev); 465 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 466 dev); 467 468 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 469 470 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 471 dev); 472 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 473 dev); 474 if (ctx->img_width == 0 || ctx->img_height == 0) 475 ctx->state = MFCINST_ERROR; 476 else 477 ctx->state = MFCINST_HEAD_PARSED; 478 479 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 480 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 481 !list_empty(&ctx->src_queue)) { 482 struct s5p_mfc_buf *src_buf; 483 src_buf = list_entry(ctx->src_queue.next, 484 struct s5p_mfc_buf, list); 485 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 486 dev) < 487 src_buf->b->v4l2_planes[0].bytesused) 488 ctx->head_processed = 0; 489 else 490 ctx->head_processed = 1; 491 } else { 492 ctx->head_processed = 1; 493 } 494 } 495 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 496 clear_work_bit(ctx); 497 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 498 BUG(); 499 s5p_mfc_clock_off(); 500 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 501 wake_up_ctx(ctx, reason, err); 502} 503 504/* Header parsing interrupt handling */ 505static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 506 unsigned int reason, unsigned int err) 507{ 508 struct s5p_mfc_buf *src_buf; 509 struct s5p_mfc_dev *dev; 510 unsigned long flags; 511 512 if (ctx == NULL) 513 return; 514 dev = ctx->dev; 515 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 516 ctx->int_type = reason; 517 ctx->int_err = err; 518 ctx->int_cond = 1; 519 clear_work_bit(ctx); 520 if (err == 0) { 521 ctx->state = MFCINST_RUNNING; 522 if (!ctx->dpb_flush_flag && ctx->head_processed) { 523 spin_lock_irqsave(&dev->irqlock, flags); 524 if (!list_empty(&ctx->src_queue)) { 525 src_buf = list_entry(ctx->src_queue.next, 526 struct s5p_mfc_buf, list); 527 list_del(&src_buf->list); 528 ctx->src_queue_cnt--; 529 vb2_buffer_done(src_buf->b, 530 VB2_BUF_STATE_DONE); 531 } 532 spin_unlock_irqrestore(&dev->irqlock, flags); 533 } else { 534 ctx->dpb_flush_flag = 0; 535 } 536 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 537 BUG(); 538 539 s5p_mfc_clock_off(); 540 541 wake_up(&ctx->queue); 542 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 543 } else { 544 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 545 BUG(); 546 547 s5p_mfc_clock_off(); 548 549 wake_up(&ctx->queue); 550 } 551} 552 553static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 554 unsigned int reason, unsigned int err) 555{ 556 struct s5p_mfc_dev *dev = ctx->dev; 557 struct s5p_mfc_buf *mb_entry; 558 559 mfc_debug(2, "Stream completed\n"); 560 561 s5p_mfc_clear_int_flags(dev); 562 ctx->int_type = reason; 563 ctx->int_err = err; 564 ctx->state = MFCINST_FINISHED; 565 566 spin_lock(&dev->irqlock); 567 if (!list_empty(&ctx->dst_queue)) { 568 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 569 list); 570 list_del(&mb_entry->list); 571 ctx->dst_queue_cnt--; 572 vb2_set_plane_payload(mb_entry->b, 0, 0); 573 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 574 } 575 spin_unlock(&dev->irqlock); 576 577 clear_work_bit(ctx); 578 579 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); 580 581 s5p_mfc_clock_off(); 582 wake_up(&ctx->queue); 583 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 584} 585 586/* Interrupt processing */ 587static irqreturn_t s5p_mfc_irq(int irq, void *priv) 588{ 589 struct s5p_mfc_dev *dev = priv; 590 struct s5p_mfc_ctx *ctx; 591 unsigned int reason; 592 unsigned int err; 593 594 mfc_debug_enter(); 595 /* Reset the timeout watchdog */ 596 atomic_set(&dev->watchdog_cnt, 0); 597 ctx = dev->ctx[dev->curr_ctx]; 598 /* Get the reason of interrupt and the error code */ 599 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 600 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 601 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 602 switch (reason) { 603 case S5P_MFC_R2H_CMD_ERR_RET: 604 /* An error has occurred */ 605 if (ctx->state == MFCINST_RUNNING && 606 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 607 dev->warn_start) 608 s5p_mfc_handle_frame(ctx, reason, err); 609 else 610 s5p_mfc_handle_error(dev, ctx, reason, err); 611 clear_bit(0, &dev->enter_suspend); 612 break; 613 614 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 615 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 616 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 617 if (ctx->c_ops->post_frame_start) { 618 if (ctx->c_ops->post_frame_start(ctx)) 619 mfc_err("post_frame_start() failed\n"); 620 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 621 wake_up_ctx(ctx, reason, err); 622 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 623 BUG(); 624 s5p_mfc_clock_off(); 625 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 626 } else { 627 s5p_mfc_handle_frame(ctx, reason, err); 628 } 629 break; 630 631 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 632 s5p_mfc_handle_seq_done(ctx, reason, err); 633 break; 634 635 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 636 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 637 ctx->state = MFCINST_GOT_INST; 638 clear_work_bit(ctx); 639 wake_up(&ctx->queue); 640 goto irq_cleanup_hw; 641 642 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 643 clear_work_bit(ctx); 644 ctx->state = MFCINST_FREE; 645 wake_up(&ctx->queue); 646 goto irq_cleanup_hw; 647 648 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 649 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 650 case S5P_MFC_R2H_CMD_SLEEP_RET: 651 case S5P_MFC_R2H_CMD_WAKEUP_RET: 652 if (ctx) 653 clear_work_bit(ctx); 654 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 655 wake_up_dev(dev, reason, err); 656 clear_bit(0, &dev->hw_lock); 657 clear_bit(0, &dev->enter_suspend); 658 break; 659 660 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 661 s5p_mfc_handle_init_buffers(ctx, reason, err); 662 break; 663 664 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 665 s5p_mfc_handle_stream_complete(ctx, reason, err); 666 break; 667 668 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 669 clear_work_bit(ctx); 670 ctx->state = MFCINST_RUNNING; 671 wake_up(&ctx->queue); 672 goto irq_cleanup_hw; 673 674 default: 675 mfc_debug(2, "Unknown int reason\n"); 676 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 677 } 678 mfc_debug_leave(); 679 return IRQ_HANDLED; 680irq_cleanup_hw: 681 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 682 ctx->int_type = reason; 683 ctx->int_err = err; 684 ctx->int_cond = 1; 685 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 686 mfc_err("Failed to unlock hw\n"); 687 688 s5p_mfc_clock_off(); 689 690 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 691 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 692 return IRQ_HANDLED; 693} 694 695/* Open an MFC node */ 696static int s5p_mfc_open(struct file *file) 697{ 698 struct video_device *vdev = video_devdata(file); 699 struct s5p_mfc_dev *dev = video_drvdata(file); 700 struct s5p_mfc_ctx *ctx = NULL; 701 struct vb2_queue *q; 702 int ret = 0; 703 704 mfc_debug_enter(); 705 if (mutex_lock_interruptible(&dev->mfc_mutex)) 706 return -ERESTARTSYS; 707 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 708 /* Allocate memory for context */ 709 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 710 if (!ctx) { 711 mfc_err("Not enough memory\n"); 712 ret = -ENOMEM; 713 goto err_alloc; 714 } 715 v4l2_fh_init(&ctx->fh, video_devdata(file)); 716 file->private_data = &ctx->fh; 717 v4l2_fh_add(&ctx->fh); 718 ctx->dev = dev; 719 INIT_LIST_HEAD(&ctx->src_queue); 720 INIT_LIST_HEAD(&ctx->dst_queue); 721 ctx->src_queue_cnt = 0; 722 ctx->dst_queue_cnt = 0; 723 /* Get context number */ 724 ctx->num = 0; 725 while (dev->ctx[ctx->num]) { 726 ctx->num++; 727 if (ctx->num >= MFC_NUM_CONTEXTS) { 728 mfc_err("Too many open contexts\n"); 729 ret = -EBUSY; 730 goto err_no_ctx; 731 } 732 } 733 /* Mark context as idle */ 734 clear_work_bit_irqsave(ctx); 735 dev->ctx[ctx->num] = ctx; 736 if (vdev == dev->vfd_dec) { 737 ctx->type = MFCINST_DECODER; 738 ctx->c_ops = get_dec_codec_ops(); 739 s5p_mfc_dec_init(ctx); 740 /* Setup ctrl handler */ 741 ret = s5p_mfc_dec_ctrls_setup(ctx); 742 if (ret) { 743 mfc_err("Failed to setup mfc controls\n"); 744 goto err_ctrls_setup; 745 } 746 } else if (vdev == dev->vfd_enc) { 747 ctx->type = MFCINST_ENCODER; 748 ctx->c_ops = get_enc_codec_ops(); 749 /* only for encoder */ 750 INIT_LIST_HEAD(&ctx->ref_queue); 751 ctx->ref_queue_cnt = 0; 752 s5p_mfc_enc_init(ctx); 753 /* Setup ctrl handler */ 754 ret = s5p_mfc_enc_ctrls_setup(ctx); 755 if (ret) { 756 mfc_err("Failed to setup mfc controls\n"); 757 goto err_ctrls_setup; 758 } 759 } else { 760 ret = -ENOENT; 761 goto err_bad_node; 762 } 763 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 764 ctx->inst_no = -1; 765 /* Load firmware if this is the first instance */ 766 if (dev->num_inst == 1) { 767 dev->watchdog_timer.expires = jiffies + 768 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 769 add_timer(&dev->watchdog_timer); 770 ret = s5p_mfc_power_on(); 771 if (ret < 0) { 772 mfc_err("power on failed\n"); 773 goto err_pwr_enable; 774 } 775 s5p_mfc_clock_on(); 776 ret = s5p_mfc_load_firmware(dev); 777 if (ret) { 778 s5p_mfc_clock_off(); 779 goto err_load_fw; 780 } 781 /* Init the FW */ 782 ret = s5p_mfc_init_hw(dev); 783 s5p_mfc_clock_off(); 784 if (ret) 785 goto err_init_hw; 786 } 787 /* Init videobuf2 queue for CAPTURE */ 788 q = &ctx->vq_dst; 789 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 790 q->drv_priv = &ctx->fh; 791 if (vdev == dev->vfd_dec) { 792 q->io_modes = VB2_MMAP; 793 q->ops = get_dec_queue_ops(); 794 } else if (vdev == dev->vfd_enc) { 795 q->io_modes = VB2_MMAP | VB2_USERPTR; 796 q->ops = get_enc_queue_ops(); 797 } else { 798 ret = -ENOENT; 799 goto err_queue_init; 800 } 801 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 802 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 803 ret = vb2_queue_init(q); 804 if (ret) { 805 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 806 goto err_queue_init; 807 } 808 /* Init videobuf2 queue for OUTPUT */ 809 q = &ctx->vq_src; 810 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 811 q->io_modes = VB2_MMAP; 812 q->drv_priv = &ctx->fh; 813 if (vdev == dev->vfd_dec) { 814 q->io_modes = VB2_MMAP; 815 q->ops = get_dec_queue_ops(); 816 } else if (vdev == dev->vfd_enc) { 817 q->io_modes = VB2_MMAP | VB2_USERPTR; 818 q->ops = get_enc_queue_ops(); 819 } else { 820 ret = -ENOENT; 821 goto err_queue_init; 822 } 823 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 824 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 825 ret = vb2_queue_init(q); 826 if (ret) { 827 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 828 goto err_queue_init; 829 } 830 init_waitqueue_head(&ctx->queue); 831 mutex_unlock(&dev->mfc_mutex); 832 mfc_debug_leave(); 833 return ret; 834 /* Deinit when failure occurred */ 835err_queue_init: 836 if (dev->num_inst == 1) 837 s5p_mfc_deinit_hw(dev); 838err_init_hw: 839err_load_fw: 840err_pwr_enable: 841 if (dev->num_inst == 1) { 842 if (s5p_mfc_power_off() < 0) 843 mfc_err("power off failed\n"); 844 del_timer_sync(&dev->watchdog_timer); 845 } 846err_ctrls_setup: 847 s5p_mfc_dec_ctrls_delete(ctx); 848err_bad_node: 849 dev->ctx[ctx->num] = NULL; 850err_no_ctx: 851 v4l2_fh_del(&ctx->fh); 852 v4l2_fh_exit(&ctx->fh); 853 kfree(ctx); 854err_alloc: 855 dev->num_inst--; 856 mutex_unlock(&dev->mfc_mutex); 857 mfc_debug_leave(); 858 return ret; 859} 860 861/* Release MFC context */ 862static int s5p_mfc_release(struct file *file) 863{ 864 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 865 struct s5p_mfc_dev *dev = ctx->dev; 866 867 mfc_debug_enter(); 868 mutex_lock(&dev->mfc_mutex); 869 s5p_mfc_clock_on(); 870 vb2_queue_release(&ctx->vq_src); 871 vb2_queue_release(&ctx->vq_dst); 872 /* Mark context as idle */ 873 clear_work_bit_irqsave(ctx); 874 /* If instance was initialised then 875 * return instance and free resources */ 876 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 877 mfc_debug(2, "Has to free instance\n"); 878 ctx->state = MFCINST_RETURN_INST; 879 set_work_bit_irqsave(ctx); 880 s5p_mfc_clean_ctx_int_flags(ctx); 881 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 882 /* Wait until instance is returned or timeout occurred */ 883 if (s5p_mfc_wait_for_done_ctx 884 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 885 s5p_mfc_clock_off(); 886 mfc_err("Err returning instance\n"); 887 } 888 mfc_debug(2, "After free instance\n"); 889 /* Free resources */ 890 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 891 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 892 if (ctx->type == MFCINST_DECODER) 893 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 894 ctx); 895 896 ctx->inst_no = MFC_NO_INSTANCE_SET; 897 } 898 /* hardware locking scheme */ 899 if (dev->curr_ctx == ctx->num) 900 clear_bit(0, &dev->hw_lock); 901 dev->num_inst--; 902 if (dev->num_inst == 0) { 903 mfc_debug(2, "Last instance\n"); 904 s5p_mfc_deinit_hw(dev); 905 del_timer_sync(&dev->watchdog_timer); 906 if (s5p_mfc_power_off() < 0) 907 mfc_err("Power off failed\n"); 908 } 909 mfc_debug(2, "Shutting down clock\n"); 910 s5p_mfc_clock_off(); 911 dev->ctx[ctx->num] = NULL; 912 s5p_mfc_dec_ctrls_delete(ctx); 913 v4l2_fh_del(&ctx->fh); 914 v4l2_fh_exit(&ctx->fh); 915 kfree(ctx); 916 mfc_debug_leave(); 917 mutex_unlock(&dev->mfc_mutex); 918 return 0; 919} 920 921/* Poll */ 922static unsigned int s5p_mfc_poll(struct file *file, 923 struct poll_table_struct *wait) 924{ 925 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 926 struct s5p_mfc_dev *dev = ctx->dev; 927 struct vb2_queue *src_q, *dst_q; 928 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 929 unsigned int rc = 0; 930 unsigned long flags; 931 932 mutex_lock(&dev->mfc_mutex); 933 src_q = &ctx->vq_src; 934 dst_q = &ctx->vq_dst; 935 /* 936 * There has to be at least one buffer queued on each queued_list, which 937 * means either in driver already or waiting for driver to claim it 938 * and start processing. 939 */ 940 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 941 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 942 rc = POLLERR; 943 goto end; 944 } 945 mutex_unlock(&dev->mfc_mutex); 946 poll_wait(file, &ctx->fh.wait, wait); 947 poll_wait(file, &src_q->done_wq, wait); 948 poll_wait(file, &dst_q->done_wq, wait); 949 mutex_lock(&dev->mfc_mutex); 950 if (v4l2_event_pending(&ctx->fh)) 951 rc |= POLLPRI; 952 spin_lock_irqsave(&src_q->done_lock, flags); 953 if (!list_empty(&src_q->done_list)) 954 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 955 done_entry); 956 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 957 || src_vb->state == VB2_BUF_STATE_ERROR)) 958 rc |= POLLOUT | POLLWRNORM; 959 spin_unlock_irqrestore(&src_q->done_lock, flags); 960 spin_lock_irqsave(&dst_q->done_lock, flags); 961 if (!list_empty(&dst_q->done_list)) 962 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 963 done_entry); 964 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 965 || dst_vb->state == VB2_BUF_STATE_ERROR)) 966 rc |= POLLIN | POLLRDNORM; 967 spin_unlock_irqrestore(&dst_q->done_lock, flags); 968end: 969 mutex_unlock(&dev->mfc_mutex); 970 return rc; 971} 972 973/* Mmap */ 974static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 975{ 976 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 977 struct s5p_mfc_dev *dev = ctx->dev; 978 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 979 int ret; 980 981 if (mutex_lock_interruptible(&dev->mfc_mutex)) 982 return -ERESTARTSYS; 983 if (offset < DST_QUEUE_OFF_BASE) { 984 mfc_debug(2, "mmaping source\n"); 985 ret = vb2_mmap(&ctx->vq_src, vma); 986 } else { /* capture */ 987 mfc_debug(2, "mmaping destination\n"); 988 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 989 ret = vb2_mmap(&ctx->vq_dst, vma); 990 } 991 mutex_unlock(&dev->mfc_mutex); 992 return ret; 993} 994 995/* v4l2 ops */ 996static const struct v4l2_file_operations s5p_mfc_fops = { 997 .owner = THIS_MODULE, 998 .open = s5p_mfc_open, 999 .release = s5p_mfc_release, 1000 .poll = s5p_mfc_poll, 1001 .unlocked_ioctl = video_ioctl2, 1002 .mmap = s5p_mfc_mmap, 1003}; 1004 1005static int match_child(struct device *dev, void *data) 1006{ 1007 if (!dev_name(dev)) 1008 return 0; 1009 return !strcmp(dev_name(dev), (char *)data); 1010} 1011 1012static void *mfc_get_drv_data(struct platform_device *pdev); 1013 1014static int s5p_mfc_alloc_memdevs(struct s5p_mfc_dev *dev) 1015{ 1016 unsigned int mem_info[2] = { }; 1017 1018 dev->mem_dev_l = devm_kzalloc(&dev->plat_dev->dev, 1019 sizeof(struct device), GFP_KERNEL); 1020 if (!dev->mem_dev_l) { 1021 mfc_err("Not enough memory\n"); 1022 return -ENOMEM; 1023 } 1024 device_initialize(dev->mem_dev_l); 1025 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1026 "samsung,mfc-l", mem_info, 2); 1027 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1028 mem_info[0], mem_info[1], 1029 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1030 mfc_err("Failed to declare coherent memory for\n" 1031 "MFC device\n"); 1032 return -ENOMEM; 1033 } 1034 1035 dev->mem_dev_r = devm_kzalloc(&dev->plat_dev->dev, 1036 sizeof(struct device), GFP_KERNEL); 1037 if (!dev->mem_dev_r) { 1038 mfc_err("Not enough memory\n"); 1039 return -ENOMEM; 1040 } 1041 device_initialize(dev->mem_dev_r); 1042 of_property_read_u32_array(dev->plat_dev->dev.of_node, 1043 "samsung,mfc-r", mem_info, 2); 1044 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1045 mem_info[0], mem_info[1], 1046 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1047 pr_err("Failed to declare coherent memory for\n" 1048 "MFC device\n"); 1049 return -ENOMEM; 1050 } 1051 return 0; 1052} 1053 1054/* MFC probe function */ 1055static int s5p_mfc_probe(struct platform_device *pdev) 1056{ 1057 struct s5p_mfc_dev *dev; 1058 struct video_device *vfd; 1059 struct resource *res; 1060 int ret; 1061 1062 pr_debug("%s++\n", __func__); 1063 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1064 if (!dev) { 1065 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1066 return -ENOMEM; 1067 } 1068 1069 spin_lock_init(&dev->irqlock); 1070 spin_lock_init(&dev->condlock); 1071 dev->plat_dev = pdev; 1072 if (!dev->plat_dev) { 1073 dev_err(&pdev->dev, "No platform data specified\n"); 1074 return -ENODEV; 1075 } 1076 1077 dev->variant = mfc_get_drv_data(pdev); 1078 1079 ret = s5p_mfc_init_pm(dev); 1080 if (ret < 0) { 1081 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1082 return ret; 1083 } 1084 1085 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1086 1087 dev->regs_base = devm_ioremap_resource(&pdev->dev, res); 1088 if (IS_ERR(dev->regs_base)) 1089 return PTR_ERR(dev->regs_base); 1090 1091 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1092 if (res == NULL) { 1093 dev_err(&pdev->dev, "failed to get irq resource\n"); 1094 ret = -ENOENT; 1095 goto err_res; 1096 } 1097 dev->irq = res->start; 1098 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1099 0, pdev->name, dev); 1100 if (ret) { 1101 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1102 goto err_res; 1103 } 1104 1105 if (pdev->dev.of_node) { 1106 ret = s5p_mfc_alloc_memdevs(dev); 1107 if (ret < 0) 1108 goto err_res; 1109 } else { 1110 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1111 "s5p-mfc-l", match_child); 1112 if (!dev->mem_dev_l) { 1113 mfc_err("Mem child (L) device get failed\n"); 1114 ret = -ENODEV; 1115 goto err_res; 1116 } 1117 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1118 "s5p-mfc-r", match_child); 1119 if (!dev->mem_dev_r) { 1120 mfc_err("Mem child (R) device get failed\n"); 1121 ret = -ENODEV; 1122 goto err_res; 1123 } 1124 } 1125 1126 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1127 if (IS_ERR(dev->alloc_ctx[0])) { 1128 ret = PTR_ERR(dev->alloc_ctx[0]); 1129 goto err_res; 1130 } 1131 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1132 if (IS_ERR(dev->alloc_ctx[1])) { 1133 ret = PTR_ERR(dev->alloc_ctx[1]); 1134 goto err_mem_init_ctx_1; 1135 } 1136 1137 mutex_init(&dev->mfc_mutex); 1138 1139 ret = s5p_mfc_alloc_firmware(dev); 1140 if (ret) 1141 goto err_alloc_fw; 1142 1143 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1144 if (ret) 1145 goto err_v4l2_dev_reg; 1146 init_waitqueue_head(&dev->queue); 1147 1148 /* decoder */ 1149 vfd = video_device_alloc(); 1150 if (!vfd) { 1151 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1152 ret = -ENOMEM; 1153 goto err_dec_alloc; 1154 } 1155 vfd->fops = &s5p_mfc_fops; 1156 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1157 vfd->release = video_device_release; 1158 vfd->lock = &dev->mfc_mutex; 1159 vfd->v4l2_dev = &dev->v4l2_dev; 1160 vfd->vfl_dir = VFL_DIR_M2M; 1161 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1162 dev->vfd_dec = vfd; 1163 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1164 if (ret) { 1165 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1166 video_device_release(vfd); 1167 goto err_dec_reg; 1168 } 1169 v4l2_info(&dev->v4l2_dev, 1170 "decoder registered as /dev/video%d\n", vfd->num); 1171 video_set_drvdata(vfd, dev); 1172 1173 /* encoder */ 1174 vfd = video_device_alloc(); 1175 if (!vfd) { 1176 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1177 ret = -ENOMEM; 1178 goto err_enc_alloc; 1179 } 1180 vfd->fops = &s5p_mfc_fops; 1181 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1182 vfd->release = video_device_release; 1183 vfd->lock = &dev->mfc_mutex; 1184 vfd->v4l2_dev = &dev->v4l2_dev; 1185 vfd->vfl_dir = VFL_DIR_M2M; 1186 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1187 dev->vfd_enc = vfd; 1188 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1189 if (ret) { 1190 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1191 video_device_release(vfd); 1192 goto err_enc_reg; 1193 } 1194 v4l2_info(&dev->v4l2_dev, 1195 "encoder registered as /dev/video%d\n", vfd->num); 1196 video_set_drvdata(vfd, dev); 1197 platform_set_drvdata(pdev, dev); 1198 1199 dev->hw_lock = 0; 1200 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1201 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1202 atomic_set(&dev->watchdog_cnt, 0); 1203 init_timer(&dev->watchdog_timer); 1204 dev->watchdog_timer.data = (unsigned long)dev; 1205 dev->watchdog_timer.function = s5p_mfc_watchdog; 1206 1207 /* Initialize HW ops and commands based on MFC version */ 1208 s5p_mfc_init_hw_ops(dev); 1209 s5p_mfc_init_hw_cmds(dev); 1210 1211 pr_debug("%s--\n", __func__); 1212 return 0; 1213 1214/* Deinit MFC if probe had failed */ 1215err_enc_reg: 1216 video_device_release(dev->vfd_enc); 1217err_enc_alloc: 1218 video_unregister_device(dev->vfd_dec); 1219err_dec_reg: 1220 video_device_release(dev->vfd_dec); 1221err_dec_alloc: 1222 v4l2_device_unregister(&dev->v4l2_dev); 1223err_v4l2_dev_reg: 1224 s5p_mfc_release_firmware(dev); 1225err_alloc_fw: 1226 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1227err_mem_init_ctx_1: 1228 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1229err_res: 1230 s5p_mfc_final_pm(dev); 1231 1232 pr_debug("%s-- with error\n", __func__); 1233 return ret; 1234 1235} 1236 1237/* Remove the driver */ 1238static int s5p_mfc_remove(struct platform_device *pdev) 1239{ 1240 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1241 1242 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1243 1244 del_timer_sync(&dev->watchdog_timer); 1245 flush_workqueue(dev->watchdog_workqueue); 1246 destroy_workqueue(dev->watchdog_workqueue); 1247 1248 video_unregister_device(dev->vfd_enc); 1249 video_unregister_device(dev->vfd_dec); 1250 v4l2_device_unregister(&dev->v4l2_dev); 1251 s5p_mfc_release_firmware(dev); 1252 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1253 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1254 if (pdev->dev.of_node) { 1255 put_device(dev->mem_dev_l); 1256 put_device(dev->mem_dev_r); 1257 } 1258 1259 s5p_mfc_final_pm(dev); 1260 return 0; 1261} 1262 1263#ifdef CONFIG_PM_SLEEP 1264 1265static int s5p_mfc_suspend(struct device *dev) 1266{ 1267 struct platform_device *pdev = to_platform_device(dev); 1268 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1269 int ret; 1270 1271 if (m_dev->num_inst == 0) 1272 return 0; 1273 1274 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1275 mfc_err("Error: going to suspend for a second time\n"); 1276 return -EIO; 1277 } 1278 1279 /* Check if we're processing then wait if it necessary. */ 1280 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1281 /* Try and lock the HW */ 1282 /* Wait on the interrupt waitqueue */ 1283 ret = wait_event_interruptible_timeout(m_dev->queue, 1284 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT)); 1285 if (ret == 0) { 1286 mfc_err("Waiting for hardware to finish timed out\n"); 1287 return -EIO; 1288 } 1289 } 1290 1291 return s5p_mfc_sleep(m_dev); 1292} 1293 1294static int s5p_mfc_resume(struct device *dev) 1295{ 1296 struct platform_device *pdev = to_platform_device(dev); 1297 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1298 1299 if (m_dev->num_inst == 0) 1300 return 0; 1301 return s5p_mfc_wakeup(m_dev); 1302} 1303#endif 1304 1305#ifdef CONFIG_PM_RUNTIME 1306static int s5p_mfc_runtime_suspend(struct device *dev) 1307{ 1308 struct platform_device *pdev = to_platform_device(dev); 1309 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1310 1311 atomic_set(&m_dev->pm.power, 0); 1312 return 0; 1313} 1314 1315static int s5p_mfc_runtime_resume(struct device *dev) 1316{ 1317 struct platform_device *pdev = to_platform_device(dev); 1318 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1319 int pre_power; 1320 1321 if (!m_dev->alloc_ctx) 1322 return 0; 1323 pre_power = atomic_read(&m_dev->pm.power); 1324 atomic_set(&m_dev->pm.power, 1); 1325 return 0; 1326} 1327#endif 1328 1329/* Power management */ 1330static const struct dev_pm_ops s5p_mfc_pm_ops = { 1331 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1332 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1333 NULL) 1334}; 1335 1336struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1337 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1338 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1339 .dsc = DESC_BUF_SIZE, 1340 .shm = SHARED_BUF_SIZE, 1341}; 1342 1343struct s5p_mfc_buf_size buf_size_v5 = { 1344 .fw = MAX_FW_SIZE, 1345 .cpb = MAX_CPB_SIZE, 1346 .priv = &mfc_buf_size_v5, 1347}; 1348 1349struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1350 .base = MFC_BASE_ALIGN_ORDER, 1351}; 1352 1353static struct s5p_mfc_variant mfc_drvdata_v5 = { 1354 .version = MFC_VERSION, 1355 .port_num = MFC_NUM_PORTS, 1356 .buf_size = &buf_size_v5, 1357 .buf_align = &mfc_buf_align_v5, 1358 .fw_name = "s5p-mfc.fw", 1359}; 1360 1361struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1362 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1363 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1364 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1365 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1366 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1367}; 1368 1369struct s5p_mfc_buf_size buf_size_v6 = { 1370 .fw = MAX_FW_SIZE_V6, 1371 .cpb = MAX_CPB_SIZE_V6, 1372 .priv = &mfc_buf_size_v6, 1373}; 1374 1375struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1376 .base = 0, 1377}; 1378 1379static struct s5p_mfc_variant mfc_drvdata_v6 = { 1380 .version = MFC_VERSION_V6, 1381 .port_num = MFC_NUM_PORTS_V6, 1382 .buf_size = &buf_size_v6, 1383 .buf_align = &mfc_buf_align_v6, 1384 .fw_name = "s5p-mfc-v6.fw", 1385}; 1386 1387struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = { 1388 .dev_ctx = MFC_CTX_BUF_SIZE_V7, 1389 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7, 1390 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7, 1391 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7, 1392 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7, 1393}; 1394 1395struct s5p_mfc_buf_size buf_size_v7 = { 1396 .fw = MAX_FW_SIZE_V7, 1397 .cpb = MAX_CPB_SIZE_V7, 1398 .priv = &mfc_buf_size_v7, 1399}; 1400 1401struct s5p_mfc_buf_align mfc_buf_align_v7 = { 1402 .base = 0, 1403}; 1404 1405static struct s5p_mfc_variant mfc_drvdata_v7 = { 1406 .version = MFC_VERSION_V7, 1407 .port_num = MFC_NUM_PORTS_V7, 1408 .buf_size = &buf_size_v7, 1409 .buf_align = &mfc_buf_align_v7, 1410 .fw_name = "s5p-mfc-v7.fw", 1411}; 1412 1413static struct platform_device_id mfc_driver_ids[] = { 1414 { 1415 .name = "s5p-mfc", 1416 .driver_data = (unsigned long)&mfc_drvdata_v5, 1417 }, { 1418 .name = "s5p-mfc-v5", 1419 .driver_data = (unsigned long)&mfc_drvdata_v5, 1420 }, { 1421 .name = "s5p-mfc-v6", 1422 .driver_data = (unsigned long)&mfc_drvdata_v6, 1423 }, { 1424 .name = "s5p-mfc-v7", 1425 .driver_data = (unsigned long)&mfc_drvdata_v7, 1426 }, 1427 {}, 1428}; 1429MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1430 1431static const struct of_device_id exynos_mfc_match[] = { 1432 { 1433 .compatible = "samsung,mfc-v5", 1434 .data = &mfc_drvdata_v5, 1435 }, { 1436 .compatible = "samsung,mfc-v6", 1437 .data = &mfc_drvdata_v6, 1438 }, { 1439 .compatible = "samsung,mfc-v7", 1440 .data = &mfc_drvdata_v7, 1441 }, 1442 {}, 1443}; 1444MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1445 1446static void *mfc_get_drv_data(struct platform_device *pdev) 1447{ 1448 struct s5p_mfc_variant *driver_data = NULL; 1449 1450 if (pdev->dev.of_node) { 1451 const struct of_device_id *match; 1452 match = of_match_node(exynos_mfc_match, 1453 pdev->dev.of_node); 1454 if (match) 1455 driver_data = (struct s5p_mfc_variant *)match->data; 1456 } else { 1457 driver_data = (struct s5p_mfc_variant *) 1458 platform_get_device_id(pdev)->driver_data; 1459 } 1460 return driver_data; 1461} 1462 1463static struct platform_driver s5p_mfc_driver = { 1464 .probe = s5p_mfc_probe, 1465 .remove = s5p_mfc_remove, 1466 .id_table = mfc_driver_ids, 1467 .driver = { 1468 .name = S5P_MFC_NAME, 1469 .owner = THIS_MODULE, 1470 .pm = &s5p_mfc_pm_ops, 1471 .of_match_table = exynos_mfc_match, 1472 }, 1473}; 1474 1475module_platform_driver(s5p_mfc_driver); 1476 1477MODULE_LICENSE("GPL"); 1478MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1479MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1480 1481