s5p_mfc.c revision e82564475eab196b2e8a11572fff8e268329530e
1/* 2 * Samsung S5P Multi Format Codec v 5.1 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Kamil Debski, <k.debski@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/platform_device.h> 19#include <linux/sched.h> 20#include <linux/slab.h> 21#include <linux/videodev2.h> 22#include <media/v4l2-event.h> 23#include <linux/workqueue.h> 24#include <linux/of.h> 25#include <media/videobuf2-core.h> 26#include "s5p_mfc_common.h" 27#include "s5p_mfc_ctrl.h" 28#include "s5p_mfc_debug.h" 29#include "s5p_mfc_dec.h" 30#include "s5p_mfc_enc.h" 31#include "s5p_mfc_intr.h" 32#include "s5p_mfc_opr.h" 33#include "s5p_mfc_cmd.h" 34#include "s5p_mfc_pm.h" 35 36#define S5P_MFC_NAME "s5p-mfc" 37#define S5P_MFC_DEC_NAME "s5p-mfc-dec" 38#define S5P_MFC_ENC_NAME "s5p-mfc-enc" 39 40int debug; 41module_param(debug, int, S_IRUGO | S_IWUSR); 42MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages"); 43 44/* Helper functions for interrupt processing */ 45 46/* Remove from hw execution round robin */ 47void clear_work_bit(struct s5p_mfc_ctx *ctx) 48{ 49 struct s5p_mfc_dev *dev = ctx->dev; 50 51 spin_lock(&dev->condlock); 52 __clear_bit(ctx->num, &dev->ctx_work_bits); 53 spin_unlock(&dev->condlock); 54} 55 56/* Add to hw execution round robin */ 57void set_work_bit(struct s5p_mfc_ctx *ctx) 58{ 59 struct s5p_mfc_dev *dev = ctx->dev; 60 61 spin_lock(&dev->condlock); 62 __set_bit(ctx->num, &dev->ctx_work_bits); 63 spin_unlock(&dev->condlock); 64} 65 66/* Remove from hw execution round robin */ 67void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 68{ 69 struct s5p_mfc_dev *dev = ctx->dev; 70 unsigned long flags; 71 72 spin_lock_irqsave(&dev->condlock, flags); 73 __clear_bit(ctx->num, &dev->ctx_work_bits); 74 spin_unlock_irqrestore(&dev->condlock, flags); 75} 76 77/* Add to hw execution round robin */ 78void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx) 79{ 80 struct s5p_mfc_dev *dev = ctx->dev; 81 unsigned long flags; 82 83 spin_lock_irqsave(&dev->condlock, flags); 84 __set_bit(ctx->num, &dev->ctx_work_bits); 85 spin_unlock_irqrestore(&dev->condlock, flags); 86} 87 88/* Wake up context wait_queue */ 89static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason, 90 unsigned int err) 91{ 92 ctx->int_cond = 1; 93 ctx->int_type = reason; 94 ctx->int_err = err; 95 wake_up(&ctx->queue); 96} 97 98/* Wake up device wait_queue */ 99static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason, 100 unsigned int err) 101{ 102 dev->int_cond = 1; 103 dev->int_type = reason; 104 dev->int_err = err; 105 wake_up(&dev->queue); 106} 107 108static void s5p_mfc_watchdog(unsigned long arg) 109{ 110 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg; 111 112 if (test_bit(0, &dev->hw_lock)) 113 atomic_inc(&dev->watchdog_cnt); 114 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) { 115 /* This means that hw is busy and no interrupts were 116 * generated by hw for the Nth time of running this 117 * watchdog timer. This usually means a serious hw 118 * error. Now it is time to kill all instances and 119 * reset the MFC. */ 120 mfc_err("Time out during waiting for HW\n"); 121 queue_work(dev->watchdog_workqueue, &dev->watchdog_work); 122 } 123 dev->watchdog_timer.expires = jiffies + 124 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 125 add_timer(&dev->watchdog_timer); 126} 127 128static void s5p_mfc_watchdog_worker(struct work_struct *work) 129{ 130 struct s5p_mfc_dev *dev; 131 struct s5p_mfc_ctx *ctx; 132 unsigned long flags; 133 int mutex_locked; 134 int i, ret; 135 136 dev = container_of(work, struct s5p_mfc_dev, watchdog_work); 137 138 mfc_err("Driver timeout error handling\n"); 139 /* Lock the mutex that protects open and release. 140 * This is necessary as they may load and unload firmware. */ 141 mutex_locked = mutex_trylock(&dev->mfc_mutex); 142 if (!mutex_locked) 143 mfc_err("Error: some instance may be closing/opening\n"); 144 spin_lock_irqsave(&dev->irqlock, flags); 145 146 s5p_mfc_clock_off(); 147 148 for (i = 0; i < MFC_NUM_CONTEXTS; i++) { 149 ctx = dev->ctx[i]; 150 if (!ctx) 151 continue; 152 ctx->state = MFCINST_ERROR; 153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 154 &ctx->vq_dst); 155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 156 &ctx->vq_src); 157 clear_work_bit(ctx); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 159 } 160 clear_bit(0, &dev->hw_lock); 161 spin_unlock_irqrestore(&dev->irqlock, flags); 162 /* Double check if there is at least one instance running. 163 * If no instance is in memory than no firmware should be present */ 164 if (dev->num_inst > 0) { 165 ret = s5p_mfc_reload_firmware(dev); 166 if (ret) { 167 mfc_err("Failed to reload FW\n"); 168 goto unlock; 169 } 170 s5p_mfc_clock_on(); 171 ret = s5p_mfc_init_hw(dev); 172 if (ret) 173 mfc_err("Failed to reinit FW\n"); 174 } 175unlock: 176 if (mutex_locked) 177 mutex_unlock(&dev->mfc_mutex); 178} 179 180static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file) 181{ 182 struct video_device *vdev = video_devdata(file); 183 184 if (!vdev) { 185 mfc_err("failed to get video_device"); 186 return MFCNODE_INVALID; 187 } 188 if (vdev->index == 0) 189 return MFCNODE_DECODER; 190 else if (vdev->index == 1) 191 return MFCNODE_ENCODER; 192 return MFCNODE_INVALID; 193} 194 195static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev) 196{ 197 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 198 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 199 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 200} 201 202static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx) 203{ 204 struct s5p_mfc_buf *dst_buf; 205 struct s5p_mfc_dev *dev = ctx->dev; 206 207 ctx->state = MFCINST_FINISHED; 208 ctx->sequence++; 209 while (!list_empty(&ctx->dst_queue)) { 210 dst_buf = list_entry(ctx->dst_queue.next, 211 struct s5p_mfc_buf, list); 212 mfc_debug(2, "Cleaning up buffer: %d\n", 213 dst_buf->b->v4l2_buf.index); 214 vb2_set_plane_payload(dst_buf->b, 0, 0); 215 vb2_set_plane_payload(dst_buf->b, 1, 0); 216 list_del(&dst_buf->list); 217 ctx->dst_queue_cnt--; 218 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++); 219 220 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) == 221 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx)) 222 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 223 else 224 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED; 225 226 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index); 227 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE); 228 } 229} 230 231static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx) 232{ 233 struct s5p_mfc_dev *dev = ctx->dev; 234 struct s5p_mfc_buf *dst_buf, *src_buf; 235 size_t dec_y_addr; 236 unsigned int frame_type; 237 238 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev); 239 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 240 241 /* Copy timestamp / timecode from decoded src to dst and set 242 appropraite flags */ 243 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 244 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 245 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) { 246 memcpy(&dst_buf->b->v4l2_buf.timecode, 247 &src_buf->b->v4l2_buf.timecode, 248 sizeof(struct v4l2_timecode)); 249 memcpy(&dst_buf->b->v4l2_buf.timestamp, 250 &src_buf->b->v4l2_buf.timestamp, 251 sizeof(struct timeval)); 252 switch (frame_type) { 253 case S5P_FIMV_DECODE_FRAME_I_FRAME: 254 dst_buf->b->v4l2_buf.flags |= 255 V4L2_BUF_FLAG_KEYFRAME; 256 break; 257 case S5P_FIMV_DECODE_FRAME_P_FRAME: 258 dst_buf->b->v4l2_buf.flags |= 259 V4L2_BUF_FLAG_PFRAME; 260 break; 261 case S5P_FIMV_DECODE_FRAME_B_FRAME: 262 dst_buf->b->v4l2_buf.flags |= 263 V4L2_BUF_FLAG_BFRAME; 264 break; 265 } 266 break; 267 } 268 } 269} 270 271static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err) 272{ 273 struct s5p_mfc_dev *dev = ctx->dev; 274 struct s5p_mfc_buf *dst_buf; 275 size_t dspl_y_addr; 276 unsigned int frame_type; 277 278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev); 279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev); 280 281 /* If frame is same as previous then skip and do not dequeue */ 282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) { 283 if (!ctx->after_packed_pb) 284 ctx->sequence++; 285 ctx->after_packed_pb = 0; 286 return; 287 } 288 ctx->sequence++; 289 /* The MFC returns address of the buffer, now we have to 290 * check which videobuf does it correspond to */ 291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) { 292 /* Check if this is the buffer we're looking for */ 293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) { 294 list_del(&dst_buf->list); 295 ctx->dst_queue_cnt--; 296 dst_buf->b->v4l2_buf.sequence = ctx->sequence; 297 if (s5p_mfc_hw_call(dev->mfc_ops, 298 get_pic_type_top, ctx) == 299 s5p_mfc_hw_call(dev->mfc_ops, 300 get_pic_type_bot, ctx)) 301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE; 302 else 303 dst_buf->b->v4l2_buf.field = 304 V4L2_FIELD_INTERLACED; 305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size); 306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size); 307 clear_bit(dst_buf->b->v4l2_buf.index, 308 &ctx->dec_dst_flag); 309 310 vb2_buffer_done(dst_buf->b, 311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 312 313 break; 314 } 315 } 316} 317 318/* Handle frame decoding interrupt */ 319static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx, 320 unsigned int reason, unsigned int err) 321{ 322 struct s5p_mfc_dev *dev = ctx->dev; 323 unsigned int dst_frame_status; 324 struct s5p_mfc_buf *src_buf; 325 unsigned long flags; 326 unsigned int res_change; 327 328 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 329 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK; 330 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev) 331 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK) 332 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT; 333 mfc_debug(2, "Frame Status: %x\n", dst_frame_status); 334 if (ctx->state == MFCINST_RES_CHANGE_INIT) 335 ctx->state = MFCINST_RES_CHANGE_FLUSH; 336 if (res_change == S5P_FIMV_RES_INCREASE || 337 res_change == S5P_FIMV_RES_DECREASE) { 338 ctx->state = MFCINST_RES_CHANGE_INIT; 339 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 340 wake_up_ctx(ctx, reason, err); 341 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 342 BUG(); 343 s5p_mfc_clock_off(); 344 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 345 return; 346 } 347 if (ctx->dpb_flush_flag) 348 ctx->dpb_flush_flag = 0; 349 350 spin_lock_irqsave(&dev->irqlock, flags); 351 /* All frames remaining in the buffer have been extracted */ 352 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) { 353 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) { 354 s5p_mfc_handle_frame_all_extracted(ctx); 355 ctx->state = MFCINST_RES_CHANGE_END; 356 goto leave_handle_frame; 357 } else { 358 s5p_mfc_handle_frame_all_extracted(ctx); 359 } 360 } 361 362 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY || 363 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY) 364 s5p_mfc_handle_frame_copy_time(ctx); 365 366 /* A frame has been decoded and is in the buffer */ 367 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY || 368 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) { 369 s5p_mfc_handle_frame_new(ctx, err); 370 } else { 371 mfc_debug(2, "No frame decode\n"); 372 } 373 /* Mark source buffer as complete */ 374 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 375 && !list_empty(&ctx->src_queue)) { 376 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 377 list); 378 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops, 379 get_consumed_stream, dev); 380 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC && 381 ctx->consumed_stream + STUFF_BYTE < 382 src_buf->b->v4l2_planes[0].bytesused) { 383 /* Run MFC again on the same buffer */ 384 mfc_debug(2, "Running again the same buffer\n"); 385 ctx->after_packed_pb = 1; 386 } else { 387 mfc_debug(2, "MFC needs next buffer\n"); 388 ctx->consumed_stream = 0; 389 list_del(&src_buf->list); 390 ctx->src_queue_cnt--; 391 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0) 392 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR); 393 else 394 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE); 395 } 396 } 397leave_handle_frame: 398 spin_unlock_irqrestore(&dev->irqlock, flags); 399 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 400 || ctx->dst_queue_cnt < ctx->dpb_count) 401 clear_work_bit(ctx); 402 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 403 wake_up_ctx(ctx, reason, err); 404 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 405 BUG(); 406 s5p_mfc_clock_off(); 407 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 408} 409 410/* Error handling for interrupt */ 411static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev, 412 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err) 413{ 414 unsigned long flags; 415 416 mfc_err("Interrupt Error: %08x\n", err); 417 418 if (ctx != NULL) { 419 /* Error recovery is dependent on the state of context */ 420 switch (ctx->state) { 421 case MFCINST_RES_CHANGE_INIT: 422 case MFCINST_RES_CHANGE_FLUSH: 423 case MFCINST_RES_CHANGE_END: 424 case MFCINST_FINISHING: 425 case MFCINST_FINISHED: 426 case MFCINST_RUNNING: 427 /* It is higly probable that an error occured 428 * while decoding a frame */ 429 clear_work_bit(ctx); 430 ctx->state = MFCINST_ERROR; 431 /* Mark all dst buffers as having an error */ 432 spin_lock_irqsave(&dev->irqlock, flags); 433 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 434 &ctx->dst_queue, &ctx->vq_dst); 435 /* Mark all src buffers as having an error */ 436 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 437 &ctx->src_queue, &ctx->vq_src); 438 spin_unlock_irqrestore(&dev->irqlock, flags); 439 wake_up_ctx(ctx, reason, err); 440 break; 441 default: 442 clear_work_bit(ctx); 443 ctx->state = MFCINST_ERROR; 444 wake_up_ctx(ctx, reason, err); 445 break; 446 } 447 } 448 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 449 BUG(); 450 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 451 s5p_mfc_clock_off(); 452 wake_up_dev(dev, reason, err); 453 return; 454} 455 456/* Header parsing interrupt handling */ 457static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 458 unsigned int reason, unsigned int err) 459{ 460 struct s5p_mfc_dev *dev; 461 462 if (ctx == NULL) 463 return; 464 dev = ctx->dev; 465 if (ctx->c_ops->post_seq_start) { 466 if (ctx->c_ops->post_seq_start(ctx)) 467 mfc_err("post_seq_start() failed\n"); 468 } else { 469 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width, 470 dev); 471 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 472 dev); 473 474 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 475 476 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 477 dev); 478 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count, 479 dev); 480 if (ctx->img_width == 0 || ctx->img_height == 0) 481 ctx->state = MFCINST_ERROR; 482 else 483 ctx->state = MFCINST_HEAD_PARSED; 484 485 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 486 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) && 487 !list_empty(&ctx->src_queue)) { 488 struct s5p_mfc_buf *src_buf; 489 src_buf = list_entry(ctx->src_queue.next, 490 struct s5p_mfc_buf, list); 491 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream, 492 dev) < 493 src_buf->b->v4l2_planes[0].bytesused) 494 ctx->head_processed = 0; 495 else 496 ctx->head_processed = 1; 497 } else { 498 ctx->head_processed = 1; 499 } 500 } 501 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 502 clear_work_bit(ctx); 503 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 504 BUG(); 505 s5p_mfc_clock_off(); 506 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 507 wake_up_ctx(ctx, reason, err); 508} 509 510/* Header parsing interrupt handling */ 511static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx, 512 unsigned int reason, unsigned int err) 513{ 514 struct s5p_mfc_buf *src_buf; 515 struct s5p_mfc_dev *dev; 516 unsigned long flags; 517 518 if (ctx == NULL) 519 return; 520 dev = ctx->dev; 521 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 522 ctx->int_type = reason; 523 ctx->int_err = err; 524 ctx->int_cond = 1; 525 clear_work_bit(ctx); 526 if (err == 0) { 527 ctx->state = MFCINST_RUNNING; 528 if (!ctx->dpb_flush_flag && ctx->head_processed) { 529 spin_lock_irqsave(&dev->irqlock, flags); 530 if (!list_empty(&ctx->src_queue)) { 531 src_buf = list_entry(ctx->src_queue.next, 532 struct s5p_mfc_buf, list); 533 list_del(&src_buf->list); 534 ctx->src_queue_cnt--; 535 vb2_buffer_done(src_buf->b, 536 VB2_BUF_STATE_DONE); 537 } 538 spin_unlock_irqrestore(&dev->irqlock, flags); 539 } else { 540 ctx->dpb_flush_flag = 0; 541 } 542 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 543 BUG(); 544 545 s5p_mfc_clock_off(); 546 547 wake_up(&ctx->queue); 548 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 549 } else { 550 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 551 BUG(); 552 553 s5p_mfc_clock_off(); 554 555 wake_up(&ctx->queue); 556 } 557} 558 559static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx, 560 unsigned int reason, unsigned int err) 561{ 562 struct s5p_mfc_dev *dev = ctx->dev; 563 struct s5p_mfc_buf *mb_entry; 564 565 mfc_debug(2, "Stream completed"); 566 567 s5p_mfc_clear_int_flags(dev); 568 ctx->int_type = reason; 569 ctx->int_err = err; 570 ctx->state = MFCINST_FINISHED; 571 572 spin_lock(&dev->irqlock); 573 if (!list_empty(&ctx->dst_queue)) { 574 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, 575 list); 576 list_del(&mb_entry->list); 577 ctx->dst_queue_cnt--; 578 vb2_set_plane_payload(mb_entry->b, 0, 0); 579 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE); 580 } 581 spin_unlock(&dev->irqlock); 582 583 clear_work_bit(ctx); 584 585 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0); 586 587 s5p_mfc_clock_off(); 588 wake_up(&ctx->queue); 589 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 590} 591 592/* Interrupt processing */ 593static irqreturn_t s5p_mfc_irq(int irq, void *priv) 594{ 595 struct s5p_mfc_dev *dev = priv; 596 struct s5p_mfc_ctx *ctx; 597 unsigned int reason; 598 unsigned int err; 599 600 mfc_debug_enter(); 601 /* Reset the timeout watchdog */ 602 atomic_set(&dev->watchdog_cnt, 0); 603 ctx = dev->ctx[dev->curr_ctx]; 604 /* Get the reason of interrupt and the error code */ 605 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev); 606 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev); 607 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err); 608 switch (reason) { 609 case S5P_MFC_R2H_CMD_ERR_RET: 610 /* An error has occured */ 611 if (ctx->state == MFCINST_RUNNING && 612 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >= 613 dev->warn_start) 614 s5p_mfc_handle_frame(ctx, reason, err); 615 else 616 s5p_mfc_handle_error(dev, ctx, reason, err); 617 clear_bit(0, &dev->enter_suspend); 618 break; 619 620 case S5P_MFC_R2H_CMD_SLICE_DONE_RET: 621 case S5P_MFC_R2H_CMD_FIELD_DONE_RET: 622 case S5P_MFC_R2H_CMD_FRAME_DONE_RET: 623 if (ctx->c_ops->post_frame_start) { 624 if (ctx->c_ops->post_frame_start(ctx)) 625 mfc_err("post_frame_start() failed\n"); 626 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 627 wake_up_ctx(ctx, reason, err); 628 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 629 BUG(); 630 s5p_mfc_clock_off(); 631 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 632 } else { 633 s5p_mfc_handle_frame(ctx, reason, err); 634 } 635 break; 636 637 case S5P_MFC_R2H_CMD_SEQ_DONE_RET: 638 s5p_mfc_handle_seq_done(ctx, reason, err); 639 break; 640 641 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET: 642 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev); 643 ctx->state = MFCINST_GOT_INST; 644 clear_work_bit(ctx); 645 wake_up(&ctx->queue); 646 goto irq_cleanup_hw; 647 648 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET: 649 clear_work_bit(ctx); 650 ctx->state = MFCINST_FREE; 651 wake_up(&ctx->queue); 652 goto irq_cleanup_hw; 653 654 case S5P_MFC_R2H_CMD_SYS_INIT_RET: 655 case S5P_MFC_R2H_CMD_FW_STATUS_RET: 656 case S5P_MFC_R2H_CMD_SLEEP_RET: 657 case S5P_MFC_R2H_CMD_WAKEUP_RET: 658 if (ctx) 659 clear_work_bit(ctx); 660 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 661 wake_up_dev(dev, reason, err); 662 clear_bit(0, &dev->hw_lock); 663 clear_bit(0, &dev->enter_suspend); 664 break; 665 666 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET: 667 s5p_mfc_handle_init_buffers(ctx, reason, err); 668 break; 669 670 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET: 671 s5p_mfc_handle_stream_complete(ctx, reason, err); 672 break; 673 674 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET: 675 clear_work_bit(ctx); 676 ctx->state = MFCINST_RUNNING; 677 wake_up(&ctx->queue); 678 goto irq_cleanup_hw; 679 680 default: 681 mfc_debug(2, "Unknown int reason\n"); 682 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 683 } 684 mfc_debug_leave(); 685 return IRQ_HANDLED; 686irq_cleanup_hw: 687 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 688 ctx->int_type = reason; 689 ctx->int_err = err; 690 ctx->int_cond = 1; 691 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 692 mfc_err("Failed to unlock hw\n"); 693 694 s5p_mfc_clock_off(); 695 696 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 697 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 698 return IRQ_HANDLED; 699} 700 701/* Open an MFC node */ 702static int s5p_mfc_open(struct file *file) 703{ 704 struct s5p_mfc_dev *dev = video_drvdata(file); 705 struct s5p_mfc_ctx *ctx = NULL; 706 struct vb2_queue *q; 707 int ret = 0; 708 709 mfc_debug_enter(); 710 if (mutex_lock_interruptible(&dev->mfc_mutex)) 711 return -ERESTARTSYS; 712 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */ 713 /* Allocate memory for context */ 714 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 715 if (!ctx) { 716 mfc_err("Not enough memory\n"); 717 ret = -ENOMEM; 718 goto err_alloc; 719 } 720 v4l2_fh_init(&ctx->fh, video_devdata(file)); 721 file->private_data = &ctx->fh; 722 v4l2_fh_add(&ctx->fh); 723 ctx->dev = dev; 724 INIT_LIST_HEAD(&ctx->src_queue); 725 INIT_LIST_HEAD(&ctx->dst_queue); 726 ctx->src_queue_cnt = 0; 727 ctx->dst_queue_cnt = 0; 728 /* Get context number */ 729 ctx->num = 0; 730 while (dev->ctx[ctx->num]) { 731 ctx->num++; 732 if (ctx->num >= MFC_NUM_CONTEXTS) { 733 mfc_err("Too many open contexts\n"); 734 ret = -EBUSY; 735 goto err_no_ctx; 736 } 737 } 738 /* Mark context as idle */ 739 clear_work_bit_irqsave(ctx); 740 dev->ctx[ctx->num] = ctx; 741 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 742 ctx->type = MFCINST_DECODER; 743 ctx->c_ops = get_dec_codec_ops(); 744 s5p_mfc_dec_init(ctx); 745 /* Setup ctrl handler */ 746 ret = s5p_mfc_dec_ctrls_setup(ctx); 747 if (ret) { 748 mfc_err("Failed to setup mfc controls\n"); 749 goto err_ctrls_setup; 750 } 751 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 752 ctx->type = MFCINST_ENCODER; 753 ctx->c_ops = get_enc_codec_ops(); 754 /* only for encoder */ 755 INIT_LIST_HEAD(&ctx->ref_queue); 756 ctx->ref_queue_cnt = 0; 757 s5p_mfc_enc_init(ctx); 758 /* Setup ctrl handler */ 759 ret = s5p_mfc_enc_ctrls_setup(ctx); 760 if (ret) { 761 mfc_err("Failed to setup mfc controls\n"); 762 goto err_ctrls_setup; 763 } 764 } else { 765 ret = -ENOENT; 766 goto err_bad_node; 767 } 768 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 769 ctx->inst_no = -1; 770 /* Load firmware if this is the first instance */ 771 if (dev->num_inst == 1) { 772 dev->watchdog_timer.expires = jiffies + 773 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL); 774 add_timer(&dev->watchdog_timer); 775 ret = s5p_mfc_power_on(); 776 if (ret < 0) { 777 mfc_err("power on failed\n"); 778 goto err_pwr_enable; 779 } 780 s5p_mfc_clock_on(); 781 ret = s5p_mfc_load_firmware(dev); 782 if (ret) { 783 s5p_mfc_clock_off(); 784 goto err_load_fw; 785 } 786 /* Init the FW */ 787 ret = s5p_mfc_init_hw(dev); 788 s5p_mfc_clock_off(); 789 if (ret) 790 goto err_init_hw; 791 } 792 /* Init videobuf2 queue for CAPTURE */ 793 q = &ctx->vq_dst; 794 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 795 q->drv_priv = &ctx->fh; 796 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 797 q->io_modes = VB2_MMAP; 798 q->ops = get_dec_queue_ops(); 799 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 800 q->io_modes = VB2_MMAP | VB2_USERPTR; 801 q->ops = get_enc_queue_ops(); 802 } else { 803 ret = -ENOENT; 804 goto err_queue_init; 805 } 806 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 807 ret = vb2_queue_init(q); 808 if (ret) { 809 mfc_err("Failed to initialize videobuf2 queue(capture)\n"); 810 goto err_queue_init; 811 } 812 /* Init videobuf2 queue for OUTPUT */ 813 q = &ctx->vq_src; 814 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 815 q->io_modes = VB2_MMAP; 816 q->drv_priv = &ctx->fh; 817 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) { 818 q->io_modes = VB2_MMAP; 819 q->ops = get_dec_queue_ops(); 820 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) { 821 q->io_modes = VB2_MMAP | VB2_USERPTR; 822 q->ops = get_enc_queue_ops(); 823 } else { 824 ret = -ENOENT; 825 goto err_queue_init; 826 } 827 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops; 828 ret = vb2_queue_init(q); 829 if (ret) { 830 mfc_err("Failed to initialize videobuf2 queue(output)\n"); 831 goto err_queue_init; 832 } 833 init_waitqueue_head(&ctx->queue); 834 mutex_unlock(&dev->mfc_mutex); 835 mfc_debug_leave(); 836 return ret; 837 /* Deinit when failure occured */ 838err_queue_init: 839 if (dev->num_inst == 1) 840 s5p_mfc_deinit_hw(dev); 841err_init_hw: 842err_load_fw: 843err_pwr_enable: 844 if (dev->num_inst == 1) { 845 if (s5p_mfc_power_off() < 0) 846 mfc_err("power off failed\n"); 847 del_timer_sync(&dev->watchdog_timer); 848 } 849err_ctrls_setup: 850 s5p_mfc_dec_ctrls_delete(ctx); 851err_bad_node: 852 dev->ctx[ctx->num] = NULL; 853err_no_ctx: 854 v4l2_fh_del(&ctx->fh); 855 v4l2_fh_exit(&ctx->fh); 856 kfree(ctx); 857err_alloc: 858 dev->num_inst--; 859 mutex_unlock(&dev->mfc_mutex); 860 mfc_debug_leave(); 861 return ret; 862} 863 864/* Release MFC context */ 865static int s5p_mfc_release(struct file *file) 866{ 867 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 868 struct s5p_mfc_dev *dev = ctx->dev; 869 870 mfc_debug_enter(); 871 mutex_lock(&dev->mfc_mutex); 872 s5p_mfc_clock_on(); 873 vb2_queue_release(&ctx->vq_src); 874 vb2_queue_release(&ctx->vq_dst); 875 /* Mark context as idle */ 876 clear_work_bit_irqsave(ctx); 877 /* If instance was initialised then 878 * return instance and free reosurces */ 879 if (ctx->inst_no != MFC_NO_INSTANCE_SET) { 880 mfc_debug(2, "Has to free instance\n"); 881 ctx->state = MFCINST_RETURN_INST; 882 set_work_bit_irqsave(ctx); 883 s5p_mfc_clean_ctx_int_flags(ctx); 884 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 885 /* Wait until instance is returned or timeout occured */ 886 if (s5p_mfc_wait_for_done_ctx 887 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) { 888 s5p_mfc_clock_off(); 889 mfc_err("Err returning instance\n"); 890 } 891 mfc_debug(2, "After free instance\n"); 892 /* Free resources */ 893 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 894 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 895 if (ctx->type == MFCINST_DECODER) 896 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, 897 ctx); 898 899 ctx->inst_no = MFC_NO_INSTANCE_SET; 900 } 901 /* hardware locking scheme */ 902 if (dev->curr_ctx == ctx->num) 903 clear_bit(0, &dev->hw_lock); 904 dev->num_inst--; 905 if (dev->num_inst == 0) { 906 mfc_debug(2, "Last instance\n"); 907 s5p_mfc_deinit_hw(dev); 908 del_timer_sync(&dev->watchdog_timer); 909 if (s5p_mfc_power_off() < 0) 910 mfc_err("Power off failed\n"); 911 } 912 mfc_debug(2, "Shutting down clock\n"); 913 s5p_mfc_clock_off(); 914 dev->ctx[ctx->num] = NULL; 915 s5p_mfc_dec_ctrls_delete(ctx); 916 v4l2_fh_del(&ctx->fh); 917 v4l2_fh_exit(&ctx->fh); 918 kfree(ctx); 919 mfc_debug_leave(); 920 mutex_unlock(&dev->mfc_mutex); 921 return 0; 922} 923 924/* Poll */ 925static unsigned int s5p_mfc_poll(struct file *file, 926 struct poll_table_struct *wait) 927{ 928 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 929 struct s5p_mfc_dev *dev = ctx->dev; 930 struct vb2_queue *src_q, *dst_q; 931 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL; 932 unsigned int rc = 0; 933 unsigned long flags; 934 935 mutex_lock(&dev->mfc_mutex); 936 src_q = &ctx->vq_src; 937 dst_q = &ctx->vq_dst; 938 /* 939 * There has to be at least one buffer queued on each queued_list, which 940 * means either in driver already or waiting for driver to claim it 941 * and start processing. 942 */ 943 if ((!src_q->streaming || list_empty(&src_q->queued_list)) 944 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) { 945 rc = POLLERR; 946 goto end; 947 } 948 mutex_unlock(&dev->mfc_mutex); 949 poll_wait(file, &ctx->fh.wait, wait); 950 poll_wait(file, &src_q->done_wq, wait); 951 poll_wait(file, &dst_q->done_wq, wait); 952 mutex_lock(&dev->mfc_mutex); 953 if (v4l2_event_pending(&ctx->fh)) 954 rc |= POLLPRI; 955 spin_lock_irqsave(&src_q->done_lock, flags); 956 if (!list_empty(&src_q->done_list)) 957 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer, 958 done_entry); 959 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE 960 || src_vb->state == VB2_BUF_STATE_ERROR)) 961 rc |= POLLOUT | POLLWRNORM; 962 spin_unlock_irqrestore(&src_q->done_lock, flags); 963 spin_lock_irqsave(&dst_q->done_lock, flags); 964 if (!list_empty(&dst_q->done_list)) 965 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer, 966 done_entry); 967 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE 968 || dst_vb->state == VB2_BUF_STATE_ERROR)) 969 rc |= POLLIN | POLLRDNORM; 970 spin_unlock_irqrestore(&dst_q->done_lock, flags); 971end: 972 mutex_unlock(&dev->mfc_mutex); 973 return rc; 974} 975 976/* Mmap */ 977static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma) 978{ 979 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data); 980 struct s5p_mfc_dev *dev = ctx->dev; 981 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; 982 int ret; 983 984 if (mutex_lock_interruptible(&dev->mfc_mutex)) 985 return -ERESTARTSYS; 986 if (offset < DST_QUEUE_OFF_BASE) { 987 mfc_debug(2, "mmaping source\n"); 988 ret = vb2_mmap(&ctx->vq_src, vma); 989 } else { /* capture */ 990 mfc_debug(2, "mmaping destination\n"); 991 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT); 992 ret = vb2_mmap(&ctx->vq_dst, vma); 993 } 994 mutex_unlock(&dev->mfc_mutex); 995 return ret; 996} 997 998/* v4l2 ops */ 999static const struct v4l2_file_operations s5p_mfc_fops = { 1000 .owner = THIS_MODULE, 1001 .open = s5p_mfc_open, 1002 .release = s5p_mfc_release, 1003 .poll = s5p_mfc_poll, 1004 .unlocked_ioctl = video_ioctl2, 1005 .mmap = s5p_mfc_mmap, 1006}; 1007 1008static int match_child(struct device *dev, void *data) 1009{ 1010 if (!dev_name(dev)) 1011 return 0; 1012 return !strcmp(dev_name(dev), (char *)data); 1013} 1014 1015static void *mfc_get_drv_data(struct platform_device *pdev); 1016 1017/* MFC probe function */ 1018static int s5p_mfc_probe(struct platform_device *pdev) 1019{ 1020 struct s5p_mfc_dev *dev; 1021 struct video_device *vfd; 1022 struct resource *res; 1023 int ret; 1024 unsigned int mem_info[2]; 1025 1026 pr_debug("%s++\n", __func__); 1027 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 1028 if (!dev) { 1029 dev_err(&pdev->dev, "Not enough memory for MFC device\n"); 1030 return -ENOMEM; 1031 } 1032 1033 spin_lock_init(&dev->irqlock); 1034 spin_lock_init(&dev->condlock); 1035 dev->plat_dev = pdev; 1036 if (!dev->plat_dev) { 1037 dev_err(&pdev->dev, "No platform data specified\n"); 1038 return -ENODEV; 1039 } 1040 1041 dev->variant = mfc_get_drv_data(pdev); 1042 1043 ret = s5p_mfc_init_pm(dev); 1044 if (ret < 0) { 1045 dev_err(&pdev->dev, "failed to get mfc clock source\n"); 1046 return ret; 1047 } 1048 1049 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1050 1051 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res); 1052 if (dev->regs_base == NULL) { 1053 dev_err(&pdev->dev, "Failed to obtain io memory\n"); 1054 return -ENOENT; 1055 } 1056 1057 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1058 if (res == NULL) { 1059 dev_err(&pdev->dev, "failed to get irq resource\n"); 1060 ret = -ENOENT; 1061 goto err_res; 1062 } 1063 dev->irq = res->start; 1064 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq, 1065 IRQF_DISABLED, pdev->name, dev); 1066 if (ret) { 1067 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret); 1068 goto err_res; 1069 } 1070 1071 if (pdev->dev.of_node) { 1072 dev->mem_dev_l = kzalloc(sizeof(struct device), GFP_KERNEL); 1073 if (!dev->mem_dev_l) { 1074 mfc_err("Not enough memory\n"); 1075 ret = -ENOMEM; 1076 goto err_res; 1077 } 1078 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-l", 1079 mem_info, 2); 1080 if (dma_declare_coherent_memory(dev->mem_dev_l, mem_info[0], 1081 mem_info[0], mem_info[1], 1082 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1083 mfc_err("Failed to declare coherent memory for\n" 1084 "MFC device\n"); 1085 ret = -ENOMEM; 1086 goto err_res; 1087 } 1088 1089 dev->mem_dev_r = kzalloc(sizeof(struct device), GFP_KERNEL); 1090 if (!dev->mem_dev_r) { 1091 mfc_err("Not enough memory\n"); 1092 ret = -ENOMEM; 1093 goto err_res; 1094 } 1095 of_property_read_u32_array(pdev->dev.of_node, "samsung,mfc-r", 1096 mem_info, 2); 1097 if (dma_declare_coherent_memory(dev->mem_dev_r, mem_info[0], 1098 mem_info[0], mem_info[1], 1099 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0) { 1100 pr_err("Failed to declare coherent memory for\n" 1101 "MFC device\n"); 1102 ret = -ENOMEM; 1103 goto err_res; 1104 } 1105 } else { 1106 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, 1107 "s5p-mfc-l", match_child); 1108 if (!dev->mem_dev_l) { 1109 mfc_err("Mem child (L) device get failed\n"); 1110 ret = -ENODEV; 1111 goto err_res; 1112 } 1113 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, 1114 "s5p-mfc-r", match_child); 1115 if (!dev->mem_dev_r) { 1116 mfc_err("Mem child (R) device get failed\n"); 1117 ret = -ENODEV; 1118 goto err_res; 1119 } 1120 } 1121 1122 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l); 1123 if (IS_ERR(dev->alloc_ctx[0])) { 1124 ret = PTR_ERR(dev->alloc_ctx[0]); 1125 goto err_res; 1126 } 1127 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r); 1128 if (IS_ERR(dev->alloc_ctx[1])) { 1129 ret = PTR_ERR(dev->alloc_ctx[1]); 1130 goto err_mem_init_ctx_1; 1131 } 1132 1133 mutex_init(&dev->mfc_mutex); 1134 1135 ret = s5p_mfc_alloc_firmware(dev); 1136 if (ret) 1137 goto err_alloc_fw; 1138 1139 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); 1140 if (ret) 1141 goto err_v4l2_dev_reg; 1142 init_waitqueue_head(&dev->queue); 1143 1144 /* decoder */ 1145 vfd = video_device_alloc(); 1146 if (!vfd) { 1147 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1148 ret = -ENOMEM; 1149 goto err_dec_alloc; 1150 } 1151 vfd->fops = &s5p_mfc_fops, 1152 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops(); 1153 vfd->release = video_device_release, 1154 vfd->lock = &dev->mfc_mutex; 1155 vfd->v4l2_dev = &dev->v4l2_dev; 1156 vfd->vfl_dir = VFL_DIR_M2M; 1157 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME); 1158 dev->vfd_dec = vfd; 1159 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1160 if (ret) { 1161 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1162 video_device_release(vfd); 1163 goto err_dec_reg; 1164 } 1165 v4l2_info(&dev->v4l2_dev, 1166 "decoder registered as /dev/video%d\n", vfd->num); 1167 video_set_drvdata(vfd, dev); 1168 1169 /* encoder */ 1170 vfd = video_device_alloc(); 1171 if (!vfd) { 1172 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n"); 1173 ret = -ENOMEM; 1174 goto err_enc_alloc; 1175 } 1176 vfd->fops = &s5p_mfc_fops, 1177 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops(); 1178 vfd->release = video_device_release, 1179 vfd->lock = &dev->mfc_mutex; 1180 vfd->v4l2_dev = &dev->v4l2_dev; 1181 vfd->vfl_dir = VFL_DIR_M2M; 1182 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME); 1183 dev->vfd_enc = vfd; 1184 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); 1185 if (ret) { 1186 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); 1187 video_device_release(vfd); 1188 goto err_enc_reg; 1189 } 1190 v4l2_info(&dev->v4l2_dev, 1191 "encoder registered as /dev/video%d\n", vfd->num); 1192 video_set_drvdata(vfd, dev); 1193 platform_set_drvdata(pdev, dev); 1194 1195 dev->hw_lock = 0; 1196 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME); 1197 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker); 1198 atomic_set(&dev->watchdog_cnt, 0); 1199 init_timer(&dev->watchdog_timer); 1200 dev->watchdog_timer.data = (unsigned long)dev; 1201 dev->watchdog_timer.function = s5p_mfc_watchdog; 1202 1203 /* Initialize HW ops and commands based on MFC version */ 1204 s5p_mfc_init_hw_ops(dev); 1205 s5p_mfc_init_hw_cmds(dev); 1206 1207 pr_debug("%s--\n", __func__); 1208 return 0; 1209 1210/* Deinit MFC if probe had failed */ 1211err_enc_reg: 1212 video_device_release(dev->vfd_enc); 1213err_enc_alloc: 1214 video_unregister_device(dev->vfd_dec); 1215err_dec_reg: 1216 video_device_release(dev->vfd_dec); 1217err_dec_alloc: 1218 v4l2_device_unregister(&dev->v4l2_dev); 1219err_v4l2_dev_reg: 1220 s5p_mfc_release_firmware(dev); 1221err_alloc_fw: 1222 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1223err_mem_init_ctx_1: 1224 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1225err_res: 1226 s5p_mfc_final_pm(dev); 1227 1228 pr_debug("%s-- with error\n", __func__); 1229 return ret; 1230 1231} 1232 1233/* Remove the driver */ 1234static int s5p_mfc_remove(struct platform_device *pdev) 1235{ 1236 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev); 1237 1238 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name); 1239 1240 del_timer_sync(&dev->watchdog_timer); 1241 flush_workqueue(dev->watchdog_workqueue); 1242 destroy_workqueue(dev->watchdog_workqueue); 1243 1244 video_unregister_device(dev->vfd_enc); 1245 video_unregister_device(dev->vfd_dec); 1246 v4l2_device_unregister(&dev->v4l2_dev); 1247 s5p_mfc_release_firmware(dev); 1248 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]); 1249 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]); 1250 1251 s5p_mfc_final_pm(dev); 1252 return 0; 1253} 1254 1255#ifdef CONFIG_PM_SLEEP 1256 1257static int s5p_mfc_suspend(struct device *dev) 1258{ 1259 struct platform_device *pdev = to_platform_device(dev); 1260 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1261 int ret; 1262 1263 if (m_dev->num_inst == 0) 1264 return 0; 1265 1266 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) { 1267 mfc_err("Error: going to suspend for a second time\n"); 1268 return -EIO; 1269 } 1270 1271 /* Check if we're processing then wait if it necessary. */ 1272 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) { 1273 /* Try and lock the HW */ 1274 /* Wait on the interrupt waitqueue */ 1275 ret = wait_event_interruptible_timeout(m_dev->queue, 1276 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond, 1277 msecs_to_jiffies(MFC_INT_TIMEOUT)); 1278 1279 if (ret == 0) { 1280 mfc_err("Waiting for hardware to finish timed out\n"); 1281 return -EIO; 1282 } 1283 } 1284 1285 return s5p_mfc_sleep(m_dev); 1286} 1287 1288static int s5p_mfc_resume(struct device *dev) 1289{ 1290 struct platform_device *pdev = to_platform_device(dev); 1291 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1292 1293 if (m_dev->num_inst == 0) 1294 return 0; 1295 return s5p_mfc_wakeup(m_dev); 1296} 1297#endif 1298 1299#ifdef CONFIG_PM_RUNTIME 1300static int s5p_mfc_runtime_suspend(struct device *dev) 1301{ 1302 struct platform_device *pdev = to_platform_device(dev); 1303 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1304 1305 atomic_set(&m_dev->pm.power, 0); 1306 return 0; 1307} 1308 1309static int s5p_mfc_runtime_resume(struct device *dev) 1310{ 1311 struct platform_device *pdev = to_platform_device(dev); 1312 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev); 1313 int pre_power; 1314 1315 if (!m_dev->alloc_ctx) 1316 return 0; 1317 pre_power = atomic_read(&m_dev->pm.power); 1318 atomic_set(&m_dev->pm.power, 1); 1319 return 0; 1320} 1321#endif 1322 1323/* Power management */ 1324static const struct dev_pm_ops s5p_mfc_pm_ops = { 1325 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume) 1326 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume, 1327 NULL) 1328}; 1329 1330struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = { 1331 .h264_ctx = MFC_H264_CTX_BUF_SIZE, 1332 .non_h264_ctx = MFC_CTX_BUF_SIZE, 1333 .dsc = DESC_BUF_SIZE, 1334 .shm = SHARED_BUF_SIZE, 1335}; 1336 1337struct s5p_mfc_buf_size buf_size_v5 = { 1338 .fw = MAX_FW_SIZE, 1339 .cpb = MAX_CPB_SIZE, 1340 .priv = &mfc_buf_size_v5, 1341}; 1342 1343struct s5p_mfc_buf_align mfc_buf_align_v5 = { 1344 .base = MFC_BASE_ALIGN_ORDER, 1345}; 1346 1347static struct s5p_mfc_variant mfc_drvdata_v5 = { 1348 .version = MFC_VERSION, 1349 .port_num = MFC_NUM_PORTS, 1350 .buf_size = &buf_size_v5, 1351 .buf_align = &mfc_buf_align_v5, 1352 .mclk_name = "sclk_mfc", 1353 .fw_name = "s5p-mfc.fw", 1354}; 1355 1356struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = { 1357 .dev_ctx = MFC_CTX_BUF_SIZE_V6, 1358 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6, 1359 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6, 1360 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6, 1361 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6, 1362}; 1363 1364struct s5p_mfc_buf_size buf_size_v6 = { 1365 .fw = MAX_FW_SIZE_V6, 1366 .cpb = MAX_CPB_SIZE_V6, 1367 .priv = &mfc_buf_size_v6, 1368}; 1369 1370struct s5p_mfc_buf_align mfc_buf_align_v6 = { 1371 .base = 0, 1372}; 1373 1374static struct s5p_mfc_variant mfc_drvdata_v6 = { 1375 .version = MFC_VERSION_V6, 1376 .port_num = MFC_NUM_PORTS_V6, 1377 .buf_size = &buf_size_v6, 1378 .buf_align = &mfc_buf_align_v6, 1379 .mclk_name = "aclk_333", 1380 .fw_name = "s5p-mfc-v6.fw", 1381}; 1382 1383static struct platform_device_id mfc_driver_ids[] = { 1384 { 1385 .name = "s5p-mfc", 1386 .driver_data = (unsigned long)&mfc_drvdata_v5, 1387 }, { 1388 .name = "s5p-mfc-v5", 1389 .driver_data = (unsigned long)&mfc_drvdata_v5, 1390 }, { 1391 .name = "s5p-mfc-v6", 1392 .driver_data = (unsigned long)&mfc_drvdata_v6, 1393 }, 1394 {}, 1395}; 1396MODULE_DEVICE_TABLE(platform, mfc_driver_ids); 1397 1398static const struct of_device_id exynos_mfc_match[] = { 1399 { 1400 .compatible = "samsung,mfc-v5", 1401 .data = &mfc_drvdata_v5, 1402 }, { 1403 .compatible = "samsung,mfc-v6", 1404 .data = &mfc_drvdata_v6, 1405 }, 1406 {}, 1407}; 1408MODULE_DEVICE_TABLE(of, exynos_mfc_match); 1409 1410static void *mfc_get_drv_data(struct platform_device *pdev) 1411{ 1412 struct s5p_mfc_variant *driver_data = NULL; 1413 1414 if (pdev->dev.of_node) { 1415 const struct of_device_id *match; 1416 match = of_match_node(of_match_ptr(exynos_mfc_match), 1417 pdev->dev.of_node); 1418 if (match) 1419 driver_data = (struct s5p_mfc_variant *)match->data; 1420 } else { 1421 driver_data = (struct s5p_mfc_variant *) 1422 platform_get_device_id(pdev)->driver_data; 1423 } 1424 return driver_data; 1425} 1426 1427static struct platform_driver s5p_mfc_driver = { 1428 .probe = s5p_mfc_probe, 1429 .remove = s5p_mfc_remove, 1430 .id_table = mfc_driver_ids, 1431 .driver = { 1432 .name = S5P_MFC_NAME, 1433 .owner = THIS_MODULE, 1434 .pm = &s5p_mfc_pm_ops, 1435 .of_match_table = exynos_mfc_match, 1436 }, 1437}; 1438 1439module_platform_driver(s5p_mfc_driver); 1440 1441MODULE_LICENSE("GPL"); 1442MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>"); 1443MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver"); 1444 1445