s5p_mfc_opr_v5.c revision 2028c71d54e7bd7eb4470d5968f581f9f9284406
1/* 2 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c 3 * 4 * Samsung MFC (Multi Function Codec - FIMV) driver 5 * This file contains hw related functions. 6 * 7 * Kamil Debski, Copyright (c) 2011 Samsung Electronics 8 * http://www.samsung.com/ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include "s5p_mfc_common.h" 16#include "s5p_mfc_cmd.h" 17#include "s5p_mfc_ctrl.h" 18#include "s5p_mfc_debug.h" 19#include "s5p_mfc_intr.h" 20#include "s5p_mfc_pm.h" 21#include "s5p_mfc_opr.h" 22#include "s5p_mfc_opr_v5.h" 23#include <asm/cacheflush.h> 24#include <linux/delay.h> 25#include <linux/dma-mapping.h> 26#include <linux/err.h> 27#include <linux/firmware.h> 28#include <linux/io.h> 29#include <linux/jiffies.h> 30#include <linux/mm.h> 31#include <linux/sched.h> 32 33#define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT) 34#define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT) 35 36/* Allocate temporary buffers for decoding */ 37static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx) 38{ 39 struct s5p_mfc_dev *dev = ctx->dev; 40 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 41 int ret; 42 43 ctx->dsc.size = buf_size->dsc; 44 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->dsc); 45 if (ret) { 46 mfc_err("Failed to allocate temporary buffer\n"); 47 return ret; 48 } 49 50 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 51 memset(ctx->dsc.virt, 0, ctx->dsc.size); 52 wmb(); 53 return 0; 54} 55 56 57/* Release temporary buffers for decoding */ 58static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx) 59{ 60 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc); 61} 62 63/* Allocate codec buffers */ 64static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx) 65{ 66 struct s5p_mfc_dev *dev = ctx->dev; 67 unsigned int enc_ref_y_size = 0; 68 unsigned int enc_ref_c_size = 0; 69 unsigned int guard_width, guard_height; 70 int ret; 71 72 if (ctx->type == MFCINST_DECODER) { 73 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", 74 ctx->luma_size, ctx->chroma_size, ctx->mv_size); 75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); 76 } else if (ctx->type == MFCINST_ENCODER) { 77 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 78 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 79 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); 80 81 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { 82 enc_ref_c_size = ALIGN(ctx->img_width, 83 S5P_FIMV_NV12MT_HALIGN) 84 * ALIGN(ctx->img_height >> 1, 85 S5P_FIMV_NV12MT_VALIGN); 86 enc_ref_c_size = ALIGN(enc_ref_c_size, 87 S5P_FIMV_NV12MT_SALIGN); 88 } else { 89 guard_width = ALIGN(ctx->img_width + 16, 90 S5P_FIMV_NV12MT_HALIGN); 91 guard_height = ALIGN((ctx->img_height >> 1) + 4, 92 S5P_FIMV_NV12MT_VALIGN); 93 enc_ref_c_size = ALIGN(guard_width * guard_height, 94 S5P_FIMV_NV12MT_SALIGN); 95 } 96 mfc_debug(2, "recon luma size: %d chroma size: %d\n", 97 enc_ref_y_size, enc_ref_c_size); 98 } else { 99 return -EINVAL; 100 } 101 /* Codecs have different memory requirements */ 102 switch (ctx->codec_mode) { 103 case S5P_MFC_CODEC_H264_DEC: 104 ctx->bank1.size = 105 ALIGN(S5P_FIMV_DEC_NB_IP_SIZE + 106 S5P_FIMV_DEC_VERT_NB_MV_SIZE, 107 S5P_FIMV_DEC_BUF_ALIGN); 108 ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size; 109 break; 110 case S5P_MFC_CODEC_MPEG4_DEC: 111 ctx->bank1.size = 112 ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE + 113 S5P_FIMV_DEC_UPNB_MV_SIZE + 114 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 115 S5P_FIMV_DEC_STX_PARSER_SIZE + 116 S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE, 117 S5P_FIMV_DEC_BUF_ALIGN); 118 ctx->bank2.size = 0; 119 break; 120 case S5P_MFC_CODEC_VC1RCV_DEC: 121 case S5P_MFC_CODEC_VC1_DEC: 122 ctx->bank1.size = 123 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + 124 S5P_FIMV_DEC_UPNB_MV_SIZE + 125 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 126 S5P_FIMV_DEC_NB_DCAC_SIZE + 127 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE, 128 S5P_FIMV_DEC_BUF_ALIGN); 129 ctx->bank2.size = 0; 130 break; 131 case S5P_MFC_CODEC_MPEG2_DEC: 132 ctx->bank1.size = 0; 133 ctx->bank2.size = 0; 134 break; 135 case S5P_MFC_CODEC_H263_DEC: 136 ctx->bank1.size = 137 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + 138 S5P_FIMV_DEC_UPNB_MV_SIZE + 139 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 140 S5P_FIMV_DEC_NB_DCAC_SIZE, 141 S5P_FIMV_DEC_BUF_ALIGN); 142 ctx->bank2.size = 0; 143 break; 144 case S5P_MFC_CODEC_H264_ENC: 145 ctx->bank1.size = (enc_ref_y_size * 2) + 146 S5P_FIMV_ENC_UPMV_SIZE + 147 S5P_FIMV_ENC_COLFLG_SIZE + 148 S5P_FIMV_ENC_INTRAMD_SIZE + 149 S5P_FIMV_ENC_NBORINFO_SIZE; 150 ctx->bank2.size = (enc_ref_y_size * 2) + 151 (enc_ref_c_size * 4) + 152 S5P_FIMV_ENC_INTRAPRED_SIZE; 153 break; 154 case S5P_MFC_CODEC_MPEG4_ENC: 155 ctx->bank1.size = (enc_ref_y_size * 2) + 156 S5P_FIMV_ENC_UPMV_SIZE + 157 S5P_FIMV_ENC_COLFLG_SIZE + 158 S5P_FIMV_ENC_ACDCCOEF_SIZE; 159 ctx->bank2.size = (enc_ref_y_size * 2) + 160 (enc_ref_c_size * 4); 161 break; 162 case S5P_MFC_CODEC_H263_ENC: 163 ctx->bank1.size = (enc_ref_y_size * 2) + 164 S5P_FIMV_ENC_UPMV_SIZE + 165 S5P_FIMV_ENC_ACDCCOEF_SIZE; 166 ctx->bank2.size = (enc_ref_y_size * 2) + 167 (enc_ref_c_size * 4); 168 break; 169 default: 170 break; 171 } 172 /* Allocate only if memory from bank 1 is necessary */ 173 if (ctx->bank1.size > 0) { 174 175 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1); 176 if (ret) { 177 mfc_err("Failed to allocate Bank1 temporary buffer\n"); 178 return ret; 179 } 180 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 181 } 182 /* Allocate only if memory from bank 2 is necessary */ 183 if (ctx->bank2.size > 0) { 184 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, &ctx->bank2); 185 if (ret) { 186 mfc_err("Failed to allocate Bank2 temporary buffer\n"); 187 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); 188 return ret; 189 } 190 BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1)); 191 } 192 return 0; 193} 194 195/* Release buffers allocated for codec */ 196static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx) 197{ 198 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); 199 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2); 200} 201 202/* Allocate memory for instance data buffer */ 203static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 204{ 205 struct s5p_mfc_dev *dev = ctx->dev; 206 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 207 int ret; 208 209 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 210 ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 211 ctx->ctx.size = buf_size->h264_ctx; 212 else 213 ctx->ctx.size = buf_size->non_h264_ctx; 214 215 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx); 216 if (ret) { 217 mfc_err("Failed to allocate instance buffer\n"); 218 return ret; 219 } 220 ctx->ctx.ofs = OFFSETA(ctx->ctx.dma); 221 222 /* Zero content of the allocated memory */ 223 memset(ctx->ctx.virt, 0, ctx->ctx.size); 224 wmb(); 225 226 /* Initialize shared memory */ 227 ctx->shm.size = buf_size->shm; 228 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->shm); 229 if (ret) { 230 mfc_err("Failed to allocate shared memory buffer\n"); 231 return ret; 232 } 233 234 /* shared memory offset only keeps the offset from base (port a) */ 235 ctx->shm.ofs = ctx->shm.dma - dev->bank1; 236 BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 237 238 memset(ctx->shm.virt, 0, buf_size->shm); 239 wmb(); 240 return 0; 241} 242 243/* Release instance buffer */ 244static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 245{ 246 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx); 247 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm); 248} 249 250static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev) 251{ 252 /* NOP */ 253 254 return 0; 255} 256 257static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev) 258{ 259 /* NOP */ 260} 261 262static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, 263 unsigned int ofs) 264{ 265 writel(data, (ctx->shm.virt + ofs)); 266 wmb(); 267} 268 269static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, 270 unsigned int ofs) 271{ 272 rmb(); 273 return readl(ctx->shm.virt + ofs); 274} 275 276static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) 277{ 278 unsigned int guard_width, guard_height; 279 280 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); 281 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 282 mfc_debug(2, 283 "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n", 284 ctx->img_width, ctx->img_height, ctx->buf_width, 285 ctx->buf_height); 286 287 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { 288 ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height, 289 S5P_FIMV_DEC_BUF_ALIGN); 290 ctx->chroma_size = ALIGN(ctx->buf_width * 291 ALIGN((ctx->img_height >> 1), 292 S5P_FIMV_NV12MT_VALIGN), 293 S5P_FIMV_DEC_BUF_ALIGN); 294 ctx->mv_size = ALIGN(ctx->buf_width * 295 ALIGN((ctx->buf_height >> 2), 296 S5P_FIMV_NV12MT_VALIGN), 297 S5P_FIMV_DEC_BUF_ALIGN); 298 } else { 299 guard_width = 300 ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN); 301 guard_height = 302 ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN); 303 ctx->luma_size = ALIGN(guard_width * guard_height, 304 S5P_FIMV_DEC_BUF_ALIGN); 305 306 guard_width = 307 ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN); 308 guard_height = 309 ALIGN((ctx->img_height >> 1) + 4, 310 S5P_FIMV_NV12MT_VALIGN); 311 ctx->chroma_size = ALIGN(guard_width * guard_height, 312 S5P_FIMV_DEC_BUF_ALIGN); 313 314 ctx->mv_size = 0; 315 } 316} 317 318static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx) 319{ 320 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 321 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN); 322 323 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) 324 * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN); 325 ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) 326 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN); 327 328 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN); 329 ctx->chroma_size = 330 ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN); 331 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) { 332 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); 333 334 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 335 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 336 ctx->chroma_size = 337 ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 338 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); 339 340 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN); 341 ctx->chroma_size = 342 ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN); 343 } 344} 345 346/* Set registers for decoding temporary buffers */ 347static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) 348{ 349 struct s5p_mfc_dev *dev = ctx->dev; 350 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 351 352 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); 353 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); 354} 355 356/* Set registers for shared buffer */ 357static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) 358{ 359 struct s5p_mfc_dev *dev = ctx->dev; 360 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); 361} 362 363/* Set registers for decoding stream buffer */ 364static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx, 365 int buf_addr, unsigned int start_num_byte, 366 unsigned int buf_size) 367{ 368 struct s5p_mfc_dev *dev = ctx->dev; 369 370 mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR); 371 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE); 372 mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE); 373 s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM); 374 return 0; 375} 376 377/* Set decoding frame buffer */ 378static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) 379{ 380 unsigned int frame_size, i; 381 unsigned int frame_size_ch, frame_size_mv; 382 struct s5p_mfc_dev *dev = ctx->dev; 383 unsigned int dpb; 384 size_t buf_addr1, buf_addr2; 385 int buf_size1, buf_size2; 386 387 buf_addr1 = ctx->bank1.dma; 388 buf_size1 = ctx->bank1.size; 389 buf_addr2 = ctx->bank2.dma; 390 buf_size2 = ctx->bank2.size; 391 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & 392 ~S5P_FIMV_DPB_COUNT_MASK; 393 mfc_write(dev, ctx->total_dpb_count | dpb, 394 S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 395 s5p_mfc_set_shared_buffer(ctx); 396 switch (ctx->codec_mode) { 397 case S5P_MFC_CODEC_H264_DEC: 398 mfc_write(dev, OFFSETA(buf_addr1), 399 S5P_FIMV_H264_VERT_NB_MV_ADR); 400 buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE; 401 buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE; 402 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR); 403 buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE; 404 buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE; 405 break; 406 case S5P_MFC_CODEC_MPEG4_DEC: 407 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR); 408 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 409 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 410 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR); 411 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 412 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 413 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR); 414 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 415 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 416 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR); 417 buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE; 418 buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE; 419 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR); 420 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 421 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 422 break; 423 case S5P_MFC_CODEC_H263_DEC: 424 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR); 425 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 426 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 427 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR); 428 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 429 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 430 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR); 431 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 432 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 433 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR); 434 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 435 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 436 break; 437 case S5P_MFC_CODEC_VC1_DEC: 438 case S5P_MFC_CODEC_VC1RCV_DEC: 439 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR); 440 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 441 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 442 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR); 443 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 444 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 445 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR); 446 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 447 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 448 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR); 449 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 450 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 451 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR); 452 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 453 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 454 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR); 455 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 456 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 457 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR); 458 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 459 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 460 break; 461 case S5P_MFC_CODEC_MPEG2_DEC: 462 break; 463 default: 464 mfc_err("Unknown codec for decoding (%x)\n", 465 ctx->codec_mode); 466 return -EINVAL; 467 } 468 frame_size = ctx->luma_size; 469 frame_size_ch = ctx->chroma_size; 470 frame_size_mv = ctx->mv_size; 471 mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size, frame_size_ch, 472 frame_size_mv); 473 for (i = 0; i < ctx->total_dpb_count; i++) { 474 /* Bank2 */ 475 mfc_debug(2, "Luma %d: %x\n", i, 476 ctx->dst_bufs[i].cookie.raw.luma); 477 mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), 478 S5P_FIMV_DEC_LUMA_ADR + i * 4); 479 mfc_debug(2, "\tChroma %d: %x\n", i, 480 ctx->dst_bufs[i].cookie.raw.chroma); 481 mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), 482 S5P_FIMV_DEC_CHROMA_ADR + i * 4); 483 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { 484 mfc_debug(2, "\tBuf2: %x, size: %d\n", 485 buf_addr2, buf_size2); 486 mfc_write(dev, OFFSETB(buf_addr2), 487 S5P_FIMV_H264_MV_ADR + i * 4); 488 buf_addr2 += frame_size_mv; 489 buf_size2 -= frame_size_mv; 490 } 491 } 492 mfc_debug(2, "Buf1: %u, buf_size1: %d\n", buf_addr1, buf_size1); 493 mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", 494 buf_size1, buf_size2, ctx->total_dpb_count); 495 if (buf_size1 < 0 || buf_size2 < 0) { 496 mfc_debug(2, "Not enough memory has been allocated\n"); 497 return -ENOMEM; 498 } 499 s5p_mfc_write_info_v5(ctx, frame_size, ALLOC_LUMA_DPB_SIZE); 500 s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); 501 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) 502 s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE); 503 mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) 504 << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), 505 S5P_FIMV_SI_CH0_INST_ID); 506 return 0; 507} 508 509/* Set registers for encoding stream buffer */ 510static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx, 511 unsigned long addr, unsigned int size) 512{ 513 struct s5p_mfc_dev *dev = ctx->dev; 514 515 mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR); 516 mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE); 517 return 0; 518} 519 520static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, 521 unsigned long y_addr, unsigned long c_addr) 522{ 523 struct s5p_mfc_dev *dev = ctx->dev; 524 525 mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR); 526 mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR); 527} 528 529static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, 530 unsigned long *y_addr, unsigned long *c_addr) 531{ 532 struct s5p_mfc_dev *dev = ctx->dev; 533 534 *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) 535 << MFC_OFFSET_SHIFT); 536 *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) 537 << MFC_OFFSET_SHIFT); 538} 539 540/* Set encoding ref & codec buffer */ 541static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) 542{ 543 struct s5p_mfc_dev *dev = ctx->dev; 544 size_t buf_addr1, buf_addr2; 545 size_t buf_size1, buf_size2; 546 unsigned int enc_ref_y_size, enc_ref_c_size; 547 unsigned int guard_width, guard_height; 548 int i; 549 550 buf_addr1 = ctx->bank1.dma; 551 buf_size1 = ctx->bank1.size; 552 buf_addr2 = ctx->bank2.dma; 553 buf_size2 = ctx->bank2.size; 554 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 555 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 556 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); 557 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { 558 enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 559 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); 560 enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN); 561 } else { 562 guard_width = ALIGN(ctx->img_width + 16, 563 S5P_FIMV_NV12MT_HALIGN); 564 guard_height = ALIGN((ctx->img_height >> 1) + 4, 565 S5P_FIMV_NV12MT_VALIGN); 566 enc_ref_c_size = ALIGN(guard_width * guard_height, 567 S5P_FIMV_NV12MT_SALIGN); 568 } 569 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", buf_size1, buf_size2); 570 switch (ctx->codec_mode) { 571 case S5P_MFC_CODEC_H264_ENC: 572 for (i = 0; i < 2; i++) { 573 mfc_write(dev, OFFSETA(buf_addr1), 574 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 575 buf_addr1 += enc_ref_y_size; 576 buf_size1 -= enc_ref_y_size; 577 578 mfc_write(dev, OFFSETB(buf_addr2), 579 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 580 buf_addr2 += enc_ref_y_size; 581 buf_size2 -= enc_ref_y_size; 582 } 583 for (i = 0; i < 4; i++) { 584 mfc_write(dev, OFFSETB(buf_addr2), 585 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 586 buf_addr2 += enc_ref_c_size; 587 buf_size2 -= enc_ref_c_size; 588 } 589 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR); 590 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 591 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 592 mfc_write(dev, OFFSETA(buf_addr1), 593 S5P_FIMV_H264_COZERO_FLAG_ADR); 594 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; 595 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; 596 mfc_write(dev, OFFSETA(buf_addr1), 597 S5P_FIMV_H264_UP_INTRA_MD_ADR); 598 buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE; 599 buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE; 600 mfc_write(dev, OFFSETB(buf_addr2), 601 S5P_FIMV_H264_UP_INTRA_PRED_ADR); 602 buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE; 603 buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE; 604 mfc_write(dev, OFFSETA(buf_addr1), 605 S5P_FIMV_H264_NBOR_INFO_ADR); 606 buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; 607 buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; 608 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", 609 buf_size1, buf_size2); 610 break; 611 case S5P_MFC_CODEC_MPEG4_ENC: 612 for (i = 0; i < 2; i++) { 613 mfc_write(dev, OFFSETA(buf_addr1), 614 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 615 buf_addr1 += enc_ref_y_size; 616 buf_size1 -= enc_ref_y_size; 617 mfc_write(dev, OFFSETB(buf_addr2), 618 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 619 buf_addr2 += enc_ref_y_size; 620 buf_size2 -= enc_ref_y_size; 621 } 622 for (i = 0; i < 4; i++) { 623 mfc_write(dev, OFFSETB(buf_addr2), 624 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 625 buf_addr2 += enc_ref_c_size; 626 buf_size2 -= enc_ref_c_size; 627 } 628 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR); 629 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 630 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 631 mfc_write(dev, OFFSETA(buf_addr1), 632 S5P_FIMV_MPEG4_COZERO_FLAG_ADR); 633 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; 634 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; 635 mfc_write(dev, OFFSETA(buf_addr1), 636 S5P_FIMV_MPEG4_ACDC_COEF_ADR); 637 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; 638 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; 639 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", 640 buf_size1, buf_size2); 641 break; 642 case S5P_MFC_CODEC_H263_ENC: 643 for (i = 0; i < 2; i++) { 644 mfc_write(dev, OFFSETA(buf_addr1), 645 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 646 buf_addr1 += enc_ref_y_size; 647 buf_size1 -= enc_ref_y_size; 648 mfc_write(dev, OFFSETB(buf_addr2), 649 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 650 buf_addr2 += enc_ref_y_size; 651 buf_size2 -= enc_ref_y_size; 652 } 653 for (i = 0; i < 4; i++) { 654 mfc_write(dev, OFFSETB(buf_addr2), 655 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 656 buf_addr2 += enc_ref_c_size; 657 buf_size2 -= enc_ref_c_size; 658 } 659 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR); 660 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 661 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 662 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); 663 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; 664 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; 665 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", 666 buf_size1, buf_size2); 667 break; 668 default: 669 mfc_err("Unknown codec set for encoding: %d\n", 670 ctx->codec_mode); 671 return -EINVAL; 672 } 673 return 0; 674} 675 676static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) 677{ 678 struct s5p_mfc_dev *dev = ctx->dev; 679 struct s5p_mfc_enc_params *p = &ctx->enc_params; 680 unsigned int reg; 681 unsigned int shm; 682 683 /* width */ 684 mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX); 685 /* height */ 686 mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX); 687 /* pictype : enable, IDR period */ 688 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 689 reg |= (1 << 18); 690 reg &= ~(0xFFFF); 691 reg |= p->gop_size; 692 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 693 mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON); 694 /* multi-slice control */ 695 /* multi-slice MB number or bit size */ 696 mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL); 697 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 698 mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB); 699 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 700 mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT); 701 } else { 702 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB); 703 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT); 704 } 705 /* cyclic intra refresh */ 706 mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL); 707 /* memory structure cur. frame */ 708 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) 709 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); 710 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) 711 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); 712 /* padding control & value */ 713 reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); 714 if (p->pad) { 715 /** enable */ 716 reg |= (1 << 31); 717 /** cr value */ 718 reg &= ~(0xFF << 16); 719 reg |= (p->pad_cr << 16); 720 /** cb value */ 721 reg &= ~(0xFF << 8); 722 reg |= (p->pad_cb << 8); 723 /** y value */ 724 reg &= ~(0xFF); 725 reg |= (p->pad_luma); 726 } else { 727 /** disable & all value clear */ 728 reg = 0; 729 } 730 mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); 731 /* rate control config. */ 732 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 733 /** frame-level rate control */ 734 reg &= ~(0x1 << 9); 735 reg |= (p->rc_frame << 9); 736 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 737 /* bit rate */ 738 if (p->rc_frame) 739 mfc_write(dev, p->rc_bitrate, 740 S5P_FIMV_ENC_RC_BIT_RATE); 741 else 742 mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE); 743 /* reaction coefficient */ 744 if (p->rc_frame) 745 mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA); 746 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 747 /* seq header ctrl */ 748 shm &= ~(0x1 << 3); 749 shm |= (p->seq_hdr_mode << 3); 750 /* frame skip mode */ 751 shm &= ~(0x3 << 1); 752 shm |= (p->frame_skip_mode << 1); 753 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 754 /* fixed target bit */ 755 s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); 756 return 0; 757} 758 759static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 760{ 761 struct s5p_mfc_dev *dev = ctx->dev; 762 struct s5p_mfc_enc_params *p = &ctx->enc_params; 763 struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; 764 unsigned int reg; 765 unsigned int shm; 766 767 s5p_mfc_set_enc_params(ctx); 768 /* pictype : number of B */ 769 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 770 /* num_b_frame - 0 ~ 2 */ 771 reg &= ~(0x3 << 16); 772 reg |= (p->num_b_frame << 16); 773 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 774 /* profile & level */ 775 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); 776 /* level */ 777 reg &= ~(0xFF << 8); 778 reg |= (p_264->level << 8); 779 /* profile - 0 ~ 2 */ 780 reg &= ~(0x3F); 781 reg |= p_264->profile; 782 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); 783 /* interlace */ 784 mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT); 785 /* height */ 786 if (p_264->interlace) 787 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); 788 /* loopfilter ctrl */ 789 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); 790 /* loopfilter alpha offset */ 791 if (p_264->loop_filter_alpha < 0) { 792 reg = 0x10; 793 reg |= (0xFF - p_264->loop_filter_alpha) + 1; 794 } else { 795 reg = 0x00; 796 reg |= (p_264->loop_filter_alpha & 0xF); 797 } 798 mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); 799 /* loopfilter beta offset */ 800 if (p_264->loop_filter_beta < 0) { 801 reg = 0x10; 802 reg |= (0xFF - p_264->loop_filter_beta) + 1; 803 } else { 804 reg = 0x00; 805 reg |= (p_264->loop_filter_beta & 0xF); 806 } 807 mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); 808 /* entropy coding mode */ 809 if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 810 mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE); 811 else 812 mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE); 813 /* number of ref. picture */ 814 reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); 815 /* num of ref. pictures of P */ 816 reg &= ~(0x3 << 5); 817 reg |= (p_264->num_ref_pic_4p << 5); 818 /* max number of ref. pictures */ 819 reg &= ~(0x1F); 820 reg |= p_264->max_ref_pic; 821 mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); 822 /* 8x8 transform enable */ 823 mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG); 824 /* rate control config. */ 825 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 826 /* macroblock level rate control */ 827 reg &= ~(0x1 << 8); 828 reg |= (p->rc_mb << 8); 829 /* frame QP */ 830 reg &= ~(0x3F); 831 reg |= p_264->rc_frame_qp; 832 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 833 /* frame rate */ 834 if (p->rc_frame && p->rc_framerate_denom) 835 mfc_write(dev, p->rc_framerate_num * 1000 836 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); 837 else 838 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 839 /* max & min value of QP */ 840 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 841 /* max QP */ 842 reg &= ~(0x3F << 8); 843 reg |= (p_264->rc_max_qp << 8); 844 /* min QP */ 845 reg &= ~(0x3F); 846 reg |= p_264->rc_min_qp; 847 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 848 /* macroblock adaptive scaling features */ 849 if (p->rc_mb) { 850 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); 851 /* dark region */ 852 reg &= ~(0x1 << 3); 853 reg |= (p_264->rc_mb_dark << 3); 854 /* smooth region */ 855 reg &= ~(0x1 << 2); 856 reg |= (p_264->rc_mb_smooth << 2); 857 /* static region */ 858 reg &= ~(0x1 << 1); 859 reg |= (p_264->rc_mb_static << 1); 860 /* high activity region */ 861 reg &= ~(0x1); 862 reg |= p_264->rc_mb_activity; 863 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); 864 } 865 if (!p->rc_frame && !p->rc_mb) { 866 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 867 shm &= ~(0xFFF); 868 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); 869 shm |= (p_264->rc_p_frame_qp & 0x3F); 870 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 871 } 872 /* extended encoder ctrl */ 873 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 874 /* AR VUI control */ 875 shm &= ~(0x1 << 15); 876 shm |= (p_264->vui_sar << 1); 877 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 878 if (p_264->vui_sar) { 879 /* aspect ration IDC */ 880 shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC); 881 shm &= ~(0xFF); 882 shm |= p_264->vui_sar_idc; 883 s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC); 884 if (p_264->vui_sar_idc == 0xFF) { 885 /* sample AR info */ 886 shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR); 887 shm &= ~(0xFFFFFFFF); 888 shm |= p_264->vui_ext_sar_width << 16; 889 shm |= p_264->vui_ext_sar_height; 890 s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR); 891 } 892 } 893 /* intra picture period for H.264 */ 894 shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD); 895 /* control */ 896 shm &= ~(0x1 << 16); 897 shm |= (p_264->open_gop << 16); 898 /* value */ 899 if (p_264->open_gop) { 900 shm &= ~(0xFFFF); 901 shm |= p_264->open_gop_size; 902 } 903 s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD); 904 /* extended encoder ctrl */ 905 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 906 /* vbv buffer size */ 907 if (p->frame_skip_mode == 908 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 909 shm &= ~(0xFFFF << 16); 910 shm |= (p_264->cpb_size << 16); 911 } 912 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 913 return 0; 914} 915 916static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) 917{ 918 struct s5p_mfc_dev *dev = ctx->dev; 919 struct s5p_mfc_enc_params *p = &ctx->enc_params; 920 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; 921 unsigned int reg; 922 unsigned int shm; 923 unsigned int framerate; 924 925 s5p_mfc_set_enc_params(ctx); 926 /* pictype : number of B */ 927 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 928 /* num_b_frame - 0 ~ 2 */ 929 reg &= ~(0x3 << 16); 930 reg |= (p->num_b_frame << 16); 931 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 932 /* profile & level */ 933 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); 934 /* level */ 935 reg &= ~(0xFF << 8); 936 reg |= (p_mpeg4->level << 8); 937 /* profile - 0 ~ 2 */ 938 reg &= ~(0x3F); 939 reg |= p_mpeg4->profile; 940 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); 941 /* quarter_pixel */ 942 mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); 943 /* qp */ 944 if (!p->rc_frame) { 945 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 946 shm &= ~(0xFFF); 947 shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6); 948 shm |= (p_mpeg4->rc_p_frame_qp & 0x3F); 949 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 950 } 951 /* frame rate */ 952 if (p->rc_frame) { 953 if (p->rc_framerate_denom > 0) { 954 framerate = p->rc_framerate_num * 1000 / 955 p->rc_framerate_denom; 956 mfc_write(dev, framerate, 957 S5P_FIMV_ENC_RC_FRAME_RATE); 958 shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING); 959 shm &= ~(0xFFFFFFFF); 960 shm |= (1 << 31); 961 shm |= ((p->rc_framerate_num & 0x7FFF) << 16); 962 shm |= (p->rc_framerate_denom & 0xFFFF); 963 s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING); 964 } 965 } else { 966 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 967 } 968 /* rate control config. */ 969 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 970 /* frame QP */ 971 reg &= ~(0x3F); 972 reg |= p_mpeg4->rc_frame_qp; 973 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 974 /* max & min value of QP */ 975 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 976 /* max QP */ 977 reg &= ~(0x3F << 8); 978 reg |= (p_mpeg4->rc_max_qp << 8); 979 /* min QP */ 980 reg &= ~(0x3F); 981 reg |= p_mpeg4->rc_min_qp; 982 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 983 /* extended encoder ctrl */ 984 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 985 /* vbv buffer size */ 986 if (p->frame_skip_mode == 987 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 988 shm &= ~(0xFFFF << 16); 989 shm |= (p->vbv_size << 16); 990 } 991 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 992 return 0; 993} 994 995static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) 996{ 997 struct s5p_mfc_dev *dev = ctx->dev; 998 struct s5p_mfc_enc_params *p = &ctx->enc_params; 999 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; 1000 unsigned int reg; 1001 unsigned int shm; 1002 1003 s5p_mfc_set_enc_params(ctx); 1004 /* qp */ 1005 if (!p->rc_frame) { 1006 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 1007 shm &= ~(0xFFF); 1008 shm |= (p_h263->rc_p_frame_qp & 0x3F); 1009 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 1010 } 1011 /* frame rate */ 1012 if (p->rc_frame && p->rc_framerate_denom) 1013 mfc_write(dev, p->rc_framerate_num * 1000 1014 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); 1015 else 1016 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 1017 /* rate control config. */ 1018 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 1019 /* frame QP */ 1020 reg &= ~(0x3F); 1021 reg |= p_h263->rc_frame_qp; 1022 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 1023 /* max & min value of QP */ 1024 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 1025 /* max QP */ 1026 reg &= ~(0x3F << 8); 1027 reg |= (p_h263->rc_max_qp << 8); 1028 /* min QP */ 1029 reg &= ~(0x3F); 1030 reg |= p_h263->rc_min_qp; 1031 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 1032 /* extended encoder ctrl */ 1033 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 1034 /* vbv buffer size */ 1035 if (p->frame_skip_mode == 1036 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1037 shm &= ~(0xFFFF << 16); 1038 shm |= (p->vbv_size << 16); 1039 } 1040 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 1041 return 0; 1042} 1043 1044/* Initialize decoding */ 1045static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx) 1046{ 1047 struct s5p_mfc_dev *dev = ctx->dev; 1048 1049 s5p_mfc_set_shared_buffer(ctx); 1050 /* Setup loop filter, for decoding this is only valid for MPEG4 */ 1051 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) 1052 mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL); 1053 else 1054 mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL); 1055 mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) << 1056 S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable << 1057 S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay & 1058 S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT), 1059 S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 1060 mfc_write(dev, 1061 ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) 1062 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1063 return 0; 1064} 1065 1066static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) 1067{ 1068 struct s5p_mfc_dev *dev = ctx->dev; 1069 unsigned int dpb; 1070 1071 if (flush) 1072 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | ( 1073 S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); 1074 else 1075 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & 1076 ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); 1077 mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 1078} 1079 1080/* Decode a single frame */ 1081static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx, 1082 enum s5p_mfc_decode_arg last_frame) 1083{ 1084 struct s5p_mfc_dev *dev = ctx->dev; 1085 1086 mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF); 1087 s5p_mfc_set_shared_buffer(ctx); 1088 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); 1089 /* Issue different commands to instance basing on whether it 1090 * is the last frame or not. */ 1091 switch (last_frame) { 1092 case MFC_DEC_FRAME: 1093 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) << 1094 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1095 break; 1096 case MFC_DEC_LAST_FRAME: 1097 mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) << 1098 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1099 break; 1100 case MFC_DEC_RES_CHANGE: 1101 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC & 1102 S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), 1103 S5P_FIMV_SI_CH0_INST_ID); 1104 break; 1105 } 1106 mfc_debug(2, "Decoding a usual frame\n"); 1107 return 0; 1108} 1109 1110static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx) 1111{ 1112 struct s5p_mfc_dev *dev = ctx->dev; 1113 1114 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 1115 s5p_mfc_set_enc_params_h264(ctx); 1116 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) 1117 s5p_mfc_set_enc_params_mpeg4(ctx); 1118 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) 1119 s5p_mfc_set_enc_params_h263(ctx); 1120 else { 1121 mfc_err("Unknown codec for encoding (%x)\n", 1122 ctx->codec_mode); 1123 return -EINVAL; 1124 } 1125 s5p_mfc_set_shared_buffer(ctx); 1126 mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | 1127 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1128 return 0; 1129} 1130 1131/* Encode a single frame */ 1132static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx) 1133{ 1134 struct s5p_mfc_dev *dev = ctx->dev; 1135 int cmd; 1136 /* memory structure cur. frame */ 1137 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) 1138 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); 1139 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) 1140 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); 1141 s5p_mfc_set_shared_buffer(ctx); 1142 1143 if (ctx->state == MFCINST_FINISHING) 1144 cmd = S5P_FIMV_CH_LAST_FRAME; 1145 else 1146 cmd = S5P_FIMV_CH_FRAME_START; 1147 mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) 1148 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1149 1150 return 0; 1151} 1152 1153static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) 1154{ 1155 unsigned long flags; 1156 int new_ctx; 1157 int cnt; 1158 1159 spin_lock_irqsave(&dev->condlock, flags); 1160 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; 1161 cnt = 0; 1162 while (!test_bit(new_ctx, &dev->ctx_work_bits)) { 1163 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; 1164 if (++cnt > MFC_NUM_CONTEXTS) { 1165 /* No contexts to run */ 1166 spin_unlock_irqrestore(&dev->condlock, flags); 1167 return -EAGAIN; 1168 } 1169 } 1170 spin_unlock_irqrestore(&dev->condlock, flags); 1171 return new_ctx; 1172} 1173 1174static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx) 1175{ 1176 struct s5p_mfc_dev *dev = ctx->dev; 1177 1178 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); 1179 dev->curr_ctx = ctx->num; 1180 s5p_mfc_clean_ctx_int_flags(ctx); 1181 s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE); 1182} 1183 1184static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) 1185{ 1186 struct s5p_mfc_dev *dev = ctx->dev; 1187 struct s5p_mfc_buf *temp_vb; 1188 unsigned long flags; 1189 unsigned int index; 1190 1191 if (ctx->state == MFCINST_FINISHING) { 1192 last_frame = MFC_DEC_LAST_FRAME; 1193 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); 1194 dev->curr_ctx = ctx->num; 1195 s5p_mfc_clean_ctx_int_flags(ctx); 1196 s5p_mfc_decode_one_frame_v5(ctx, last_frame); 1197 return 0; 1198 } 1199 1200 spin_lock_irqsave(&dev->irqlock, flags); 1201 /* Frames are being decoded */ 1202 if (list_empty(&ctx->src_queue)) { 1203 mfc_debug(2, "No src buffers\n"); 1204 spin_unlock_irqrestore(&dev->irqlock, flags); 1205 return -EAGAIN; 1206 } 1207 /* Get the next source buffer */ 1208 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1209 temp_vb->flags |= MFC_BUF_FLAG_USED; 1210 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1211 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1212 ctx->consumed_stream, temp_vb->b->v4l2_planes[0].bytesused); 1213 spin_unlock_irqrestore(&dev->irqlock, flags); 1214 index = temp_vb->b->v4l2_buf.index; 1215 dev->curr_ctx = ctx->num; 1216 s5p_mfc_clean_ctx_int_flags(ctx); 1217 if (temp_vb->b->v4l2_planes[0].bytesused == 0) { 1218 last_frame = MFC_DEC_LAST_FRAME; 1219 mfc_debug(2, "Setting ctx->state to FINISHING\n"); 1220 ctx->state = MFCINST_FINISHING; 1221 } 1222 s5p_mfc_decode_one_frame_v5(ctx, last_frame); 1223 return 0; 1224} 1225 1226static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) 1227{ 1228 struct s5p_mfc_dev *dev = ctx->dev; 1229 unsigned long flags; 1230 struct s5p_mfc_buf *dst_mb; 1231 struct s5p_mfc_buf *src_mb; 1232 unsigned long src_y_addr, src_c_addr, dst_addr; 1233 unsigned int dst_size; 1234 1235 spin_lock_irqsave(&dev->irqlock, flags); 1236 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) { 1237 mfc_debug(2, "no src buffers\n"); 1238 spin_unlock_irqrestore(&dev->irqlock, flags); 1239 return -EAGAIN; 1240 } 1241 if (list_empty(&ctx->dst_queue)) { 1242 mfc_debug(2, "no dst buffers\n"); 1243 spin_unlock_irqrestore(&dev->irqlock, flags); 1244 return -EAGAIN; 1245 } 1246 if (list_empty(&ctx->src_queue)) { 1247 /* send null frame */ 1248 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2); 1249 src_mb = NULL; 1250 } else { 1251 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 1252 list); 1253 src_mb->flags |= MFC_BUF_FLAG_USED; 1254 if (src_mb->b->v4l2_planes[0].bytesused == 0) { 1255 /* send null frame */ 1256 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, 1257 dev->bank2); 1258 ctx->state = MFCINST_FINISHING; 1259 } else { 1260 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1261 0); 1262 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1263 1); 1264 s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr, 1265 src_c_addr); 1266 if (src_mb->flags & MFC_BUF_FLAG_EOS) 1267 ctx->state = MFCINST_FINISHING; 1268 } 1269 } 1270 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1271 dst_mb->flags |= MFC_BUF_FLAG_USED; 1272 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1273 dst_size = vb2_plane_size(dst_mb->b, 0); 1274 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); 1275 spin_unlock_irqrestore(&dev->irqlock, flags); 1276 dev->curr_ctx = ctx->num; 1277 s5p_mfc_clean_ctx_int_flags(ctx); 1278 mfc_debug(2, "encoding buffer with index=%d state=%d\n", 1279 src_mb ? src_mb->b->v4l2_buf.index : -1, ctx->state); 1280 s5p_mfc_encode_one_frame_v5(ctx); 1281 return 0; 1282} 1283 1284static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) 1285{ 1286 struct s5p_mfc_dev *dev = ctx->dev; 1287 unsigned long flags; 1288 struct s5p_mfc_buf *temp_vb; 1289 1290 /* Initializing decoding - parsing header */ 1291 spin_lock_irqsave(&dev->irqlock, flags); 1292 mfc_debug(2, "Preparing to init decoding\n"); 1293 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1294 s5p_mfc_set_dec_desc_buffer(ctx); 1295 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); 1296 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1297 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1298 0, temp_vb->b->v4l2_planes[0].bytesused); 1299 spin_unlock_irqrestore(&dev->irqlock, flags); 1300 dev->curr_ctx = ctx->num; 1301 s5p_mfc_clean_ctx_int_flags(ctx); 1302 s5p_mfc_init_decode_v5(ctx); 1303} 1304 1305static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) 1306{ 1307 struct s5p_mfc_dev *dev = ctx->dev; 1308 unsigned long flags; 1309 struct s5p_mfc_buf *dst_mb; 1310 unsigned long dst_addr; 1311 unsigned int dst_size; 1312 1313 s5p_mfc_set_enc_ref_buffer_v5(ctx); 1314 spin_lock_irqsave(&dev->irqlock, flags); 1315 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1316 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1317 dst_size = vb2_plane_size(dst_mb->b, 0); 1318 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); 1319 spin_unlock_irqrestore(&dev->irqlock, flags); 1320 dev->curr_ctx = ctx->num; 1321 s5p_mfc_clean_ctx_int_flags(ctx); 1322 s5p_mfc_init_encode_v5(ctx); 1323} 1324 1325static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) 1326{ 1327 struct s5p_mfc_dev *dev = ctx->dev; 1328 unsigned long flags; 1329 struct s5p_mfc_buf *temp_vb; 1330 int ret; 1331 1332 /* 1333 * Header was parsed now starting processing 1334 * First set the output frame buffers 1335 */ 1336 if (ctx->capture_state != QUEUE_BUFS_MMAPED) { 1337 mfc_err("It seems that not all destionation buffers were " 1338 "mmaped\nMFC requires that all destination are mmaped " 1339 "before starting processing\n"); 1340 return -EAGAIN; 1341 } 1342 spin_lock_irqsave(&dev->irqlock, flags); 1343 if (list_empty(&ctx->src_queue)) { 1344 mfc_err("Header has been deallocated in the middle of" 1345 " initialization\n"); 1346 spin_unlock_irqrestore(&dev->irqlock, flags); 1347 return -EIO; 1348 } 1349 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1350 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); 1351 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1352 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1353 0, temp_vb->b->v4l2_planes[0].bytesused); 1354 spin_unlock_irqrestore(&dev->irqlock, flags); 1355 dev->curr_ctx = ctx->num; 1356 s5p_mfc_clean_ctx_int_flags(ctx); 1357 ret = s5p_mfc_set_dec_frame_buffer_v5(ctx); 1358 if (ret) { 1359 mfc_err("Failed to alloc frame mem\n"); 1360 ctx->state = MFCINST_ERROR; 1361 } 1362 return ret; 1363} 1364 1365/* Try running an operation on hardware */ 1366static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev) 1367{ 1368 struct s5p_mfc_ctx *ctx; 1369 int new_ctx; 1370 unsigned int ret = 0; 1371 1372 if (test_bit(0, &dev->enter_suspend)) { 1373 mfc_debug(1, "Entering suspend so do not schedule any jobs\n"); 1374 return; 1375 } 1376 /* Check whether hardware is not running */ 1377 if (test_and_set_bit(0, &dev->hw_lock) != 0) { 1378 /* This is perfectly ok, the scheduled ctx should wait */ 1379 mfc_debug(1, "Couldn't lock HW\n"); 1380 return; 1381 } 1382 /* Choose the context to run */ 1383 new_ctx = s5p_mfc_get_new_ctx(dev); 1384 if (new_ctx < 0) { 1385 /* No contexts to run */ 1386 if (test_and_clear_bit(0, &dev->hw_lock) == 0) { 1387 mfc_err("Failed to unlock hardware\n"); 1388 return; 1389 } 1390 mfc_debug(1, "No ctx is scheduled to be run\n"); 1391 return; 1392 } 1393 ctx = dev->ctx[new_ctx]; 1394 /* Got context to run in ctx */ 1395 /* 1396 * Last frame has already been sent to MFC. 1397 * Now obtaining frames from MFC buffer 1398 */ 1399 s5p_mfc_clock_on(); 1400 if (ctx->type == MFCINST_DECODER) { 1401 s5p_mfc_set_dec_desc_buffer(ctx); 1402 switch (ctx->state) { 1403 case MFCINST_FINISHING: 1404 s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME); 1405 break; 1406 case MFCINST_RUNNING: 1407 ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); 1408 break; 1409 case MFCINST_INIT: 1410 s5p_mfc_clean_ctx_int_flags(ctx); 1411 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1412 ctx); 1413 break; 1414 case MFCINST_RETURN_INST: 1415 s5p_mfc_clean_ctx_int_flags(ctx); 1416 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1417 ctx); 1418 break; 1419 case MFCINST_GOT_INST: 1420 s5p_mfc_run_init_dec(ctx); 1421 break; 1422 case MFCINST_HEAD_PARSED: 1423 ret = s5p_mfc_run_init_dec_buffers(ctx); 1424 mfc_debug(1, "head parsed\n"); 1425 break; 1426 case MFCINST_RES_CHANGE_INIT: 1427 s5p_mfc_run_res_change(ctx); 1428 break; 1429 case MFCINST_RES_CHANGE_FLUSH: 1430 s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); 1431 break; 1432 case MFCINST_RES_CHANGE_END: 1433 mfc_debug(2, "Finished remaining frames after resolution change\n"); 1434 ctx->capture_state = QUEUE_FREE; 1435 mfc_debug(2, "Will re-init the codec\n"); 1436 s5p_mfc_run_init_dec(ctx); 1437 break; 1438 default: 1439 ret = -EAGAIN; 1440 } 1441 } else if (ctx->type == MFCINST_ENCODER) { 1442 switch (ctx->state) { 1443 case MFCINST_FINISHING: 1444 case MFCINST_RUNNING: 1445 ret = s5p_mfc_run_enc_frame(ctx); 1446 break; 1447 case MFCINST_INIT: 1448 s5p_mfc_clean_ctx_int_flags(ctx); 1449 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1450 ctx); 1451 break; 1452 case MFCINST_RETURN_INST: 1453 s5p_mfc_clean_ctx_int_flags(ctx); 1454 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1455 ctx); 1456 break; 1457 case MFCINST_GOT_INST: 1458 s5p_mfc_run_init_enc(ctx); 1459 break; 1460 default: 1461 ret = -EAGAIN; 1462 } 1463 } else { 1464 mfc_err("Invalid context type: %d\n", ctx->type); 1465 ret = -EAGAIN; 1466 } 1467 1468 if (ret) { 1469 /* Free hardware lock */ 1470 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 1471 mfc_err("Failed to unlock hardware\n"); 1472 1473 /* This is in deed imporant, as no operation has been 1474 * scheduled, reduce the clock count as no one will 1475 * ever do this, because no interrupt related to this try_run 1476 * will ever come from hardware. */ 1477 s5p_mfc_clock_off(); 1478 } 1479} 1480 1481 1482static void s5p_mfc_cleanup_queue_v5(struct list_head *lh, struct vb2_queue *vq) 1483{ 1484 struct s5p_mfc_buf *b; 1485 int i; 1486 1487 while (!list_empty(lh)) { 1488 b = list_entry(lh->next, struct s5p_mfc_buf, list); 1489 for (i = 0; i < b->b->num_planes; i++) 1490 vb2_set_plane_payload(b->b, i, 0); 1491 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); 1492 list_del(&b->list); 1493 } 1494} 1495 1496static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev) 1497{ 1498 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 1499 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 1500 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 1501} 1502 1503static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev) 1504{ 1505 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT; 1506} 1507 1508static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev) 1509{ 1510 return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT; 1511} 1512 1513static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev) 1514{ 1515 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS); 1516} 1517 1518static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev) 1519{ 1520 return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS); 1521} 1522 1523static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev) 1524{ 1525 return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) & 1526 S5P_FIMV_DECODE_FRAME_MASK; 1527} 1528 1529static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx) 1530{ 1531 return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >> 1532 S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) & 1533 S5P_FIMV_DECODE_FRAME_MASK; 1534} 1535 1536static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev) 1537{ 1538 return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES); 1539} 1540 1541static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev) 1542{ 1543 int reason; 1544 reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) & 1545 S5P_FIMV_RISC2HOST_CMD_MASK; 1546 switch (reason) { 1547 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: 1548 reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET; 1549 break; 1550 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: 1551 reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET; 1552 break; 1553 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: 1554 reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET; 1555 break; 1556 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: 1557 reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET; 1558 break; 1559 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: 1560 reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET; 1561 break; 1562 case S5P_FIMV_R2H_CMD_SYS_INIT_RET: 1563 reason = S5P_MFC_R2H_CMD_SYS_INIT_RET; 1564 break; 1565 case S5P_FIMV_R2H_CMD_FW_STATUS_RET: 1566 reason = S5P_MFC_R2H_CMD_FW_STATUS_RET; 1567 break; 1568 case S5P_FIMV_R2H_CMD_SLEEP_RET: 1569 reason = S5P_MFC_R2H_CMD_SLEEP_RET; 1570 break; 1571 case S5P_FIMV_R2H_CMD_WAKEUP_RET: 1572 reason = S5P_MFC_R2H_CMD_WAKEUP_RET; 1573 break; 1574 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: 1575 reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET; 1576 break; 1577 case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET: 1578 reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET; 1579 break; 1580 case S5P_FIMV_R2H_CMD_ERR_RET: 1581 reason = S5P_MFC_R2H_CMD_ERR_RET; 1582 break; 1583 default: 1584 reason = S5P_MFC_R2H_CMD_EMPTY; 1585 } 1586 return reason; 1587} 1588 1589static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev) 1590{ 1591 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2); 1592} 1593 1594static int s5p_mfc_err_dec_v5(unsigned int err) 1595{ 1596 return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT; 1597} 1598 1599static int s5p_mfc_err_dspl_v5(unsigned int err) 1600{ 1601 return (err & S5P_FIMV_ERR_DSPL_MASK) >> S5P_FIMV_ERR_DSPL_SHIFT; 1602} 1603 1604static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev) 1605{ 1606 return mfc_read(dev, S5P_FIMV_SI_HRESOL); 1607} 1608 1609static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev) 1610{ 1611 return mfc_read(dev, S5P_FIMV_SI_VRESOL); 1612} 1613 1614static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev) 1615{ 1616 return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER); 1617} 1618 1619static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev) 1620{ 1621 /* NOP */ 1622 return -1; 1623} 1624 1625static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev) 1626{ 1627 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1); 1628} 1629 1630static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev) 1631{ 1632 return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE); 1633} 1634 1635static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev) 1636{ 1637 return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE); 1638} 1639 1640static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev) 1641{ 1642 return -1; 1643} 1644 1645static int s5p_mfc_get_enc_pic_count_v5(struct s5p_mfc_dev *dev) 1646{ 1647 return mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT); 1648} 1649 1650static int s5p_mfc_get_sei_avail_status_v5(struct s5p_mfc_ctx *ctx) 1651{ 1652 return s5p_mfc_read_info_v5(ctx, FRAME_PACK_SEI_AVAIL); 1653} 1654 1655static int s5p_mfc_get_mvc_num_views_v5(struct s5p_mfc_dev *dev) 1656{ 1657 return -1; 1658} 1659 1660static int s5p_mfc_get_mvc_view_id_v5(struct s5p_mfc_dev *dev) 1661{ 1662 return -1; 1663} 1664 1665static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx) 1666{ 1667 return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP); 1668} 1669 1670static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx) 1671{ 1672 return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT); 1673} 1674 1675static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx) 1676{ 1677 return s5p_mfc_read_info_v5(ctx, CROP_INFO_H); 1678} 1679 1680static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx) 1681{ 1682 return s5p_mfc_read_info_v5(ctx, CROP_INFO_V); 1683} 1684 1685/* Initialize opr function pointers for MFC v5 */ 1686static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { 1687 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5, 1688 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5, 1689 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5, 1690 .release_codec_buffers = s5p_mfc_release_codec_buffers_v5, 1691 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5, 1692 .release_instance_buffer = s5p_mfc_release_instance_buffer_v5, 1693 .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5, 1694 .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5, 1695 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5, 1696 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5, 1697 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v5, 1698 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v5, 1699 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5, 1700 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5, 1701 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5, 1702 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v5, 1703 .init_decode = s5p_mfc_init_decode_v5, 1704 .init_encode = s5p_mfc_init_encode_v5, 1705 .encode_one_frame = s5p_mfc_encode_one_frame_v5, 1706 .try_run = s5p_mfc_try_run_v5, 1707 .cleanup_queue = s5p_mfc_cleanup_queue_v5, 1708 .clear_int_flags = s5p_mfc_clear_int_flags_v5, 1709 .write_info = s5p_mfc_write_info_v5, 1710 .read_info = s5p_mfc_read_info_v5, 1711 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5, 1712 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5, 1713 .get_dspl_status = s5p_mfc_get_dspl_status_v5, 1714 .get_dec_status = s5p_mfc_get_dec_status_v5, 1715 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5, 1716 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5, 1717 .get_consumed_stream = s5p_mfc_get_consumed_stream_v5, 1718 .get_int_reason = s5p_mfc_get_int_reason_v5, 1719 .get_int_err = s5p_mfc_get_int_err_v5, 1720 .err_dec = s5p_mfc_err_dec_v5, 1721 .err_dspl = s5p_mfc_err_dspl_v5, 1722 .get_img_width = s5p_mfc_get_img_width_v5, 1723 .get_img_height = s5p_mfc_get_img_height_v5, 1724 .get_dpb_count = s5p_mfc_get_dpb_count_v5, 1725 .get_mv_count = s5p_mfc_get_mv_count_v5, 1726 .get_inst_no = s5p_mfc_get_inst_no_v5, 1727 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5, 1728 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5, 1729 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5, 1730 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v5, 1731 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v5, 1732 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v5, 1733 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v5, 1734 .get_pic_type_top = s5p_mfc_get_pic_type_top_v5, 1735 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5, 1736 .get_crop_info_h = s5p_mfc_get_crop_info_h_v5, 1737 .get_crop_info_v = s5p_mfc_get_crop_info_v_v5, 1738}; 1739 1740struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void) 1741{ 1742 return &s5p_mfc_ops_v5; 1743} 1744