s5p_mfc_opr_v5.h revision 77a788fc2d4089c64eb355a004f1f16b22eb3ab1
1/* 2 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr.h 3 * 4 * Header file for Samsung MFC (Multi Function Codec - FIMV) driver 5 * Contains declarations of hw related functions. 6 * 7 * Kamil Debski, Copyright (C) 2011 Samsung Electronics 8 * http://www.samsung.com/ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#ifndef S5P_MFC_OPR_H_ 16#define S5P_MFC_OPR_H_ 17 18#include "s5p_mfc_common.h" 19 20enum MFC_SHM_OFS { 21 EXTENEDED_DECODE_STATUS = 0x00, /* D */ 22 SET_FRAME_TAG = 0x04, /* D */ 23 GET_FRAME_TAG_TOP = 0x08, /* D */ 24 GET_FRAME_TAG_BOT = 0x0C, /* D */ 25 PIC_TIME_TOP = 0x10, /* D */ 26 PIC_TIME_BOT = 0x14, /* D */ 27 START_BYTE_NUM = 0x18, /* D */ 28 29 CROP_INFO_H = 0x20, /* D */ 30 CROP_INFO_V = 0x24, /* D */ 31 EXT_ENC_CONTROL = 0x28, /* E */ 32 ENC_PARAM_CHANGE = 0x2C, /* E */ 33 RC_VOP_TIMING = 0x30, /* E, MPEG4 */ 34 HEC_PERIOD = 0x34, /* E, MPEG4 */ 35 METADATA_ENABLE = 0x38, /* C */ 36 METADATA_STATUS = 0x3C, /* C */ 37 METADATA_DISPLAY_INDEX = 0x40, /* C */ 38 EXT_METADATA_START_ADDR = 0x44, /* C */ 39 PUT_EXTRADATA = 0x48, /* C */ 40 EXTRADATA_ADDR = 0x4C, /* C */ 41 42 ALLOC_LUMA_DPB_SIZE = 0x64, /* D */ 43 ALLOC_CHROMA_DPB_SIZE = 0x68, /* D */ 44 ALLOC_MV_SIZE = 0x6C, /* D */ 45 P_B_FRAME_QP = 0x70, /* E */ 46 SAMPLE_ASPECT_RATIO_IDC = 0x74, /* E, H.264, depend on 47 ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */ 48 EXTENDED_SAR = 0x78, /* E, H.264, depned on 49 ASPECT_RATIO_VUI_ENABLE in EXT_ENC_CONTROL */ 50 DISP_PIC_PROFILE = 0x7C, /* D */ 51 FLUSH_CMD_TYPE = 0x80, /* C */ 52 FLUSH_CMD_INBUF1 = 0x84, /* C */ 53 FLUSH_CMD_INBUF2 = 0x88, /* C */ 54 FLUSH_CMD_OUTBUF = 0x8C, /* E */ 55 NEW_RC_BIT_RATE = 0x90, /* E, format as RC_BIT_RATE(0xC5A8) 56 depend on RC_BIT_RATE_CHANGE in ENC_PARAM_CHANGE */ 57 NEW_RC_FRAME_RATE = 0x94, /* E, format as RC_FRAME_RATE(0xD0D0) 58 depend on RC_FRAME_RATE_CHANGE in ENC_PARAM_CHANGE */ 59 NEW_I_PERIOD = 0x98, /* E, format as I_FRM_CTRL(0xC504) 60 depend on I_PERIOD_CHANGE in ENC_PARAM_CHANGE */ 61 H264_I_PERIOD = 0x9C, /* E, H.264, open GOP */ 62 RC_CONTROL_CONFIG = 0xA0, /* E */ 63 BATCH_INPUT_ADDR = 0xA4, /* E */ 64 BATCH_OUTPUT_ADDR = 0xA8, /* E */ 65 BATCH_OUTPUT_SIZE = 0xAC, /* E */ 66 MIN_LUMA_DPB_SIZE = 0xB0, /* D */ 67 DEVICE_FORMAT_ID = 0xB4, /* C */ 68 H264_POC_TYPE = 0xB8, /* D */ 69 MIN_CHROMA_DPB_SIZE = 0xBC, /* D */ 70 DISP_PIC_FRAME_TYPE = 0xC0, /* D */ 71 FREE_LUMA_DPB = 0xC4, /* D, VC1 MPEG4 */ 72 ASPECT_RATIO_INFO = 0xC8, /* D, MPEG4 */ 73 EXTENDED_PAR = 0xCC, /* D, MPEG4 */ 74 DBG_HISTORY_INPUT0 = 0xD0, /* C */ 75 DBG_HISTORY_INPUT1 = 0xD4, /* C */ 76 DBG_HISTORY_OUTPUT = 0xD8, /* C */ 77 HIERARCHICAL_P_QP = 0xE0, /* E, H.264 */ 78 FRAME_PACK_SEI_ENABLE = 0x168, /* C */ 79 FRAME_PACK_SEI_AVAIL = 0x16c, /* D */ 80 FRAME_PACK_SEI_INFO = 0x17c, /* E */ 81}; 82 83int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx); 84int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx); 85 86/* Decoding functions */ 87int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx); 88int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr, 89 unsigned int start_num_byte, 90 unsigned int buf_size); 91 92/* Encoding functions */ 93void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx, 94 unsigned long y_addr, unsigned long c_addr); 95int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx, 96 unsigned long addr, unsigned int size); 97void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx, 98 unsigned long *y_addr, unsigned long *c_addr); 99int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *mfc_ctx); 100 101int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx, 102 enum s5p_mfc_decode_arg last_frame); 103int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *mfc_ctx); 104 105/* Memory allocation */ 106int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx); 107void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx); 108void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx); 109 110int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx); 111void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx); 112 113int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx); 114void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx); 115 116void s5p_mfc_try_run(struct s5p_mfc_dev *dev); 117void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); 118 119/* Shared memory ops */ 120void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, 121 unsigned int ofs); 122 123unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, 124 unsigned int ofs); 125 126#define s5p_mfc_get_dspl_y_adr() (readl(dev->regs_base + \ 127 S5P_FIMV_SI_DISPLAY_Y_ADR) << \ 128 MFC_OFFSET_SHIFT) 129#define s5p_mfc_get_dec_y_adr() (readl(dev->regs_base + \ 130 S5P_FIMV_SI_DECODE_Y_ADR) << \ 131 MFC_OFFSET_SHIFT) 132#define s5p_mfc_get_dspl_status() readl(dev->regs_base + \ 133 S5P_FIMV_SI_DISPLAY_STATUS) 134#define s5p_mfc_get_dec_status() readl(dev->regs_base + \ 135 S5P_FIMV_SI_DECODE_STATUS) 136#define s5p_mfc_get_frame_type() (readl(dev->regs_base + \ 137 S5P_FIMV_DECODE_FRAME_TYPE) \ 138 & S5P_FIMV_DECODE_FRAME_MASK) 139#define s5p_mfc_get_consumed_stream() readl(dev->regs_base + \ 140 S5P_FIMV_SI_CONSUMED_BYTES) 141#define s5p_mfc_get_int_reason() (readl(dev->regs_base + \ 142 S5P_FIMV_RISC2HOST_CMD) & \ 143 S5P_FIMV_RISC2HOST_CMD_MASK) 144#define s5p_mfc_get_int_err() readl(dev->regs_base + \ 145 S5P_FIMV_RISC2HOST_ARG2) 146#define s5p_mfc_err_dec(x) (((x) & S5P_FIMV_ERR_DEC_MASK) >> \ 147 S5P_FIMV_ERR_DEC_SHIFT) 148#define s5p_mfc_err_dspl(x) (((x) & S5P_FIMV_ERR_DSPL_MASK) >> \ 149 S5P_FIMV_ERR_DSPL_SHIFT) 150#define s5p_mfc_get_img_width() readl(dev->regs_base + \ 151 S5P_FIMV_SI_HRESOL) 152#define s5p_mfc_get_img_height() readl(dev->regs_base + \ 153 S5P_FIMV_SI_VRESOL) 154#define s5p_mfc_get_dpb_count() readl(dev->regs_base + \ 155 S5P_FIMV_SI_BUF_NUMBER) 156#define s5p_mfc_get_inst_no() readl(dev->regs_base + \ 157 S5P_FIMV_RISC2HOST_ARG1) 158#define s5p_mfc_get_enc_strm_size() readl(dev->regs_base + \ 159 S5P_FIMV_ENC_SI_STRM_SIZE) 160#define s5p_mfc_get_enc_slice_type() readl(dev->regs_base + \ 161 S5P_FIMV_ENC_SI_SLICE_TYPE) 162 163#endif /* S5P_MFC_OPR_H_ */ 164