1/* 2 * Elonics E4000 silicon tuner driver 3 * 4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21#include "e4000_priv.h" 22#include <linux/math64.h> 23 24static int e4000_init(struct dvb_frontend *fe) 25{ 26 struct e4000 *s = fe->tuner_priv; 27 int ret; 28 29 dev_dbg(&s->client->dev, "\n"); 30 31 /* dummy I2C to ensure I2C wakes up */ 32 ret = regmap_write(s->regmap, 0x02, 0x40); 33 34 /* reset */ 35 ret = regmap_write(s->regmap, 0x00, 0x01); 36 if (ret) 37 goto err; 38 39 /* disable output clock */ 40 ret = regmap_write(s->regmap, 0x06, 0x00); 41 if (ret) 42 goto err; 43 44 ret = regmap_write(s->regmap, 0x7a, 0x96); 45 if (ret) 46 goto err; 47 48 /* configure gains */ 49 ret = regmap_bulk_write(s->regmap, 0x7e, "\x01\xfe", 2); 50 if (ret) 51 goto err; 52 53 ret = regmap_write(s->regmap, 0x82, 0x00); 54 if (ret) 55 goto err; 56 57 ret = regmap_write(s->regmap, 0x24, 0x05); 58 if (ret) 59 goto err; 60 61 ret = regmap_bulk_write(s->regmap, 0x87, "\x20\x01", 2); 62 if (ret) 63 goto err; 64 65 ret = regmap_bulk_write(s->regmap, 0x9f, "\x7f\x07", 2); 66 if (ret) 67 goto err; 68 69 /* DC offset control */ 70 ret = regmap_write(s->regmap, 0x2d, 0x1f); 71 if (ret) 72 goto err; 73 74 ret = regmap_bulk_write(s->regmap, 0x70, "\x01\x01", 2); 75 if (ret) 76 goto err; 77 78 /* gain control */ 79 ret = regmap_write(s->regmap, 0x1a, 0x17); 80 if (ret) 81 goto err; 82 83 ret = regmap_write(s->regmap, 0x1f, 0x1a); 84 if (ret) 85 goto err; 86 87 s->active = true; 88err: 89 if (ret) 90 dev_dbg(&s->client->dev, "failed=%d\n", ret); 91 92 return ret; 93} 94 95static int e4000_sleep(struct dvb_frontend *fe) 96{ 97 struct e4000 *s = fe->tuner_priv; 98 int ret; 99 100 dev_dbg(&s->client->dev, "\n"); 101 102 s->active = false; 103 104 ret = regmap_write(s->regmap, 0x00, 0x00); 105 if (ret) 106 goto err; 107err: 108 if (ret) 109 dev_dbg(&s->client->dev, "failed=%d\n", ret); 110 111 return ret; 112} 113 114static int e4000_set_params(struct dvb_frontend *fe) 115{ 116 struct e4000 *s = fe->tuner_priv; 117 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 118 int ret, i, sigma_delta; 119 unsigned int pll_n, pll_f; 120 u64 f_vco; 121 u8 buf[5], i_data[4], q_data[4]; 122 123 dev_dbg(&s->client->dev, 124 "delivery_system=%d frequency=%u bandwidth_hz=%u\n", 125 c->delivery_system, c->frequency, c->bandwidth_hz); 126 127 /* gain control manual */ 128 ret = regmap_write(s->regmap, 0x1a, 0x00); 129 if (ret) 130 goto err; 131 132 /* PLL */ 133 for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) { 134 if (c->frequency <= e4000_pll_lut[i].freq) 135 break; 136 } 137 138 if (i == ARRAY_SIZE(e4000_pll_lut)) { 139 ret = -EINVAL; 140 goto err; 141 } 142 143 f_vco = 1ull * c->frequency * e4000_pll_lut[i].mul; 144 pll_n = div_u64_rem(f_vco, s->clock, &pll_f); 145 sigma_delta = div_u64(0x10000ULL * pll_f, s->clock); 146 buf[0] = pll_n; 147 buf[1] = (sigma_delta >> 0) & 0xff; 148 buf[2] = (sigma_delta >> 8) & 0xff; 149 buf[3] = 0x00; 150 buf[4] = e4000_pll_lut[i].div; 151 152 dev_dbg(&s->client->dev, "f_vco=%llu pll div=%d sigma_delta=%04x\n", 153 f_vco, buf[0], sigma_delta); 154 155 ret = regmap_bulk_write(s->regmap, 0x09, buf, 5); 156 if (ret) 157 goto err; 158 159 /* LNA filter (RF filter) */ 160 for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) { 161 if (c->frequency <= e400_lna_filter_lut[i].freq) 162 break; 163 } 164 165 if (i == ARRAY_SIZE(e400_lna_filter_lut)) { 166 ret = -EINVAL; 167 goto err; 168 } 169 170 ret = regmap_write(s->regmap, 0x10, e400_lna_filter_lut[i].val); 171 if (ret) 172 goto err; 173 174 /* IF filters */ 175 for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) { 176 if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq) 177 break; 178 } 179 180 if (i == ARRAY_SIZE(e4000_if_filter_lut)) { 181 ret = -EINVAL; 182 goto err; 183 } 184 185 buf[0] = e4000_if_filter_lut[i].reg11_val; 186 buf[1] = e4000_if_filter_lut[i].reg12_val; 187 188 ret = regmap_bulk_write(s->regmap, 0x11, buf, 2); 189 if (ret) 190 goto err; 191 192 /* frequency band */ 193 for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) { 194 if (c->frequency <= e4000_band_lut[i].freq) 195 break; 196 } 197 198 if (i == ARRAY_SIZE(e4000_band_lut)) { 199 ret = -EINVAL; 200 goto err; 201 } 202 203 ret = regmap_write(s->regmap, 0x07, e4000_band_lut[i].reg07_val); 204 if (ret) 205 goto err; 206 207 ret = regmap_write(s->regmap, 0x78, e4000_band_lut[i].reg78_val); 208 if (ret) 209 goto err; 210 211 /* DC offset */ 212 for (i = 0; i < 4; i++) { 213 if (i == 0) 214 ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7e\x24", 3); 215 else if (i == 1) 216 ret = regmap_bulk_write(s->regmap, 0x15, "\x00\x7f", 2); 217 else if (i == 2) 218 ret = regmap_bulk_write(s->regmap, 0x15, "\x01", 1); 219 else 220 ret = regmap_bulk_write(s->regmap, 0x16, "\x7e", 1); 221 222 if (ret) 223 goto err; 224 225 ret = regmap_write(s->regmap, 0x29, 0x01); 226 if (ret) 227 goto err; 228 229 ret = regmap_bulk_read(s->regmap, 0x2a, buf, 3); 230 if (ret) 231 goto err; 232 233 i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f); 234 q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f); 235 } 236 237 swap(q_data[2], q_data[3]); 238 swap(i_data[2], i_data[3]); 239 240 ret = regmap_bulk_write(s->regmap, 0x50, q_data, 4); 241 if (ret) 242 goto err; 243 244 ret = regmap_bulk_write(s->regmap, 0x60, i_data, 4); 245 if (ret) 246 goto err; 247 248 /* gain control auto */ 249 ret = regmap_write(s->regmap, 0x1a, 0x17); 250 if (ret) 251 goto err; 252err: 253 if (ret) 254 dev_dbg(&s->client->dev, "failed=%d\n", ret); 255 256 return ret; 257} 258 259static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 260{ 261 struct e4000 *s = fe->tuner_priv; 262 263 dev_dbg(&s->client->dev, "\n"); 264 265 *frequency = 0; /* Zero-IF */ 266 267 return 0; 268} 269 270#if IS_ENABLED(CONFIG_VIDEO_V4L2) 271static int e4000_set_lna_gain(struct dvb_frontend *fe) 272{ 273 struct e4000 *s = fe->tuner_priv; 274 int ret; 275 u8 u8tmp; 276 277 dev_dbg(&s->client->dev, "lna auto=%d->%d val=%d->%d\n", 278 s->lna_gain_auto->cur.val, s->lna_gain_auto->val, 279 s->lna_gain->cur.val, s->lna_gain->val); 280 281 if (s->lna_gain_auto->val && s->if_gain_auto->cur.val) 282 u8tmp = 0x17; 283 else if (s->lna_gain_auto->val) 284 u8tmp = 0x19; 285 else if (s->if_gain_auto->cur.val) 286 u8tmp = 0x16; 287 else 288 u8tmp = 0x10; 289 290 ret = regmap_write(s->regmap, 0x1a, u8tmp); 291 if (ret) 292 goto err; 293 294 if (s->lna_gain_auto->val == false) { 295 ret = regmap_write(s->regmap, 0x14, s->lna_gain->val); 296 if (ret) 297 goto err; 298 } 299err: 300 if (ret) 301 dev_dbg(&s->client->dev, "failed=%d\n", ret); 302 303 return ret; 304} 305 306static int e4000_set_mixer_gain(struct dvb_frontend *fe) 307{ 308 struct e4000 *s = fe->tuner_priv; 309 int ret; 310 u8 u8tmp; 311 312 dev_dbg(&s->client->dev, "mixer auto=%d->%d val=%d->%d\n", 313 s->mixer_gain_auto->cur.val, s->mixer_gain_auto->val, 314 s->mixer_gain->cur.val, s->mixer_gain->val); 315 316 if (s->mixer_gain_auto->val) 317 u8tmp = 0x15; 318 else 319 u8tmp = 0x14; 320 321 ret = regmap_write(s->regmap, 0x20, u8tmp); 322 if (ret) 323 goto err; 324 325 if (s->mixer_gain_auto->val == false) { 326 ret = regmap_write(s->regmap, 0x15, s->mixer_gain->val); 327 if (ret) 328 goto err; 329 } 330err: 331 if (ret) 332 dev_dbg(&s->client->dev, "failed=%d\n", ret); 333 334 return ret; 335} 336 337static int e4000_set_if_gain(struct dvb_frontend *fe) 338{ 339 struct e4000 *s = fe->tuner_priv; 340 int ret; 341 u8 buf[2]; 342 u8 u8tmp; 343 344 dev_dbg(&s->client->dev, "if auto=%d->%d val=%d->%d\n", 345 s->if_gain_auto->cur.val, s->if_gain_auto->val, 346 s->if_gain->cur.val, s->if_gain->val); 347 348 if (s->if_gain_auto->val && s->lna_gain_auto->cur.val) 349 u8tmp = 0x17; 350 else if (s->lna_gain_auto->cur.val) 351 u8tmp = 0x19; 352 else if (s->if_gain_auto->val) 353 u8tmp = 0x16; 354 else 355 u8tmp = 0x10; 356 357 ret = regmap_write(s->regmap, 0x1a, u8tmp); 358 if (ret) 359 goto err; 360 361 if (s->if_gain_auto->val == false) { 362 buf[0] = e4000_if_gain_lut[s->if_gain->val].reg16_val; 363 buf[1] = e4000_if_gain_lut[s->if_gain->val].reg17_val; 364 ret = regmap_bulk_write(s->regmap, 0x16, buf, 2); 365 if (ret) 366 goto err; 367 } 368err: 369 if (ret) 370 dev_dbg(&s->client->dev, "failed=%d\n", ret); 371 372 return ret; 373} 374 375static int e4000_pll_lock(struct dvb_frontend *fe) 376{ 377 struct e4000 *s = fe->tuner_priv; 378 int ret; 379 unsigned int utmp; 380 381 ret = regmap_read(s->regmap, 0x07, &utmp); 382 if (ret) 383 goto err; 384 385 s->pll_lock->val = (utmp & 0x01); 386err: 387 if (ret) 388 dev_dbg(&s->client->dev, "failed=%d\n", ret); 389 390 return ret; 391} 392 393static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 394{ 395 struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); 396 int ret; 397 398 if (!s->active) 399 return 0; 400 401 switch (ctrl->id) { 402 case V4L2_CID_RF_TUNER_PLL_LOCK: 403 ret = e4000_pll_lock(s->fe); 404 break; 405 default: 406 dev_dbg(&s->client->dev, "unknown ctrl: id=%d name=%s\n", 407 ctrl->id, ctrl->name); 408 ret = -EINVAL; 409 } 410 411 return ret; 412} 413 414static int e4000_s_ctrl(struct v4l2_ctrl *ctrl) 415{ 416 struct e4000 *s = container_of(ctrl->handler, struct e4000, hdl); 417 struct dvb_frontend *fe = s->fe; 418 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 419 int ret; 420 421 if (!s->active) 422 return 0; 423 424 switch (ctrl->id) { 425 case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO: 426 case V4L2_CID_RF_TUNER_BANDWIDTH: 427 c->bandwidth_hz = s->bandwidth->val; 428 ret = e4000_set_params(s->fe); 429 break; 430 case V4L2_CID_RF_TUNER_LNA_GAIN_AUTO: 431 case V4L2_CID_RF_TUNER_LNA_GAIN: 432 ret = e4000_set_lna_gain(s->fe); 433 break; 434 case V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO: 435 case V4L2_CID_RF_TUNER_MIXER_GAIN: 436 ret = e4000_set_mixer_gain(s->fe); 437 break; 438 case V4L2_CID_RF_TUNER_IF_GAIN_AUTO: 439 case V4L2_CID_RF_TUNER_IF_GAIN: 440 ret = e4000_set_if_gain(s->fe); 441 break; 442 default: 443 dev_dbg(&s->client->dev, "unknown ctrl: id=%d name=%s\n", 444 ctrl->id, ctrl->name); 445 ret = -EINVAL; 446 } 447 448 return ret; 449} 450 451static const struct v4l2_ctrl_ops e4000_ctrl_ops = { 452 .g_volatile_ctrl = e4000_g_volatile_ctrl, 453 .s_ctrl = e4000_s_ctrl, 454}; 455#endif 456 457static const struct dvb_tuner_ops e4000_tuner_ops = { 458 .info = { 459 .name = "Elonics E4000", 460 .frequency_min = 174000000, 461 .frequency_max = 862000000, 462 }, 463 464 .init = e4000_init, 465 .sleep = e4000_sleep, 466 .set_params = e4000_set_params, 467 468 .get_if_frequency = e4000_get_if_frequency, 469}; 470 471/* 472 * Use V4L2 subdev to carry V4L2 control handler, even we don't implement 473 * subdev itself, just to avoid reinventing the wheel. 474 */ 475static int e4000_probe(struct i2c_client *client, 476 const struct i2c_device_id *id) 477{ 478 struct e4000_config *cfg = client->dev.platform_data; 479 struct dvb_frontend *fe = cfg->fe; 480 struct e4000 *s; 481 int ret; 482 unsigned int utmp; 483 static const struct regmap_config regmap_config = { 484 .reg_bits = 8, 485 .val_bits = 8, 486 .max_register = 0xff, 487 }; 488 489 s = kzalloc(sizeof(struct e4000), GFP_KERNEL); 490 if (!s) { 491 ret = -ENOMEM; 492 dev_err(&client->dev, "kzalloc() failed\n"); 493 goto err; 494 } 495 496 s->clock = cfg->clock; 497 s->client = client; 498 s->fe = cfg->fe; 499 s->regmap = devm_regmap_init_i2c(client, ®map_config); 500 if (IS_ERR(s->regmap)) { 501 ret = PTR_ERR(s->regmap); 502 goto err; 503 } 504 505 /* check if the tuner is there */ 506 ret = regmap_read(s->regmap, 0x02, &utmp); 507 if (ret) 508 goto err; 509 510 dev_dbg(&s->client->dev, "chip id=%02x\n", utmp); 511 512 if (utmp != 0x40) { 513 ret = -ENODEV; 514 goto err; 515 } 516 517 /* put sleep as chip seems to be in normal mode by default */ 518 ret = regmap_write(s->regmap, 0x00, 0x00); 519 if (ret) 520 goto err; 521 522#if IS_ENABLED(CONFIG_VIDEO_V4L2) 523 /* Register controls */ 524 v4l2_ctrl_handler_init(&s->hdl, 9); 525 s->bandwidth_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 526 V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1); 527 s->bandwidth = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 528 V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000); 529 v4l2_ctrl_auto_cluster(2, &s->bandwidth_auto, 0, false); 530 s->lna_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 531 V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1); 532 s->lna_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 533 V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10); 534 v4l2_ctrl_auto_cluster(2, &s->lna_gain_auto, 0, false); 535 s->mixer_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 536 V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1); 537 s->mixer_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 538 V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1); 539 v4l2_ctrl_auto_cluster(2, &s->mixer_gain_auto, 0, false); 540 s->if_gain_auto = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 541 V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1); 542 s->if_gain = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 543 V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0); 544 v4l2_ctrl_auto_cluster(2, &s->if_gain_auto, 0, false); 545 s->pll_lock = v4l2_ctrl_new_std(&s->hdl, &e4000_ctrl_ops, 546 V4L2_CID_RF_TUNER_PLL_LOCK, 0, 1, 1, 0); 547 if (s->hdl.error) { 548 ret = s->hdl.error; 549 dev_err(&s->client->dev, "Could not initialize controls\n"); 550 v4l2_ctrl_handler_free(&s->hdl); 551 goto err; 552 } 553 554 s->sd.ctrl_handler = &s->hdl; 555#endif 556 557 dev_info(&s->client->dev, "Elonics E4000 successfully identified\n"); 558 559 fe->tuner_priv = s; 560 memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops, 561 sizeof(struct dvb_tuner_ops)); 562 563 v4l2_set_subdevdata(&s->sd, client); 564 i2c_set_clientdata(client, &s->sd); 565 566 return 0; 567err: 568 if (ret) { 569 dev_dbg(&client->dev, "failed=%d\n", ret); 570 kfree(s); 571 } 572 573 return ret; 574} 575 576static int e4000_remove(struct i2c_client *client) 577{ 578 struct v4l2_subdev *sd = i2c_get_clientdata(client); 579 struct e4000 *s = container_of(sd, struct e4000, sd); 580 struct dvb_frontend *fe = s->fe; 581 582 dev_dbg(&client->dev, "\n"); 583 584#if IS_ENABLED(CONFIG_VIDEO_V4L2) 585 v4l2_ctrl_handler_free(&s->hdl); 586#endif 587 memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops)); 588 fe->tuner_priv = NULL; 589 kfree(s); 590 591 return 0; 592} 593 594static const struct i2c_device_id e4000_id[] = { 595 {"e4000", 0}, 596 {} 597}; 598MODULE_DEVICE_TABLE(i2c, e4000_id); 599 600static struct i2c_driver e4000_driver = { 601 .driver = { 602 .owner = THIS_MODULE, 603 .name = "e4000", 604 }, 605 .probe = e4000_probe, 606 .remove = e4000_remove, 607 .id_table = e4000_id, 608}; 609 610module_i2c_driver(e4000_driver); 611 612MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver"); 613MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); 614MODULE_LICENSE("GPL"); 615