1/*
2 *  mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
3 *
4 *  Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
5 *
6 *  This program is free software; you can redistribute it and/or modify
7 *  it under the terms of the GNU General Public License as published by
8 *  the Free Software Foundation; either version 2 of the License, or
9 *  (at your option) any later version.
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *  GNU General Public License for more details.
15 *
16 *  You should have received a copy of the GNU General Public License
17 *  along with this program; if not, write to the Free Software
18 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/i2c.h>
22#include <linux/types.h>
23#include <linux/videodev2.h>
24#include "tuner-i2c.h"
25#include "mxl5007t.h"
26
27static DEFINE_MUTEX(mxl5007t_list_mutex);
28static LIST_HEAD(hybrid_tuner_instance_list);
29
30static int mxl5007t_debug;
31module_param_named(debug, mxl5007t_debug, int, 0644);
32MODULE_PARM_DESC(debug, "set debug level");
33
34/* ------------------------------------------------------------------------- */
35
36#define mxl_printk(kern, fmt, arg...) \
37	printk(kern "%s: " fmt "\n", __func__, ##arg)
38
39#define mxl_err(fmt, arg...) \
40	mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
41
42#define mxl_warn(fmt, arg...) \
43	mxl_printk(KERN_WARNING, fmt, ##arg)
44
45#define mxl_info(fmt, arg...) \
46	mxl_printk(KERN_INFO, fmt, ##arg)
47
48#define mxl_debug(fmt, arg...)				\
49({							\
50	if (mxl5007t_debug)				\
51		mxl_printk(KERN_DEBUG, fmt, ##arg);	\
52})
53
54#define mxl_fail(ret)							\
55({									\
56	int __ret;							\
57	__ret = (ret < 0);						\
58	if (__ret)							\
59		mxl_printk(KERN_ERR, "error %d on line %d",		\
60			   ret, __LINE__);				\
61	__ret;								\
62})
63
64/* ------------------------------------------------------------------------- */
65
66#define MHz 1000000
67
68enum mxl5007t_mode {
69	MxL_MODE_ISDBT     =    0,
70	MxL_MODE_DVBT      =    1,
71	MxL_MODE_ATSC      =    2,
72	MxL_MODE_CABLE     = 0x10,
73};
74
75enum mxl5007t_chip_version {
76	MxL_UNKNOWN_ID     = 0x00,
77	MxL_5007_V1_F1     = 0x11,
78	MxL_5007_V1_F2     = 0x12,
79	MxL_5007_V4        = 0x14,
80	MxL_5007_V2_100_F1 = 0x21,
81	MxL_5007_V2_100_F2 = 0x22,
82	MxL_5007_V2_200_F1 = 0x23,
83	MxL_5007_V2_200_F2 = 0x24,
84};
85
86struct reg_pair_t {
87	u8 reg;
88	u8 val;
89};
90
91/* ------------------------------------------------------------------------- */
92
93static struct reg_pair_t init_tab[] = {
94	{ 0x02, 0x06 },
95	{ 0x03, 0x48 },
96	{ 0x05, 0x04 },
97	{ 0x06, 0x10 },
98	{ 0x2e, 0x15 }, /* OVERRIDE */
99	{ 0x30, 0x10 }, /* OVERRIDE */
100	{ 0x45, 0x58 }, /* OVERRIDE */
101	{ 0x48, 0x19 }, /* OVERRIDE */
102	{ 0x52, 0x03 }, /* OVERRIDE */
103	{ 0x53, 0x44 }, /* OVERRIDE */
104	{ 0x6a, 0x4b }, /* OVERRIDE */
105	{ 0x76, 0x00 }, /* OVERRIDE */
106	{ 0x78, 0x18 }, /* OVERRIDE */
107	{ 0x7a, 0x17 }, /* OVERRIDE */
108	{ 0x85, 0x06 }, /* OVERRIDE */
109	{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
110	{ 0, 0 }
111};
112
113static struct reg_pair_t init_tab_cable[] = {
114	{ 0x02, 0x06 },
115	{ 0x03, 0x48 },
116	{ 0x05, 0x04 },
117	{ 0x06, 0x10 },
118	{ 0x09, 0x3f },
119	{ 0x0a, 0x3f },
120	{ 0x0b, 0x3f },
121	{ 0x2e, 0x15 }, /* OVERRIDE */
122	{ 0x30, 0x10 }, /* OVERRIDE */
123	{ 0x45, 0x58 }, /* OVERRIDE */
124	{ 0x48, 0x19 }, /* OVERRIDE */
125	{ 0x52, 0x03 }, /* OVERRIDE */
126	{ 0x53, 0x44 }, /* OVERRIDE */
127	{ 0x6a, 0x4b }, /* OVERRIDE */
128	{ 0x76, 0x00 }, /* OVERRIDE */
129	{ 0x78, 0x18 }, /* OVERRIDE */
130	{ 0x7a, 0x17 }, /* OVERRIDE */
131	{ 0x85, 0x06 }, /* OVERRIDE */
132	{ 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
133	{ 0, 0 }
134};
135
136/* ------------------------------------------------------------------------- */
137
138static struct reg_pair_t reg_pair_rftune[] = {
139	{ 0x0f, 0x00 }, /* abort tune */
140	{ 0x0c, 0x15 },
141	{ 0x0d, 0x40 },
142	{ 0x0e, 0x0e },
143	{ 0x1f, 0x87 }, /* OVERRIDE */
144	{ 0x20, 0x1f }, /* OVERRIDE */
145	{ 0x21, 0x87 }, /* OVERRIDE */
146	{ 0x22, 0x1f }, /* OVERRIDE */
147	{ 0x80, 0x01 }, /* freq dependent */
148	{ 0x0f, 0x01 }, /* start tune */
149	{ 0, 0 }
150};
151
152/* ------------------------------------------------------------------------- */
153
154struct mxl5007t_state {
155	struct list_head hybrid_tuner_instance_list;
156	struct tuner_i2c_props i2c_props;
157
158	struct mutex lock;
159
160	struct mxl5007t_config *config;
161
162	enum mxl5007t_chip_version chip_id;
163
164	struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
165	struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
166	struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
167
168	enum mxl5007t_if_freq if_freq;
169
170	u32 frequency;
171	u32 bandwidth;
172};
173
174/* ------------------------------------------------------------------------- */
175
176/* called by _init and _rftun to manipulate the register arrays */
177
178static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
179{
180	unsigned int i = 0;
181
182	while (reg_pair[i].reg || reg_pair[i].val) {
183		if (reg_pair[i].reg == reg) {
184			reg_pair[i].val &= ~mask;
185			reg_pair[i].val |= val;
186		}
187		i++;
188
189	}
190	return;
191}
192
193static void copy_reg_bits(struct reg_pair_t *reg_pair1,
194			  struct reg_pair_t *reg_pair2)
195{
196	unsigned int i, j;
197
198	i = j = 0;
199
200	while (reg_pair1[i].reg || reg_pair1[i].val) {
201		while (reg_pair2[j].reg || reg_pair2[j].val) {
202			if (reg_pair1[i].reg != reg_pair2[j].reg) {
203				j++;
204				continue;
205			}
206			reg_pair2[j].val = reg_pair1[i].val;
207			break;
208		}
209		i++;
210	}
211	return;
212}
213
214/* ------------------------------------------------------------------------- */
215
216static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
217				   enum mxl5007t_mode mode,
218				   s32 if_diff_out_level)
219{
220	switch (mode) {
221	case MxL_MODE_ATSC:
222		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
223		break;
224	case MxL_MODE_DVBT:
225		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
226		break;
227	case MxL_MODE_ISDBT:
228		set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
229		break;
230	case MxL_MODE_CABLE:
231		set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
232		set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
233			     8 - if_diff_out_level);
234		set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
235		break;
236	default:
237		mxl_fail(-EINVAL);
238	}
239	return;
240}
241
242static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
243				      enum mxl5007t_if_freq if_freq,
244				      int invert_if)
245{
246	u8 val;
247
248	switch (if_freq) {
249	case MxL_IF_4_MHZ:
250		val = 0x00;
251		break;
252	case MxL_IF_4_5_MHZ:
253		val = 0x02;
254		break;
255	case MxL_IF_4_57_MHZ:
256		val = 0x03;
257		break;
258	case MxL_IF_5_MHZ:
259		val = 0x04;
260		break;
261	case MxL_IF_5_38_MHZ:
262		val = 0x05;
263		break;
264	case MxL_IF_6_MHZ:
265		val = 0x06;
266		break;
267	case MxL_IF_6_28_MHZ:
268		val = 0x07;
269		break;
270	case MxL_IF_9_1915_MHZ:
271		val = 0x08;
272		break;
273	case MxL_IF_35_25_MHZ:
274		val = 0x09;
275		break;
276	case MxL_IF_36_15_MHZ:
277		val = 0x0a;
278		break;
279	case MxL_IF_44_MHZ:
280		val = 0x0b;
281		break;
282	default:
283		mxl_fail(-EINVAL);
284		return;
285	}
286	set_reg_bits(state->tab_init, 0x02, 0x0f, val);
287
288	/* set inverted IF or normal IF */
289	set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
290
291	state->if_freq = if_freq;
292
293	return;
294}
295
296static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
297					enum mxl5007t_xtal_freq xtal_freq)
298{
299	switch (xtal_freq) {
300	case MxL_XTAL_16_MHZ:
301		/* select xtal freq & ref freq */
302		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
303		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
304		break;
305	case MxL_XTAL_20_MHZ:
306		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
307		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
308		break;
309	case MxL_XTAL_20_25_MHZ:
310		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
311		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
312		break;
313	case MxL_XTAL_20_48_MHZ:
314		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
315		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
316		break;
317	case MxL_XTAL_24_MHZ:
318		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
319		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
320		break;
321	case MxL_XTAL_25_MHZ:
322		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
323		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
324		break;
325	case MxL_XTAL_25_14_MHZ:
326		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
327		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
328		break;
329	case MxL_XTAL_27_MHZ:
330		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
331		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
332		break;
333	case MxL_XTAL_28_8_MHZ:
334		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
335		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
336		break;
337	case MxL_XTAL_32_MHZ:
338		set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
339		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
340		break;
341	case MxL_XTAL_40_MHZ:
342		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
343		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
344		break;
345	case MxL_XTAL_44_MHZ:
346		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
347		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
348		break;
349	case MxL_XTAL_48_MHZ:
350		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
351		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
352		break;
353	case MxL_XTAL_49_3811_MHZ:
354		set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
355		set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
356		break;
357	default:
358		mxl_fail(-EINVAL);
359		return;
360	}
361
362	return;
363}
364
365static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
366						  enum mxl5007t_mode mode)
367{
368	struct mxl5007t_config *cfg = state->config;
369
370	memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
371	memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
372
373	mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
374	mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
375	mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
376
377	set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
378	set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
379	set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
380
381	if (mode >= MxL_MODE_CABLE) {
382		copy_reg_bits(state->tab_init, state->tab_init_cable);
383		return state->tab_init_cable;
384	} else
385		return state->tab_init;
386}
387
388/* ------------------------------------------------------------------------- */
389
390enum mxl5007t_bw_mhz {
391	MxL_BW_6MHz = 6,
392	MxL_BW_7MHz = 7,
393	MxL_BW_8MHz = 8,
394};
395
396static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
397				 enum mxl5007t_bw_mhz bw)
398{
399	u8 val;
400
401	switch (bw) {
402	case MxL_BW_6MHz:
403		val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
404			     * and DIG_MODEINDEX_CSF */
405		break;
406	case MxL_BW_7MHz:
407		val = 0x2a;
408		break;
409	case MxL_BW_8MHz:
410		val = 0x3f;
411		break;
412	default:
413		mxl_fail(-EINVAL);
414		return;
415	}
416	set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
417
418	return;
419}
420
421static struct
422reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
423				       u32 rf_freq, enum mxl5007t_bw_mhz bw)
424{
425	u32 dig_rf_freq = 0;
426	u32 temp;
427	u32 frac_divider = 1000000;
428	unsigned int i;
429
430	memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
431
432	mxl5007t_set_bw_bits(state, bw);
433
434	/* Convert RF frequency into 16 bits =>
435	 * 10 bit integer (MHz) + 6 bit fraction */
436	dig_rf_freq = rf_freq / MHz;
437
438	temp = rf_freq % MHz;
439
440	for (i = 0; i < 6; i++) {
441		dig_rf_freq <<= 1;
442		frac_divider /= 2;
443		if (temp > frac_divider) {
444			temp -= frac_divider;
445			dig_rf_freq++;
446		}
447	}
448
449	/* add to have shift center point by 7.8124 kHz */
450	if (temp > 7812)
451		dig_rf_freq++;
452
453	set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
454	set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
455
456	if (rf_freq >= 333000000)
457		set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
458
459	return state->tab_rftune;
460}
461
462/* ------------------------------------------------------------------------- */
463
464static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
465{
466	u8 buf[] = { reg, val };
467	struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
468			       .buf = buf, .len = 2 };
469	int ret;
470
471	ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
472	if (ret != 1) {
473		mxl_err("failed!");
474		return -EREMOTEIO;
475	}
476	return 0;
477}
478
479static int mxl5007t_write_regs(struct mxl5007t_state *state,
480			       struct reg_pair_t *reg_pair)
481{
482	unsigned int i = 0;
483	int ret = 0;
484
485	while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
486		ret = mxl5007t_write_reg(state,
487					 reg_pair[i].reg, reg_pair[i].val);
488		i++;
489	}
490	return ret;
491}
492
493static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
494{
495	u8 buf[2] = { 0xfb, reg };
496	struct i2c_msg msg[] = {
497		{ .addr = state->i2c_props.addr, .flags = 0,
498		  .buf = buf, .len = 2 },
499		{ .addr = state->i2c_props.addr, .flags = I2C_M_RD,
500		  .buf = val, .len = 1 },
501	};
502	int ret;
503
504	ret = i2c_transfer(state->i2c_props.adap, msg, 2);
505	if (ret != 2) {
506		mxl_err("failed!");
507		return -EREMOTEIO;
508	}
509	return 0;
510}
511
512static int mxl5007t_soft_reset(struct mxl5007t_state *state)
513{
514	u8 d = 0xff;
515	struct i2c_msg msg = {
516		.addr = state->i2c_props.addr, .flags = 0,
517		.buf = &d, .len = 1
518	};
519	int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
520
521	if (ret != 1) {
522		mxl_err("failed!");
523		return -EREMOTEIO;
524	}
525	return 0;
526}
527
528static int mxl5007t_tuner_init(struct mxl5007t_state *state,
529			       enum mxl5007t_mode mode)
530{
531	struct reg_pair_t *init_regs;
532	int ret;
533
534	ret = mxl5007t_soft_reset(state);
535	if (mxl_fail(ret))
536		goto fail;
537
538	/* calculate initialization reg array */
539	init_regs = mxl5007t_calc_init_regs(state, mode);
540
541	ret = mxl5007t_write_regs(state, init_regs);
542	if (mxl_fail(ret))
543		goto fail;
544	mdelay(1);
545fail:
546	return ret;
547}
548
549static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
550				  enum mxl5007t_bw_mhz bw)
551{
552	struct reg_pair_t *rf_tune_regs;
553	int ret;
554
555	/* calculate channel change reg array */
556	rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
557
558	ret = mxl5007t_write_regs(state, rf_tune_regs);
559	if (mxl_fail(ret))
560		goto fail;
561	msleep(3);
562fail:
563	return ret;
564}
565
566/* ------------------------------------------------------------------------- */
567
568static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
569				      int *rf_locked, int *ref_locked)
570{
571	u8 d;
572	int ret;
573
574	*rf_locked = 0;
575	*ref_locked = 0;
576
577	ret = mxl5007t_read_reg(state, 0xd8, &d);
578	if (mxl_fail(ret))
579		goto fail;
580
581	if ((d & 0x0c) == 0x0c)
582		*rf_locked = 1;
583
584	if ((d & 0x03) == 0x03)
585		*ref_locked = 1;
586fail:
587	return ret;
588}
589
590/* ------------------------------------------------------------------------- */
591
592static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
593{
594	struct mxl5007t_state *state = fe->tuner_priv;
595	int rf_locked, ref_locked, ret;
596
597	*status = 0;
598
599	if (fe->ops.i2c_gate_ctrl)
600		fe->ops.i2c_gate_ctrl(fe, 1);
601
602	ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
603	if (mxl_fail(ret))
604		goto fail;
605	mxl_debug("%s%s", rf_locked ? "rf locked " : "",
606		  ref_locked ? "ref locked" : "");
607
608	if ((rf_locked) || (ref_locked))
609		*status |= TUNER_STATUS_LOCKED;
610fail:
611	if (fe->ops.i2c_gate_ctrl)
612		fe->ops.i2c_gate_ctrl(fe, 0);
613
614	return ret;
615}
616
617/* ------------------------------------------------------------------------- */
618
619static int mxl5007t_set_params(struct dvb_frontend *fe)
620{
621	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
622	u32 delsys = c->delivery_system;
623	struct mxl5007t_state *state = fe->tuner_priv;
624	enum mxl5007t_bw_mhz bw;
625	enum mxl5007t_mode mode;
626	int ret;
627	u32 freq = c->frequency;
628
629	switch (delsys) {
630	case SYS_ATSC:
631		mode = MxL_MODE_ATSC;
632		bw = MxL_BW_6MHz;
633		break;
634	case SYS_DVBC_ANNEX_B:
635		mode = MxL_MODE_CABLE;
636		bw = MxL_BW_6MHz;
637		break;
638	case SYS_DVBT:
639	case SYS_DVBT2:
640		mode = MxL_MODE_DVBT;
641		switch (c->bandwidth_hz) {
642		case 6000000:
643			bw = MxL_BW_6MHz;
644			break;
645		case 7000000:
646			bw = MxL_BW_7MHz;
647			break;
648		case 8000000:
649			bw = MxL_BW_8MHz;
650			break;
651		default:
652			return -EINVAL;
653		}
654		break;
655	default:
656		mxl_err("modulation type not supported!");
657		return -EINVAL;
658	}
659
660	if (fe->ops.i2c_gate_ctrl)
661		fe->ops.i2c_gate_ctrl(fe, 1);
662
663	mutex_lock(&state->lock);
664
665	ret = mxl5007t_tuner_init(state, mode);
666	if (mxl_fail(ret))
667		goto fail;
668
669	ret = mxl5007t_tuner_rf_tune(state, freq, bw);
670	if (mxl_fail(ret))
671		goto fail;
672
673	state->frequency = freq;
674	state->bandwidth = c->bandwidth_hz;
675fail:
676	mutex_unlock(&state->lock);
677
678	if (fe->ops.i2c_gate_ctrl)
679		fe->ops.i2c_gate_ctrl(fe, 0);
680
681	return ret;
682}
683
684/* ------------------------------------------------------------------------- */
685
686static int mxl5007t_init(struct dvb_frontend *fe)
687{
688	struct mxl5007t_state *state = fe->tuner_priv;
689	int ret;
690
691	if (fe->ops.i2c_gate_ctrl)
692		fe->ops.i2c_gate_ctrl(fe, 1);
693
694	/* wake from standby */
695	ret = mxl5007t_write_reg(state, 0x01, 0x01);
696	mxl_fail(ret);
697
698	if (fe->ops.i2c_gate_ctrl)
699		fe->ops.i2c_gate_ctrl(fe, 0);
700
701	return ret;
702}
703
704static int mxl5007t_sleep(struct dvb_frontend *fe)
705{
706	struct mxl5007t_state *state = fe->tuner_priv;
707	int ret;
708
709	if (fe->ops.i2c_gate_ctrl)
710		fe->ops.i2c_gate_ctrl(fe, 1);
711
712	/* enter standby mode */
713	ret = mxl5007t_write_reg(state, 0x01, 0x00);
714	mxl_fail(ret);
715	ret = mxl5007t_write_reg(state, 0x0f, 0x00);
716	mxl_fail(ret);
717
718	if (fe->ops.i2c_gate_ctrl)
719		fe->ops.i2c_gate_ctrl(fe, 0);
720
721	return ret;
722}
723
724/* ------------------------------------------------------------------------- */
725
726static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
727{
728	struct mxl5007t_state *state = fe->tuner_priv;
729	*frequency = state->frequency;
730	return 0;
731}
732
733static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
734{
735	struct mxl5007t_state *state = fe->tuner_priv;
736	*bandwidth = state->bandwidth;
737	return 0;
738}
739
740static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
741{
742	struct mxl5007t_state *state = fe->tuner_priv;
743
744	*frequency = 0;
745
746	switch (state->if_freq) {
747	case MxL_IF_4_MHZ:
748		*frequency = 4000000;
749		break;
750	case MxL_IF_4_5_MHZ:
751		*frequency = 4500000;
752		break;
753	case MxL_IF_4_57_MHZ:
754		*frequency = 4570000;
755		break;
756	case MxL_IF_5_MHZ:
757		*frequency = 5000000;
758		break;
759	case MxL_IF_5_38_MHZ:
760		*frequency = 5380000;
761		break;
762	case MxL_IF_6_MHZ:
763		*frequency = 6000000;
764		break;
765	case MxL_IF_6_28_MHZ:
766		*frequency = 6280000;
767		break;
768	case MxL_IF_9_1915_MHZ:
769		*frequency = 9191500;
770		break;
771	case MxL_IF_35_25_MHZ:
772		*frequency = 35250000;
773		break;
774	case MxL_IF_36_15_MHZ:
775		*frequency = 36150000;
776		break;
777	case MxL_IF_44_MHZ:
778		*frequency = 44000000;
779		break;
780	}
781	return 0;
782}
783
784static int mxl5007t_release(struct dvb_frontend *fe)
785{
786	struct mxl5007t_state *state = fe->tuner_priv;
787
788	mutex_lock(&mxl5007t_list_mutex);
789
790	if (state)
791		hybrid_tuner_release_state(state);
792
793	mutex_unlock(&mxl5007t_list_mutex);
794
795	fe->tuner_priv = NULL;
796
797	return 0;
798}
799
800/* ------------------------------------------------------------------------- */
801
802static struct dvb_tuner_ops mxl5007t_tuner_ops = {
803	.info = {
804		.name = "MaxLinear MxL5007T",
805	},
806	.init              = mxl5007t_init,
807	.sleep             = mxl5007t_sleep,
808	.set_params        = mxl5007t_set_params,
809	.get_status        = mxl5007t_get_status,
810	.get_frequency     = mxl5007t_get_frequency,
811	.get_bandwidth     = mxl5007t_get_bandwidth,
812	.release           = mxl5007t_release,
813	.get_if_frequency  = mxl5007t_get_if_frequency,
814};
815
816static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
817{
818	char *name;
819	int ret;
820	u8 id;
821
822	ret = mxl5007t_read_reg(state, 0xd9, &id);
823	if (mxl_fail(ret))
824		goto fail;
825
826	switch (id) {
827	case MxL_5007_V1_F1:
828		name = "MxL5007.v1.f1";
829		break;
830	case MxL_5007_V1_F2:
831		name = "MxL5007.v1.f2";
832		break;
833	case MxL_5007_V2_100_F1:
834		name = "MxL5007.v2.100.f1";
835		break;
836	case MxL_5007_V2_100_F2:
837		name = "MxL5007.v2.100.f2";
838		break;
839	case MxL_5007_V2_200_F1:
840		name = "MxL5007.v2.200.f1";
841		break;
842	case MxL_5007_V2_200_F2:
843		name = "MxL5007.v2.200.f2";
844		break;
845	case MxL_5007_V4:
846		name = "MxL5007T.v4";
847		break;
848	default:
849		name = "MxL5007T";
850		printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
851		id = MxL_UNKNOWN_ID;
852	}
853	state->chip_id = id;
854	mxl_info("%s detected @ %d-%04x", name,
855		 i2c_adapter_id(state->i2c_props.adap),
856		 state->i2c_props.addr);
857	return 0;
858fail:
859	mxl_warn("unable to identify device @ %d-%04x",
860		 i2c_adapter_id(state->i2c_props.adap),
861		 state->i2c_props.addr);
862
863	state->chip_id = MxL_UNKNOWN_ID;
864	return ret;
865}
866
867struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
868				     struct i2c_adapter *i2c, u8 addr,
869				     struct mxl5007t_config *cfg)
870{
871	struct mxl5007t_state *state = NULL;
872	int instance, ret;
873
874	mutex_lock(&mxl5007t_list_mutex);
875	instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
876					      hybrid_tuner_instance_list,
877					      i2c, addr, "mxl5007t");
878	switch (instance) {
879	case 0:
880		goto fail;
881	case 1:
882		/* new tuner instance */
883		state->config = cfg;
884
885		mutex_init(&state->lock);
886
887		if (fe->ops.i2c_gate_ctrl)
888			fe->ops.i2c_gate_ctrl(fe, 1);
889
890		ret = mxl5007t_get_chip_id(state);
891
892		if (fe->ops.i2c_gate_ctrl)
893			fe->ops.i2c_gate_ctrl(fe, 0);
894
895		/* check return value of mxl5007t_get_chip_id */
896		if (mxl_fail(ret))
897			goto fail;
898		break;
899	default:
900		/* existing tuner instance */
901		break;
902	}
903	fe->tuner_priv = state;
904	mutex_unlock(&mxl5007t_list_mutex);
905
906	memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
907	       sizeof(struct dvb_tuner_ops));
908
909	return fe;
910fail:
911	mutex_unlock(&mxl5007t_list_mutex);
912
913	mxl5007t_release(fe);
914	return NULL;
915}
916EXPORT_SYMBOL_GPL(mxl5007t_attach);
917MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
918MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
919MODULE_LICENSE("GPL");
920MODULE_VERSION("0.2");
921
922/*
923 * Overrides for Emacs so that we follow Linus's tabbing style.
924 * ---------------------------------------------------------------------------
925 * Local variables:
926 * c-basic-offset: 8
927 * End:
928 */
929