1/* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25#include <linux/init.h> 26#include <linux/list.h> 27#include <linux/module.h> 28#include <linux/kernel.h> 29#include <linux/bitmap.h> 30#include <linux/usb.h> 31#include <linux/i2c.h> 32#include <linux/mm.h> 33#include <linux/mutex.h> 34#include <media/tuner.h> 35 36#include <media/v4l2-common.h> 37#include <media/v4l2-ioctl.h> 38 39#include "cx231xx.h" 40#include "cx231xx-dif.h" 41 42#define TUNER_MODE_FM_RADIO 0 43/****************************************************************************** 44 -: BLOCK ARRANGEMENT :- 45 I2S block ----------------------| 46 [I2S audio] | 47 | 48 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 49 [video & audio] | [Audio] 50 | 51 |-> Cx25840 --> Video 52 [Video] 53 54*******************************************************************************/ 55/****************************************************************************** 56 * VERVE REGISTER * 57 * * 58 ******************************************************************************/ 59static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 60{ 61 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 62 saddr, 1, data, 1); 63} 64 65static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 66{ 67 int status; 68 u32 temp = 0; 69 70 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 71 saddr, 1, &temp, 1); 72 *data = (u8) temp; 73 return status; 74} 75void initGPIO(struct cx231xx *dev) 76{ 77 u32 _gpio_direction = 0; 78 u32 value = 0; 79 u8 val = 0; 80 81 _gpio_direction = _gpio_direction & 0xFC0003FF; 82 _gpio_direction = _gpio_direction | 0x03FDFC00; 83 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 84 85 verve_read_byte(dev, 0x07, &val); 86 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 87 verve_write_byte(dev, 0x07, 0xF4); 88 verve_read_byte(dev, 0x07, &val); 89 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 90 91 cx231xx_capture_start(dev, 1, Vbi); 92 93 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 94 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 95 96} 97void uninitGPIO(struct cx231xx *dev) 98{ 99 u8 value[4] = { 0, 0, 0, 0 }; 100 101 cx231xx_capture_start(dev, 0, Vbi); 102 verve_write_byte(dev, 0x07, 0x14); 103 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 104 0x68, value, 4); 105} 106 107/****************************************************************************** 108 * A F E - B L O C K C O N T R O L functions * 109 * [ANALOG FRONT END] * 110 ******************************************************************************/ 111static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 112{ 113 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 114 saddr, 2, data, 1); 115} 116 117static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 118{ 119 int status; 120 u32 temp = 0; 121 122 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 123 saddr, 2, &temp, 1); 124 *data = (u8) temp; 125 return status; 126} 127 128int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 129{ 130 int status = 0; 131 u8 temp = 0; 132 u8 afe_power_status = 0; 133 int i = 0; 134 135 /* super block initialize */ 136 temp = (u8) (ref_count & 0xff); 137 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 138 if (status < 0) 139 return status; 140 141 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 142 if (status < 0) 143 return status; 144 145 temp = (u8) ((ref_count & 0x300) >> 8); 146 temp |= 0x40; 147 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 148 if (status < 0) 149 return status; 150 151 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 152 if (status < 0) 153 return status; 154 155 /* enable pll */ 156 while (afe_power_status != 0x18) { 157 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 158 if (status < 0) { 159 cx231xx_info( 160 ": Init Super Block failed in send cmd\n"); 161 break; 162 } 163 164 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 165 afe_power_status &= 0xff; 166 if (status < 0) { 167 cx231xx_info( 168 ": Init Super Block failed in receive cmd\n"); 169 break; 170 } 171 i++; 172 if (i == 10) { 173 cx231xx_info( 174 ": Init Super Block force break in loop !!!!\n"); 175 status = -1; 176 break; 177 } 178 } 179 180 if (status < 0) 181 return status; 182 183 /* start tuning filter */ 184 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 185 if (status < 0) 186 return status; 187 188 msleep(5); 189 190 /* exit tuning */ 191 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 192 193 return status; 194} 195 196int cx231xx_afe_init_channels(struct cx231xx *dev) 197{ 198 int status = 0; 199 200 /* power up all 3 channels, clear pd_buffer */ 201 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 204 205 /* Enable quantizer calibration */ 206 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 207 208 /* channel initialize, force modulator (fb) reset */ 209 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 212 213 /* start quantilizer calibration */ 214 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 217 msleep(5); 218 219 /* exit modulator (fb) reset */ 220 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 223 224 /* enable the pre_clamp in each channel for single-ended input */ 225 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 228 229 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 230 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 231 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 232 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 233 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 234 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 235 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 236 237 /* dynamic element matching off */ 238 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 241 242 return status; 243} 244 245int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 246{ 247 u8 c_value = 0; 248 int status = 0; 249 250 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 251 c_value &= (~(0x50)); 252 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 253 254 return status; 255} 256 257/* 258 The Analog Front End in Cx231xx has 3 channels. These 259 channels are used to share between different inputs 260 like tuner, s-video and composite inputs. 261 262 channel 1 ----- pin 1 to pin4(in reg is 1-4) 263 channel 2 ----- pin 5 to pin8(in reg is 5-8) 264 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 265*/ 266int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 267{ 268 u8 ch1_setting = (u8) input_mux; 269 u8 ch2_setting = (u8) (input_mux >> 8); 270 u8 ch3_setting = (u8) (input_mux >> 16); 271 int status = 0; 272 u8 value = 0; 273 274 if (ch1_setting != 0) { 275 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 276 value &= ~INPUT_SEL_MASK; 277 value |= (ch1_setting - 1) << 4; 278 value &= 0xff; 279 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 280 } 281 282 if (ch2_setting != 0) { 283 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 284 value &= ~INPUT_SEL_MASK; 285 value |= (ch2_setting - 1) << 4; 286 value &= 0xff; 287 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 288 } 289 290 /* For ch3_setting, the value to put in the register is 291 7 less than the input number */ 292 if (ch3_setting != 0) { 293 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 294 value &= ~INPUT_SEL_MASK; 295 value |= (ch3_setting - 1) << 4; 296 value &= 0xff; 297 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 298 } 299 300 return status; 301} 302 303int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 304{ 305 int status = 0; 306 307 /* 308 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 309 * Currently, only baseband works. 310 */ 311 312 switch (mode) { 313 case AFE_MODE_LOW_IF: 314 cx231xx_Setup_AFE_for_LowIF(dev); 315 break; 316 case AFE_MODE_BASEBAND: 317 status = cx231xx_afe_setup_AFE_for_baseband(dev); 318 break; 319 case AFE_MODE_EU_HI_IF: 320 /* SetupAFEforEuHiIF(); */ 321 break; 322 case AFE_MODE_US_HI_IF: 323 /* SetupAFEforUsHiIF(); */ 324 break; 325 case AFE_MODE_JAPAN_HI_IF: 326 /* SetupAFEforJapanHiIF(); */ 327 break; 328 } 329 330 if ((mode != dev->afe_mode) && 331 (dev->video_input == CX231XX_VMUX_TELEVISION)) 332 status = cx231xx_afe_adjust_ref_count(dev, 333 CX231XX_VMUX_TELEVISION); 334 335 dev->afe_mode = mode; 336 337 return status; 338} 339 340int cx231xx_afe_update_power_control(struct cx231xx *dev, 341 enum AV_MODE avmode) 342{ 343 u8 afe_power_status = 0; 344 int status = 0; 345 346 switch (dev->model) { 347 case CX231XX_BOARD_CNXT_CARRAERA: 348 case CX231XX_BOARD_CNXT_RDE_250: 349 case CX231XX_BOARD_CNXT_SHELBY: 350 case CX231XX_BOARD_CNXT_RDU_250: 351 case CX231XX_BOARD_CNXT_RDE_253S: 352 case CX231XX_BOARD_CNXT_RDU_253S: 353 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 354 case CX231XX_BOARD_HAUPPAUGE_EXETER: 355 case CX231XX_BOARD_HAUPPAUGE_930C_HD_1113xx: 356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 359 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 360 case CX231XX_BOARD_OTG102: 361 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 362 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 363 FLD_PWRDN_ENABLE_PLL)) { 364 status = afe_write_byte(dev, SUP_BLK_PWRDN, 365 FLD_PWRDN_TUNING_BIAS | 366 FLD_PWRDN_ENABLE_PLL); 367 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 368 &afe_power_status); 369 if (status < 0) 370 break; 371 } 372 373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 374 0x00); 375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 376 0x00); 377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 378 0x00); 379 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 380 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 381 0x70); 382 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 383 0x70); 384 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 385 0x70); 386 387 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 388 &afe_power_status); 389 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 390 FLD_PWRDN_PD_BIAS | 391 FLD_PWRDN_PD_TUNECK; 392 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 393 afe_power_status); 394 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 395 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 396 FLD_PWRDN_ENABLE_PLL)) { 397 status = afe_write_byte(dev, SUP_BLK_PWRDN, 398 FLD_PWRDN_TUNING_BIAS | 399 FLD_PWRDN_ENABLE_PLL); 400 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 401 &afe_power_status); 402 if (status < 0) 403 break; 404 } 405 406 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 407 0x00); 408 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 409 0x00); 410 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 411 0x00); 412 } else { 413 cx231xx_info("Invalid AV mode input\n"); 414 status = -1; 415 } 416 break; 417 default: 418 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 419 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 420 FLD_PWRDN_ENABLE_PLL)) { 421 status = afe_write_byte(dev, SUP_BLK_PWRDN, 422 FLD_PWRDN_TUNING_BIAS | 423 FLD_PWRDN_ENABLE_PLL); 424 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 425 &afe_power_status); 426 if (status < 0) 427 break; 428 } 429 430 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 431 0x40); 432 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 433 0x40); 434 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 435 0x00); 436 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 437 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 438 0x70); 439 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 440 0x70); 441 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 442 0x70); 443 444 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 445 &afe_power_status); 446 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 447 FLD_PWRDN_PD_BIAS | 448 FLD_PWRDN_PD_TUNECK; 449 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 450 afe_power_status); 451 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 452 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 453 FLD_PWRDN_ENABLE_PLL)) { 454 status = afe_write_byte(dev, SUP_BLK_PWRDN, 455 FLD_PWRDN_TUNING_BIAS | 456 FLD_PWRDN_ENABLE_PLL); 457 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 458 &afe_power_status); 459 if (status < 0) 460 break; 461 } 462 463 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 464 0x00); 465 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 466 0x00); 467 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 468 0x40); 469 } else { 470 cx231xx_info("Invalid AV mode input\n"); 471 status = -1; 472 } 473 } /* switch */ 474 475 return status; 476} 477 478int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 479{ 480 u8 input_mode = 0; 481 u8 ntf_mode = 0; 482 int status = 0; 483 484 dev->video_input = video_input; 485 486 if (video_input == CX231XX_VMUX_TELEVISION) { 487 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 488 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 489 &ntf_mode); 490 } else { 491 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 492 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 493 &ntf_mode); 494 } 495 496 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 497 498 switch (input_mode) { 499 case SINGLE_ENDED: 500 dev->afe_ref_count = 0x23C; 501 break; 502 case LOW_IF: 503 dev->afe_ref_count = 0x24C; 504 break; 505 case EU_IF: 506 dev->afe_ref_count = 0x258; 507 break; 508 case US_IF: 509 dev->afe_ref_count = 0x260; 510 break; 511 default: 512 break; 513 } 514 515 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 516 517 return status; 518} 519 520/****************************************************************************** 521 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 522 ******************************************************************************/ 523static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 524{ 525 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 526 saddr, 2, data, 1); 527} 528 529static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 530{ 531 int status; 532 u32 temp = 0; 533 534 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 535 saddr, 2, &temp, 1); 536 *data = (u8) temp; 537 return status; 538} 539 540static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 541{ 542 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 543 saddr, 2, data, 4); 544} 545 546static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 547{ 548 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 549 saddr, 2, data, 4); 550} 551int cx231xx_check_fw(struct cx231xx *dev) 552{ 553 u8 temp = 0; 554 int status = 0; 555 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 556 if (status < 0) 557 return status; 558 else 559 return temp; 560 561} 562 563int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 564{ 565 int status = 0; 566 567 switch (INPUT(input)->type) { 568 case CX231XX_VMUX_COMPOSITE1: 569 case CX231XX_VMUX_SVIDEO: 570 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 571 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 572 /* External AV */ 573 status = cx231xx_set_power_mode(dev, 574 POLARIS_AVMODE_ENXTERNAL_AV); 575 if (status < 0) { 576 cx231xx_errdev("%s: set_power_mode : Failed to" 577 " set Power - errCode [%d]!\n", 578 __func__, status); 579 return status; 580 } 581 } 582 status = cx231xx_set_decoder_video_input(dev, 583 INPUT(input)->type, 584 INPUT(input)->vmux); 585 break; 586 case CX231XX_VMUX_TELEVISION: 587 case CX231XX_VMUX_CABLE: 588 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 589 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 590 /* Tuner */ 591 status = cx231xx_set_power_mode(dev, 592 POLARIS_AVMODE_ANALOGT_TV); 593 if (status < 0) { 594 cx231xx_errdev("%s: set_power_mode:Failed" 595 " to set Power - errCode [%d]!\n", 596 __func__, status); 597 return status; 598 } 599 } 600 if (dev->tuner_type == TUNER_NXP_TDA18271) 601 status = cx231xx_set_decoder_video_input(dev, 602 CX231XX_VMUX_TELEVISION, 603 INPUT(input)->vmux); 604 else 605 status = cx231xx_set_decoder_video_input(dev, 606 CX231XX_VMUX_COMPOSITE1, 607 INPUT(input)->vmux); 608 609 break; 610 default: 611 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 612 __func__, INPUT(input)->type); 613 break; 614 } 615 616 /* save the selection */ 617 dev->video_input = input; 618 619 return status; 620} 621 622int cx231xx_set_decoder_video_input(struct cx231xx *dev, 623 u8 pin_type, u8 input) 624{ 625 int status = 0; 626 u32 value = 0; 627 628 if (pin_type != dev->video_input) { 629 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 630 if (status < 0) { 631 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 632 "AFE input mux - errCode [%d]!\n", 633 __func__, status); 634 return status; 635 } 636 } 637 638 /* call afe block to set video inputs */ 639 status = cx231xx_afe_set_input_mux(dev, input); 640 if (status < 0) { 641 cx231xx_errdev("%s: set_input_mux :Failed to set" 642 " AFE input mux - errCode [%d]!\n", 643 __func__, status); 644 return status; 645 } 646 647 switch (pin_type) { 648 case CX231XX_VMUX_COMPOSITE1: 649 status = vid_blk_read_word(dev, AFE_CTRL, &value); 650 value |= (0 << 13) | (1 << 4); 651 value &= ~(1 << 5); 652 653 /* set [24:23] [22:15] to 0 */ 654 value &= (~(0x1ff8000)); 655 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 656 value |= 0x1000000; 657 status = vid_blk_write_word(dev, AFE_CTRL, value); 658 659 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 660 value |= (1 << 7); 661 status = vid_blk_write_word(dev, OUT_CTRL1, value); 662 663 /* Set output mode */ 664 status = cx231xx_read_modify_write_i2c_dword(dev, 665 VID_BLK_I2C_ADDRESS, 666 OUT_CTRL1, 667 FLD_OUT_MODE, 668 dev->board.output_mode); 669 670 /* Tell DIF object to go to baseband mode */ 671 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 672 if (status < 0) { 673 cx231xx_errdev("%s: cx231xx_dif set to By pass" 674 " mode- errCode [%d]!\n", 675 __func__, status); 676 return status; 677 } 678 679 /* Read the DFE_CTRL1 register */ 680 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 681 682 /* enable the VBI_GATE_EN */ 683 value |= FLD_VBI_GATE_EN; 684 685 /* Enable the auto-VGA enable */ 686 value |= FLD_VGA_AUTO_EN; 687 688 /* Write it back */ 689 status = vid_blk_write_word(dev, DFE_CTRL1, value); 690 691 /* Disable auto config of registers */ 692 status = cx231xx_read_modify_write_i2c_dword(dev, 693 VID_BLK_I2C_ADDRESS, 694 MODE_CTRL, FLD_ACFG_DIS, 695 cx231xx_set_field(FLD_ACFG_DIS, 1)); 696 697 /* Set CVBS input mode */ 698 status = cx231xx_read_modify_write_i2c_dword(dev, 699 VID_BLK_I2C_ADDRESS, 700 MODE_CTRL, FLD_INPUT_MODE, 701 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 702 break; 703 case CX231XX_VMUX_SVIDEO: 704 /* Disable the use of DIF */ 705 706 status = vid_blk_read_word(dev, AFE_CTRL, &value); 707 708 /* set [24:23] [22:15] to 0 */ 709 value &= (~(0x1ff8000)); 710 /* set FUNC_MODE[24:23] = 2 711 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 712 value |= 0x1000010; 713 status = vid_blk_write_word(dev, AFE_CTRL, value); 714 715 /* Tell DIF object to go to baseband mode */ 716 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 717 if (status < 0) { 718 cx231xx_errdev("%s: cx231xx_dif set to By pass" 719 " mode- errCode [%d]!\n", 720 __func__, status); 721 return status; 722 } 723 724 /* Read the DFE_CTRL1 register */ 725 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 726 727 /* enable the VBI_GATE_EN */ 728 value |= FLD_VBI_GATE_EN; 729 730 /* Enable the auto-VGA enable */ 731 value |= FLD_VGA_AUTO_EN; 732 733 /* Write it back */ 734 status = vid_blk_write_word(dev, DFE_CTRL1, value); 735 736 /* Disable auto config of registers */ 737 status = cx231xx_read_modify_write_i2c_dword(dev, 738 VID_BLK_I2C_ADDRESS, 739 MODE_CTRL, FLD_ACFG_DIS, 740 cx231xx_set_field(FLD_ACFG_DIS, 1)); 741 742 /* Set YC input mode */ 743 status = cx231xx_read_modify_write_i2c_dword(dev, 744 VID_BLK_I2C_ADDRESS, 745 MODE_CTRL, 746 FLD_INPUT_MODE, 747 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 748 749 /* Chroma to ADC2 */ 750 status = vid_blk_read_word(dev, AFE_CTRL, &value); 751 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 752 753 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 754 This sets them to use video 755 rather than audio. Only one of the two will be in use. */ 756 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 757 758 status = vid_blk_write_word(dev, AFE_CTRL, value); 759 760 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 761 break; 762 case CX231XX_VMUX_TELEVISION: 763 case CX231XX_VMUX_CABLE: 764 default: 765 /* TODO: Test if this is also needed for xc2028/xc3028 */ 766 if (dev->board.tuner_type == TUNER_XC5000) { 767 /* Disable the use of DIF */ 768 769 status = vid_blk_read_word(dev, AFE_CTRL, &value); 770 value |= (0 << 13) | (1 << 4); 771 value &= ~(1 << 5); 772 773 /* set [24:23] [22:15] to 0 */ 774 value &= (~(0x1FF8000)); 775 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 776 value |= 0x1000000; 777 status = vid_blk_write_word(dev, AFE_CTRL, value); 778 779 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 780 value |= (1 << 7); 781 status = vid_blk_write_word(dev, OUT_CTRL1, value); 782 783 /* Set output mode */ 784 status = cx231xx_read_modify_write_i2c_dword(dev, 785 VID_BLK_I2C_ADDRESS, 786 OUT_CTRL1, FLD_OUT_MODE, 787 dev->board.output_mode); 788 789 /* Tell DIF object to go to baseband mode */ 790 status = cx231xx_dif_set_standard(dev, 791 DIF_USE_BASEBAND); 792 if (status < 0) { 793 cx231xx_errdev("%s: cx231xx_dif set to By pass" 794 " mode- errCode [%d]!\n", 795 __func__, status); 796 return status; 797 } 798 799 /* Read the DFE_CTRL1 register */ 800 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 801 802 /* enable the VBI_GATE_EN */ 803 value |= FLD_VBI_GATE_EN; 804 805 /* Enable the auto-VGA enable */ 806 value |= FLD_VGA_AUTO_EN; 807 808 /* Write it back */ 809 status = vid_blk_write_word(dev, DFE_CTRL1, value); 810 811 /* Disable auto config of registers */ 812 status = cx231xx_read_modify_write_i2c_dword(dev, 813 VID_BLK_I2C_ADDRESS, 814 MODE_CTRL, FLD_ACFG_DIS, 815 cx231xx_set_field(FLD_ACFG_DIS, 1)); 816 817 /* Set CVBS input mode */ 818 status = cx231xx_read_modify_write_i2c_dword(dev, 819 VID_BLK_I2C_ADDRESS, 820 MODE_CTRL, FLD_INPUT_MODE, 821 cx231xx_set_field(FLD_INPUT_MODE, 822 INPUT_MODE_CVBS_0)); 823 } else { 824 /* Enable the DIF for the tuner */ 825 826 /* Reinitialize the DIF */ 827 status = cx231xx_dif_set_standard(dev, dev->norm); 828 if (status < 0) { 829 cx231xx_errdev("%s: cx231xx_dif set to By pass" 830 " mode- errCode [%d]!\n", 831 __func__, status); 832 return status; 833 } 834 835 /* Make sure bypass is cleared */ 836 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 837 838 /* Clear the bypass bit */ 839 value &= ~FLD_DIF_DIF_BYPASS; 840 841 /* Enable the use of the DIF block */ 842 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 843 844 /* Read the DFE_CTRL1 register */ 845 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 846 847 /* Disable the VBI_GATE_EN */ 848 value &= ~FLD_VBI_GATE_EN; 849 850 /* Enable the auto-VGA enable, AGC, and 851 set the skip count to 2 */ 852 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 853 854 /* Write it back */ 855 status = vid_blk_write_word(dev, DFE_CTRL1, value); 856 857 /* Wait until AGC locks up */ 858 msleep(1); 859 860 /* Disable the auto-VGA enable AGC */ 861 value &= ~(FLD_VGA_AUTO_EN); 862 863 /* Write it back */ 864 status = vid_blk_write_word(dev, DFE_CTRL1, value); 865 866 /* Enable Polaris B0 AGC output */ 867 status = vid_blk_read_word(dev, PIN_CTRL, &value); 868 value |= (FLD_OEF_AGC_RF) | 869 (FLD_OEF_AGC_IFVGA) | 870 (FLD_OEF_AGC_IF); 871 status = vid_blk_write_word(dev, PIN_CTRL, value); 872 873 /* Set output mode */ 874 status = cx231xx_read_modify_write_i2c_dword(dev, 875 VID_BLK_I2C_ADDRESS, 876 OUT_CTRL1, FLD_OUT_MODE, 877 dev->board.output_mode); 878 879 /* Disable auto config of registers */ 880 status = cx231xx_read_modify_write_i2c_dword(dev, 881 VID_BLK_I2C_ADDRESS, 882 MODE_CTRL, FLD_ACFG_DIS, 883 cx231xx_set_field(FLD_ACFG_DIS, 1)); 884 885 /* Set CVBS input mode */ 886 status = cx231xx_read_modify_write_i2c_dword(dev, 887 VID_BLK_I2C_ADDRESS, 888 MODE_CTRL, FLD_INPUT_MODE, 889 cx231xx_set_field(FLD_INPUT_MODE, 890 INPUT_MODE_CVBS_0)); 891 892 /* Set some bits in AFE_CTRL so that channel 2 or 3 893 * is ready to receive audio */ 894 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 895 /* Clear droop comp (bit 19-20) */ 896 /* Set VGA_SEL (for audio control) (bit 7-8) */ 897 status = vid_blk_read_word(dev, AFE_CTRL, &value); 898 899 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 900 value &= (~(FLD_FUNC_MODE)); 901 value |= 0x800000; 902 903 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 904 905 status = vid_blk_write_word(dev, AFE_CTRL, value); 906 907 if (dev->tuner_type == TUNER_NXP_TDA18271) { 908 status = vid_blk_read_word(dev, PIN_CTRL, 909 &value); 910 status = vid_blk_write_word(dev, PIN_CTRL, 911 (value & 0xFFFFFFEF)); 912 } 913 914 break; 915 916 } 917 break; 918 } 919 920 /* Set raw VBI mode */ 921 status = cx231xx_read_modify_write_i2c_dword(dev, 922 VID_BLK_I2C_ADDRESS, 923 OUT_CTRL1, FLD_VBIHACTRAW_EN, 924 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 925 926 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 927 if (value & 0x02) { 928 value |= (1 << 19); 929 status = vid_blk_write_word(dev, OUT_CTRL1, value); 930 } 931 932 return status; 933} 934 935void cx231xx_enable656(struct cx231xx *dev) 936{ 937 u8 temp = 0; 938 /*enable TS1 data[0:7] as output to export 656*/ 939 940 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 941 942 /*enable TS1 clock as output to export 656*/ 943 944 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 945 temp = temp|0x04; 946 947 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 948} 949EXPORT_SYMBOL_GPL(cx231xx_enable656); 950 951void cx231xx_disable656(struct cx231xx *dev) 952{ 953 u8 temp = 0; 954 955 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 956 957 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 958 temp = temp&0xFB; 959 960 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 961} 962EXPORT_SYMBOL_GPL(cx231xx_disable656); 963 964/* 965 * Handle any video-mode specific overrides that are different 966 * on a per video standards basis after touching the MODE_CTRL 967 * register which resets many values for autodetect 968 */ 969int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 970{ 971 int status = 0; 972 973 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 974 (unsigned int)dev->norm); 975 976 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 977 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 978 979 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 980 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 981 982 /* Move the close caption lines out of active video, 983 adjust the active video start point */ 984 status = cx231xx_read_modify_write_i2c_dword(dev, 985 VID_BLK_I2C_ADDRESS, 986 VERT_TIM_CTRL, 987 FLD_VBLANK_CNT, 0x18); 988 status = cx231xx_read_modify_write_i2c_dword(dev, 989 VID_BLK_I2C_ADDRESS, 990 VERT_TIM_CTRL, 991 FLD_VACTIVE_CNT, 992 0x1E7000); 993 status = cx231xx_read_modify_write_i2c_dword(dev, 994 VID_BLK_I2C_ADDRESS, 995 VERT_TIM_CTRL, 996 FLD_V656BLANK_CNT, 997 0x1C000000); 998 999 status = cx231xx_read_modify_write_i2c_dword(dev, 1000 VID_BLK_I2C_ADDRESS, 1001 HORIZ_TIM_CTRL, 1002 FLD_HBLANK_CNT, 1003 cx231xx_set_field 1004 (FLD_HBLANK_CNT, 0x79)); 1005 1006 } else if (dev->norm & V4L2_STD_SECAM) { 1007 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 1008 status = cx231xx_read_modify_write_i2c_dword(dev, 1009 VID_BLK_I2C_ADDRESS, 1010 VERT_TIM_CTRL, 1011 FLD_VBLANK_CNT, 0x20); 1012 status = cx231xx_read_modify_write_i2c_dword(dev, 1013 VID_BLK_I2C_ADDRESS, 1014 VERT_TIM_CTRL, 1015 FLD_VACTIVE_CNT, 1016 cx231xx_set_field 1017 (FLD_VACTIVE_CNT, 1018 0x244)); 1019 status = cx231xx_read_modify_write_i2c_dword(dev, 1020 VID_BLK_I2C_ADDRESS, 1021 VERT_TIM_CTRL, 1022 FLD_V656BLANK_CNT, 1023 cx231xx_set_field 1024 (FLD_V656BLANK_CNT, 1025 0x24)); 1026 /* Adjust the active video horizontal start point */ 1027 status = cx231xx_read_modify_write_i2c_dword(dev, 1028 VID_BLK_I2C_ADDRESS, 1029 HORIZ_TIM_CTRL, 1030 FLD_HBLANK_CNT, 1031 cx231xx_set_field 1032 (FLD_HBLANK_CNT, 0x85)); 1033 } else { 1034 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 1035 status = cx231xx_read_modify_write_i2c_dword(dev, 1036 VID_BLK_I2C_ADDRESS, 1037 VERT_TIM_CTRL, 1038 FLD_VBLANK_CNT, 0x20); 1039 status = cx231xx_read_modify_write_i2c_dword(dev, 1040 VID_BLK_I2C_ADDRESS, 1041 VERT_TIM_CTRL, 1042 FLD_VACTIVE_CNT, 1043 cx231xx_set_field 1044 (FLD_VACTIVE_CNT, 1045 0x244)); 1046 status = cx231xx_read_modify_write_i2c_dword(dev, 1047 VID_BLK_I2C_ADDRESS, 1048 VERT_TIM_CTRL, 1049 FLD_V656BLANK_CNT, 1050 cx231xx_set_field 1051 (FLD_V656BLANK_CNT, 1052 0x24)); 1053 /* Adjust the active video horizontal start point */ 1054 status = cx231xx_read_modify_write_i2c_dword(dev, 1055 VID_BLK_I2C_ADDRESS, 1056 HORIZ_TIM_CTRL, 1057 FLD_HBLANK_CNT, 1058 cx231xx_set_field 1059 (FLD_HBLANK_CNT, 0x85)); 1060 1061 } 1062 1063 return status; 1064} 1065 1066int cx231xx_unmute_audio(struct cx231xx *dev) 1067{ 1068 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1069} 1070EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1071 1072static int stopAudioFirmware(struct cx231xx *dev) 1073{ 1074 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1075} 1076 1077static int restartAudioFirmware(struct cx231xx *dev) 1078{ 1079 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1080} 1081 1082int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1083{ 1084 int status = 0; 1085 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1086 1087 switch (INPUT(input)->amux) { 1088 case CX231XX_AMUX_VIDEO: 1089 ainput = AUDIO_INPUT_TUNER_TV; 1090 break; 1091 case CX231XX_AMUX_LINE_IN: 1092 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1093 ainput = AUDIO_INPUT_LINE; 1094 break; 1095 default: 1096 break; 1097 } 1098 1099 status = cx231xx_set_audio_decoder_input(dev, ainput); 1100 1101 return status; 1102} 1103 1104int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1105 enum AUDIO_INPUT audio_input) 1106{ 1107 u32 dwval; 1108 int status; 1109 u8 gen_ctrl; 1110 u32 value = 0; 1111 1112 /* Put it in soft reset */ 1113 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1114 gen_ctrl |= 1; 1115 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1116 1117 switch (audio_input) { 1118 case AUDIO_INPUT_LINE: 1119 /* setup AUD_IO control from Merlin paralle output */ 1120 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1121 AUD_CHAN_SRC_PARALLEL); 1122 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1123 1124 /* setup input to Merlin, SRC2 connect to AC97 1125 bypass upsample-by-2, slave mode, sony mode, left justify 1126 adr 091c, dat 01000000 */ 1127 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1128 1129 status = vid_blk_write_word(dev, AC97_CTL, 1130 (dwval | FLD_AC97_UP2X_BYPASS)); 1131 1132 /* select the parallel1 and SRC3 */ 1133 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1134 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1135 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1136 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1137 1138 /* unmute all, AC97 in, independence mode 1139 adr 08d0, data 0x00063073 */ 1140 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1141 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1142 1143 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1144 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1145 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1146 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1147 1148 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1149 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1150 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1151 (dwval | FLD_PATH1_SC_THRESHOLD)); 1152 break; 1153 1154 case AUDIO_INPUT_TUNER_TV: 1155 default: 1156 status = stopAudioFirmware(dev); 1157 /* Setup SRC sources and clocks */ 1158 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1159 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1160 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1161 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1162 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1163 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1164 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1165 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1166 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1167 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1168 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1169 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1170 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1171 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1172 1173 /* Setup the AUD_IO control */ 1174 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1175 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1176 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1177 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1178 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1179 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1180 1181 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1182 1183 /* setAudioStandard(_audio_standard); */ 1184 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1185 1186 status = restartAudioFirmware(dev); 1187 1188 switch (dev->board.tuner_type) { 1189 case TUNER_XC5000: 1190 /* SIF passthrough at 28.6363 MHz sample rate */ 1191 status = cx231xx_read_modify_write_i2c_dword(dev, 1192 VID_BLK_I2C_ADDRESS, 1193 CHIP_CTRL, 1194 FLD_SIF_EN, 1195 cx231xx_set_field(FLD_SIF_EN, 1)); 1196 break; 1197 case TUNER_NXP_TDA18271: 1198 /* Normal mode: SIF passthrough at 14.32 MHz */ 1199 status = cx231xx_read_modify_write_i2c_dword(dev, 1200 VID_BLK_I2C_ADDRESS, 1201 CHIP_CTRL, 1202 FLD_SIF_EN, 1203 cx231xx_set_field(FLD_SIF_EN, 0)); 1204 break; 1205 default: 1206 /* This is just a casual suggestion to people adding 1207 new boards in case they use a tuner type we don't 1208 currently know about */ 1209 printk(KERN_INFO "Unknown tuner type configuring SIF"); 1210 break; 1211 } 1212 break; 1213 1214 case AUDIO_INPUT_TUNER_FM: 1215 /* use SIF for FM radio 1216 setupFM(); 1217 setAudioStandard(_audio_standard); 1218 */ 1219 break; 1220 1221 case AUDIO_INPUT_MUTE: 1222 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1223 break; 1224 } 1225 1226 /* Take it out of soft reset */ 1227 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1228 gen_ctrl &= ~1; 1229 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1230 1231 return status; 1232} 1233 1234/****************************************************************************** 1235 * C H I P Specific C O N T R O L functions * 1236 ******************************************************************************/ 1237int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1238{ 1239 u32 value; 1240 int status = 0; 1241 1242 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1243 value |= (~dev->board.ctl_pin_status_mask); 1244 status = vid_blk_write_word(dev, PIN_CTRL, value); 1245 1246 return status; 1247} 1248 1249int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1250 u8 analog_or_digital) 1251{ 1252 int status = 0; 1253 1254 /* first set the direction to output */ 1255 status = cx231xx_set_gpio_direction(dev, 1256 dev->board. 1257 agc_analog_digital_select_gpio, 1); 1258 1259 /* 0 - demod ; 1 - Analog mode */ 1260 status = cx231xx_set_gpio_value(dev, 1261 dev->board.agc_analog_digital_select_gpio, 1262 analog_or_digital); 1263 1264 return status; 1265} 1266 1267int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1268{ 1269 u8 value[4] = { 0, 0, 0, 0 }; 1270 int status = 0; 1271 bool current_is_port_3; 1272 1273 if (dev->board.dont_use_port_3) 1274 is_port_3 = false; 1275 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1276 PWR_CTL_EN, value, 4); 1277 if (status < 0) 1278 return status; 1279 1280 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1281 1282 /* Just return, if already using the right port */ 1283 if (current_is_port_3 == is_port_3) 1284 return 0; 1285 1286 if (is_port_3) 1287 value[0] |= I2C_DEMOD_EN; 1288 else 1289 value[0] &= ~I2C_DEMOD_EN; 1290 1291 cx231xx_info("Changing the i2c master port to %d\n", 1292 is_port_3 ? 3 : 1); 1293 1294 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1295 PWR_CTL_EN, value, 4); 1296 1297 return status; 1298 1299} 1300EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1301 1302void update_HH_register_after_set_DIF(struct cx231xx *dev) 1303{ 1304/* 1305 u8 status = 0; 1306 u32 value = 0; 1307 1308 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1309 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1310 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1311 1312 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1313 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1314 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1315*/ 1316} 1317 1318void cx231xx_dump_HH_reg(struct cx231xx *dev) 1319{ 1320 u32 value = 0; 1321 u16 i = 0; 1322 1323 value = 0x45005390; 1324 vid_blk_write_word(dev, 0x104, value); 1325 1326 for (i = 0x100; i < 0x140; i++) { 1327 vid_blk_read_word(dev, i, &value); 1328 cx231xx_info("reg0x%x=0x%x\n", i, value); 1329 i = i+3; 1330 } 1331 1332 for (i = 0x300; i < 0x400; i++) { 1333 vid_blk_read_word(dev, i, &value); 1334 cx231xx_info("reg0x%x=0x%x\n", i, value); 1335 i = i+3; 1336 } 1337 1338 for (i = 0x400; i < 0x440; i++) { 1339 vid_blk_read_word(dev, i, &value); 1340 cx231xx_info("reg0x%x=0x%x\n", i, value); 1341 i = i+3; 1342 } 1343 1344 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1345 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1346 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1347 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1348 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1349} 1350 1351void cx231xx_dump_SC_reg(struct cx231xx *dev) 1352{ 1353 u8 value[4] = { 0, 0, 0, 0 }; 1354 cx231xx_info("cx231xx_dump_SC_reg!\n"); 1355 1356 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1357 value, 4); 1358 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1359 value[1], value[2], value[3]); 1360 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1361 value, 4); 1362 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1363 value[1], value[2], value[3]); 1364 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1365 value, 4); 1366 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1367 value[1], value[2], value[3]); 1368 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1369 value, 4); 1370 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1371 value[1], value[2], value[3]); 1372 1373 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1374 value, 4); 1375 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1376 value[1], value[2], value[3]); 1377 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1378 value, 4); 1379 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1380 value[1], value[2], value[3]); 1381 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1382 value, 4); 1383 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1384 value[1], value[2], value[3]); 1385 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1386 value, 4); 1387 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1388 value[1], value[2], value[3]); 1389 1390 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1391 value, 4); 1392 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1393 value[1], value[2], value[3]); 1394 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1395 value, 4); 1396 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1397 value[1], value[2], value[3]); 1398 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1399 value, 4); 1400 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1401 value[1], value[2], value[3]); 1402 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1403 value, 4); 1404 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1405 value[1], value[2], value[3]); 1406 1407 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1408 value, 4); 1409 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1410 value[1], value[2], value[3]); 1411 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1412 value, 4); 1413 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1414 value[1], value[2], value[3]); 1415 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1416 value, 4); 1417 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1418 value[1], value[2], value[3]); 1419 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1420 value, 4); 1421 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1422 value[1], value[2], value[3]); 1423 1424 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1425 value, 4); 1426 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1427 value[1], value[2], value[3]); 1428 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1429 value, 4); 1430 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1431 value[1], value[2], value[3]); 1432 1433 1434} 1435 1436void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1437 1438{ 1439 u8 value = 0; 1440 1441 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1442 value = (value & 0xFE)|0x01; 1443 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1444 1445 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1446 value = (value & 0xFE)|0x00; 1447 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1448 1449 1450/* 1451 config colibri to lo-if mode 1452 1453 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1454 the diff IF input by half, 1455 1456 for low-if agc defect 1457*/ 1458 1459 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1460 value = (value & 0xFC)|0x00; 1461 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1462 1463 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1464 value = (value & 0xF9)|0x02; 1465 afe_write_byte(dev, ADC_INPUT_CH3, value); 1466 1467 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1468 value = (value & 0xFB)|0x04; 1469 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1470 1471 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1472 value = (value & 0xFC)|0x03; 1473 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1474 1475 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1476 value = (value & 0xFB)|0x04; 1477 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1478 1479 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1480 value = (value & 0xF8)|0x06; 1481 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1482 1483 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1484 value = (value & 0x8F)|0x40; 1485 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1486 1487 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1488 value = (value & 0xDF)|0x20; 1489 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1490} 1491 1492void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1493 u8 spectral_invert, u32 mode) 1494{ 1495 u32 colibri_carrier_offset = 0; 1496 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1497 u32 standard = 0; 1498 u8 value[4] = { 0, 0, 0, 0 }; 1499 1500 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); 1501 value[0] = (u8) 0x6F; 1502 value[1] = (u8) 0x6F; 1503 value[2] = (u8) 0x6F; 1504 value[3] = (u8) 0x6F; 1505 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1506 PWR_CTL_EN, value, 4); 1507 1508 /*Set colibri for low IF*/ 1509 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1510 1511 /* Set C2HH for low IF operation.*/ 1512 standard = dev->norm; 1513 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1514 func_mode, standard); 1515 1516 /* Get colibri offsets.*/ 1517 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1518 standard); 1519 1520 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", 1521 colibri_carrier_offset, standard); 1522 1523 /* Set the band Pass filter for DIF*/ 1524 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1525 spectral_invert, mode); 1526} 1527 1528u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1529{ 1530 u32 colibri_carrier_offset = 0; 1531 1532 if (mode == TUNER_MODE_FM_RADIO) { 1533 colibri_carrier_offset = 1100000; 1534 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1535 colibri_carrier_offset = 4832000; /*4.83MHz */ 1536 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1537 colibri_carrier_offset = 2700000; /*2.70MHz */ 1538 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1539 | V4L2_STD_SECAM)) { 1540 colibri_carrier_offset = 2100000; /*2.10MHz */ 1541 } 1542 1543 return colibri_carrier_offset; 1544} 1545 1546void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1547 u8 spectral_invert, u32 mode) 1548{ 1549 unsigned long pll_freq_word; 1550 u32 dif_misc_ctrl_value = 0; 1551 u64 pll_freq_u64 = 0; 1552 u32 i = 0; 1553 1554 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1555 if_freq, spectral_invert, mode); 1556 1557 1558 if (mode == TUNER_MODE_FM_RADIO) { 1559 pll_freq_word = 0x905A1CAC; 1560 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1561 1562 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1563 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1564 pll_freq_word = if_freq; 1565 pll_freq_u64 = (u64)pll_freq_word << 28L; 1566 do_div(pll_freq_u64, 50000000); 1567 pll_freq_word = (u32)pll_freq_u64; 1568 /*pll_freq_word = 0x3463497;*/ 1569 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1570 1571 if (spectral_invert) { 1572 if_freq -= 400000; 1573 /* Enable Spectral Invert*/ 1574 vid_blk_read_word(dev, DIF_MISC_CTRL, 1575 &dif_misc_ctrl_value); 1576 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1577 vid_blk_write_word(dev, DIF_MISC_CTRL, 1578 dif_misc_ctrl_value); 1579 } else { 1580 if_freq += 400000; 1581 /* Disable Spectral Invert*/ 1582 vid_blk_read_word(dev, DIF_MISC_CTRL, 1583 &dif_misc_ctrl_value); 1584 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1585 vid_blk_write_word(dev, DIF_MISC_CTRL, 1586 dif_misc_ctrl_value); 1587 } 1588 1589 if_freq = (if_freq/100000)*100000; 1590 1591 if (if_freq < 3000000) 1592 if_freq = 3000000; 1593 1594 if (if_freq > 16000000) 1595 if_freq = 16000000; 1596 } 1597 1598 cx231xx_info("Enter IF=%zu\n", 1599 ARRAY_SIZE(Dif_set_array)); 1600 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1601 if (Dif_set_array[i].if_freq == if_freq) { 1602 vid_blk_write_word(dev, 1603 Dif_set_array[i].register_address, Dif_set_array[i].value); 1604 } 1605 } 1606} 1607 1608/****************************************************************************** 1609 * D I F - B L O C K C O N T R O L functions * 1610 ******************************************************************************/ 1611int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1612 u32 function_mode, u32 standard) 1613{ 1614 int status = 0; 1615 1616 1617 if (mode == V4L2_TUNER_RADIO) { 1618 /* C2HH */ 1619 /* lo if big signal */ 1620 status = cx231xx_reg_mask_write(dev, 1621 VID_BLK_I2C_ADDRESS, 32, 1622 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1623 /* FUNC_MODE = DIF */ 1624 status = cx231xx_reg_mask_write(dev, 1625 VID_BLK_I2C_ADDRESS, 32, 1626 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1627 /* IF_MODE */ 1628 status = cx231xx_reg_mask_write(dev, 1629 VID_BLK_I2C_ADDRESS, 32, 1630 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1631 /* no inv */ 1632 status = cx231xx_reg_mask_write(dev, 1633 VID_BLK_I2C_ADDRESS, 32, 1634 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1635 } else if (standard != DIF_USE_BASEBAND) { 1636 if (standard & V4L2_STD_MN) { 1637 /* lo if big signal */ 1638 status = cx231xx_reg_mask_write(dev, 1639 VID_BLK_I2C_ADDRESS, 32, 1640 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1641 /* FUNC_MODE = DIF */ 1642 status = cx231xx_reg_mask_write(dev, 1643 VID_BLK_I2C_ADDRESS, 32, 1644 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1645 function_mode); 1646 /* IF_MODE */ 1647 status = cx231xx_reg_mask_write(dev, 1648 VID_BLK_I2C_ADDRESS, 32, 1649 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1650 /* no inv */ 1651 status = cx231xx_reg_mask_write(dev, 1652 VID_BLK_I2C_ADDRESS, 32, 1653 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1654 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1655 status = cx231xx_reg_mask_write(dev, 1656 VID_BLK_I2C_ADDRESS, 32, 1657 AUD_IO_CTRL, 0, 31, 0x00000003); 1658 } else if ((standard == V4L2_STD_PAL_I) | 1659 (standard & V4L2_STD_PAL_D) | 1660 (standard & V4L2_STD_SECAM)) { 1661 /* C2HH setup */ 1662 /* lo if big signal */ 1663 status = cx231xx_reg_mask_write(dev, 1664 VID_BLK_I2C_ADDRESS, 32, 1665 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1666 /* FUNC_MODE = DIF */ 1667 status = cx231xx_reg_mask_write(dev, 1668 VID_BLK_I2C_ADDRESS, 32, 1669 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1670 function_mode); 1671 /* IF_MODE */ 1672 status = cx231xx_reg_mask_write(dev, 1673 VID_BLK_I2C_ADDRESS, 32, 1674 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1675 /* no inv */ 1676 status = cx231xx_reg_mask_write(dev, 1677 VID_BLK_I2C_ADDRESS, 32, 1678 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1679 } else { 1680 /* default PAL BG */ 1681 /* C2HH setup */ 1682 /* lo if big signal */ 1683 status = cx231xx_reg_mask_write(dev, 1684 VID_BLK_I2C_ADDRESS, 32, 1685 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1686 /* FUNC_MODE = DIF */ 1687 status = cx231xx_reg_mask_write(dev, 1688 VID_BLK_I2C_ADDRESS, 32, 1689 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1690 function_mode); 1691 /* IF_MODE */ 1692 status = cx231xx_reg_mask_write(dev, 1693 VID_BLK_I2C_ADDRESS, 32, 1694 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1695 /* no inv */ 1696 status = cx231xx_reg_mask_write(dev, 1697 VID_BLK_I2C_ADDRESS, 32, 1698 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1699 } 1700 } 1701 1702 return status; 1703} 1704 1705int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1706{ 1707 int status = 0; 1708 u32 dif_misc_ctrl_value = 0; 1709 u32 func_mode = 0; 1710 1711 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1712 1713 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1714 if (standard != DIF_USE_BASEBAND) 1715 dev->norm = standard; 1716 1717 switch (dev->model) { 1718 case CX231XX_BOARD_CNXT_CARRAERA: 1719 case CX231XX_BOARD_CNXT_RDE_250: 1720 case CX231XX_BOARD_CNXT_SHELBY: 1721 case CX231XX_BOARD_CNXT_RDU_250: 1722 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1723 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1724 case CX231XX_BOARD_OTG102: 1725 func_mode = 0x03; 1726 break; 1727 case CX231XX_BOARD_CNXT_RDE_253S: 1728 case CX231XX_BOARD_CNXT_RDU_253S: 1729 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1730 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1731 func_mode = 0x01; 1732 break; 1733 default: 1734 func_mode = 0x01; 1735 } 1736 1737 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1738 func_mode, standard); 1739 1740 if (standard == DIF_USE_BASEBAND) { /* base band */ 1741 /* There is a different SRC_PHASE_INC value 1742 for baseband vs. DIF */ 1743 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1744 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1745 &dif_misc_ctrl_value); 1746 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1747 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1748 dif_misc_ctrl_value); 1749 } else if (standard & V4L2_STD_PAL_D) { 1750 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1751 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1752 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1753 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1754 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1755 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1756 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1757 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1759 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1761 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1763 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1765 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1766 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1767 DIF_AGC_IF_INT_CURRENT, 0, 31, 1768 0x26001700); 1769 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1770 DIF_AGC_RF_CURRENT, 0, 31, 1771 0x00002660); 1772 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1773 DIF_VIDEO_AGC_CTRL, 0, 31, 1774 0x72500800); 1775 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1776 DIF_VID_AUD_OVERRIDE, 0, 31, 1777 0x27000100); 1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1779 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1780 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1781 DIF_COMP_FLT_CTRL, 0, 31, 1782 0x00000000); 1783 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1784 DIF_SRC_PHASE_INC, 0, 31, 1785 0x1befbf06); 1786 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1787 DIF_SRC_GAIN_CONTROL, 0, 31, 1788 0x000035e8); 1789 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1790 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1791 /* Save the Spec Inversion value */ 1792 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1793 dif_misc_ctrl_value |= 0x3a023F11; 1794 } else if (standard & V4L2_STD_PAL_I) { 1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1796 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1798 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1799 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1800 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1802 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1804 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1806 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1808 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1810 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1811 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1812 DIF_AGC_IF_INT_CURRENT, 0, 31, 1813 0x26001700); 1814 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1815 DIF_AGC_RF_CURRENT, 0, 31, 1816 0x00002660); 1817 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1818 DIF_VIDEO_AGC_CTRL, 0, 31, 1819 0x72500800); 1820 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1821 DIF_VID_AUD_OVERRIDE, 0, 31, 1822 0x27000100); 1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1824 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1825 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1826 DIF_COMP_FLT_CTRL, 0, 31, 1827 0x00000000); 1828 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1829 DIF_SRC_PHASE_INC, 0, 31, 1830 0x1befbf06); 1831 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1832 DIF_SRC_GAIN_CONTROL, 0, 31, 1833 0x000035e8); 1834 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1835 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1836 /* Save the Spec Inversion value */ 1837 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1838 dif_misc_ctrl_value |= 0x3a033F11; 1839 } else if (standard & V4L2_STD_PAL_M) { 1840 /* improved Low Frequency Phase Noise */ 1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1843 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1844 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1845 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1846 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1847 0x26001700); 1848 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1849 0x00002660); 1850 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1851 0x72500800); 1852 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1853 0x27000100); 1854 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1855 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1856 0x009f50c1); 1857 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1858 0x1befbf06); 1859 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1860 0x000035e8); 1861 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1862 0x00000000); 1863 /* Save the Spec Inversion value */ 1864 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1865 dif_misc_ctrl_value |= 0x3A0A3F10; 1866 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1867 /* improved Low Frequency Phase Noise */ 1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1870 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1871 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1872 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1873 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1874 0x26001700); 1875 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1876 0x00002660); 1877 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1878 0x72500800); 1879 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1880 0x27000100); 1881 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1882 0x012c405d); 1883 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1884 0x009f50c1); 1885 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1886 0x1befbf06); 1887 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1888 0x000035e8); 1889 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1890 0x00000000); 1891 /* Save the Spec Inversion value */ 1892 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1893 dif_misc_ctrl_value = 0x3A093F10; 1894 } else if (standard & 1895 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1896 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1897 1898 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1899 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1900 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1901 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1902 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1903 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1904 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1905 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1907 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1909 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1911 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1913 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1914 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1915 DIF_AGC_IF_INT_CURRENT, 0, 31, 1916 0x26001700); 1917 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1918 DIF_AGC_RF_CURRENT, 0, 31, 1919 0x00002660); 1920 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1921 DIF_VID_AUD_OVERRIDE, 0, 31, 1922 0x27000100); 1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1924 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1925 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1926 DIF_COMP_FLT_CTRL, 0, 31, 1927 0x00000000); 1928 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1929 DIF_SRC_PHASE_INC, 0, 31, 1930 0x1befbf06); 1931 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1932 DIF_SRC_GAIN_CONTROL, 0, 31, 1933 0x000035e8); 1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1935 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1936 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1937 DIF_VIDEO_AGC_CTRL, 0, 31, 1938 0xf4000000); 1939 1940 /* Save the Spec Inversion value */ 1941 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1942 dif_misc_ctrl_value |= 0x3a023F11; 1943 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1944 /* Is it SECAM_L1? */ 1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1946 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1947 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1948 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1950 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1952 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1954 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1956 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1958 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1960 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1961 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1962 DIF_AGC_IF_INT_CURRENT, 0, 31, 1963 0x26001700); 1964 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1965 DIF_AGC_RF_CURRENT, 0, 31, 1966 0x00002660); 1967 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1968 DIF_VID_AUD_OVERRIDE, 0, 31, 1969 0x27000100); 1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1971 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1972 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1973 DIF_COMP_FLT_CTRL, 0, 31, 1974 0x00000000); 1975 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1976 DIF_SRC_PHASE_INC, 0, 31, 1977 0x1befbf06); 1978 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1979 DIF_SRC_GAIN_CONTROL, 0, 31, 1980 0x000035e8); 1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1982 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1983 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1984 DIF_VIDEO_AGC_CTRL, 0, 31, 1985 0xf2560000); 1986 1987 /* Save the Spec Inversion value */ 1988 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1989 dif_misc_ctrl_value |= 0x3a023F11; 1990 1991 } else if (standard & V4L2_STD_NTSC_M) { 1992 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 1993 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1994 1995 /* For NTSC the centre frequency of video coming out of 1996 sidewinder is around 7.1MHz or 3.6MHz depending on the 1997 spectral inversion. so for a non spectrally inverted channel 1998 the pll freq word is 0x03420c49 1999 */ 2000 2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2003 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2004 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2005 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2006 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2007 0x26001700); 2008 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2009 0x00002660); 2010 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2011 0x04000800); 2012 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2013 0x27000100); 2014 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2015 2016 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2017 0x009f50c1); 2018 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2019 0x1befbf06); 2020 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2021 0x000035e8); 2022 2023 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2024 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2025 0xC2262600); 2026 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2027 2028 /* Save the Spec Inversion value */ 2029 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2030 dif_misc_ctrl_value |= 0x3a003F10; 2031 } else { 2032 /* default PAL BG */ 2033 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2034 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2035 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2036 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2037 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2038 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2039 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2040 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2042 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2044 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2046 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2048 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2049 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2050 DIF_AGC_IF_INT_CURRENT, 0, 31, 2051 0x26001700); 2052 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2053 DIF_AGC_RF_CURRENT, 0, 31, 2054 0x00002660); 2055 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2056 DIF_VIDEO_AGC_CTRL, 0, 31, 2057 0x72500800); 2058 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2059 DIF_VID_AUD_OVERRIDE, 0, 31, 2060 0x27000100); 2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2062 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2063 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2064 DIF_COMP_FLT_CTRL, 0, 31, 2065 0x00A653A8); 2066 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2067 DIF_SRC_PHASE_INC, 0, 31, 2068 0x1befbf06); 2069 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2070 DIF_SRC_GAIN_CONTROL, 0, 31, 2071 0x000035e8); 2072 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2073 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2074 /* Save the Spec Inversion value */ 2075 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2076 dif_misc_ctrl_value |= 0x3a013F11; 2077 } 2078 2079 /* The AGC values should be the same for all standards, 2080 AUD_SRC_SEL[19] should always be disabled */ 2081 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2082 2083 /* It is still possible to get Set Standard calls even when we 2084 are in FM mode. 2085 This is done to override the value for FM. */ 2086 if (dev->active_mode == V4L2_TUNER_RADIO) 2087 dif_misc_ctrl_value = 0x7a080000; 2088 2089 /* Write the calculated value for misc ontrol register */ 2090 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2091 2092 return status; 2093} 2094 2095int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2096{ 2097 int status = 0; 2098 u32 dwval; 2099 2100 /* Set the RF and IF k_agc values to 3 */ 2101 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2102 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2103 dwval |= 0x33000000; 2104 2105 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2106 2107 return status; 2108} 2109 2110int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2111{ 2112 int status = 0; 2113 u32 dwval; 2114 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", 2115 dev->tuner_type); 2116 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2117 * SECAM L/B/D standards */ 2118 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2119 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2120 2121 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2122 V4L2_STD_SECAM_D)) { 2123 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2124 dwval &= ~FLD_DIF_IF_REF; 2125 dwval |= 0x88000300; 2126 } else 2127 dwval |= 0x88000000; 2128 } else { 2129 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2130 dwval &= ~FLD_DIF_IF_REF; 2131 dwval |= 0xCC000300; 2132 } else 2133 dwval |= 0x44000000; 2134 } 2135 2136 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2137 2138 return status == sizeof(dwval) ? 0 : -EIO; 2139} 2140 2141/****************************************************************************** 2142 * I 2 S - B L O C K C O N T R O L functions * 2143 ******************************************************************************/ 2144int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2145{ 2146 int status = 0; 2147 u32 value; 2148 2149 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2150 CH_PWR_CTRL1, 1, &value, 1); 2151 /* enables clock to delta-sigma and decimation filter */ 2152 value |= 0x80; 2153 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2154 CH_PWR_CTRL1, 1, value, 1); 2155 /* power up all channel */ 2156 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2157 CH_PWR_CTRL2, 1, 0x00, 1); 2158 2159 return status; 2160} 2161 2162int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2163 enum AV_MODE avmode) 2164{ 2165 int status = 0; 2166 u32 value = 0; 2167 2168 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2169 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2170 CH_PWR_CTRL2, 1, &value, 1); 2171 value |= 0xfe; 2172 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2173 CH_PWR_CTRL2, 1, value, 1); 2174 } else { 2175 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2176 CH_PWR_CTRL2, 1, 0x00, 1); 2177 } 2178 2179 return status; 2180} 2181 2182/* set i2s_blk for audio input types */ 2183int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2184{ 2185 int status = 0; 2186 2187 switch (audio_input) { 2188 case CX231XX_AMUX_LINE_IN: 2189 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2190 CH_PWR_CTRL2, 1, 0x00, 1); 2191 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2192 CH_PWR_CTRL1, 1, 0x80, 1); 2193 break; 2194 case CX231XX_AMUX_VIDEO: 2195 default: 2196 break; 2197 } 2198 2199 dev->ctl_ainput = audio_input; 2200 2201 return status; 2202} 2203 2204/****************************************************************************** 2205 * P O W E R C O N T R O L functions * 2206 ******************************************************************************/ 2207int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2208{ 2209 u8 value[4] = { 0, 0, 0, 0 }; 2210 u32 tmp = 0; 2211 int status = 0; 2212 2213 if (dev->power_mode != mode) 2214 dev->power_mode = mode; 2215 else { 2216 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", 2217 mode); 2218 return 0; 2219 } 2220 2221 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2222 4); 2223 if (status < 0) 2224 return status; 2225 2226 tmp = le32_to_cpu(*((__le32 *) value)); 2227 2228 switch (mode) { 2229 case POLARIS_AVMODE_ENXTERNAL_AV: 2230 2231 tmp &= (~PWR_MODE_MASK); 2232 2233 tmp |= PWR_AV_EN; 2234 value[0] = (u8) tmp; 2235 value[1] = (u8) (tmp >> 8); 2236 value[2] = (u8) (tmp >> 16); 2237 value[3] = (u8) (tmp >> 24); 2238 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2239 PWR_CTL_EN, value, 4); 2240 msleep(PWR_SLEEP_INTERVAL); 2241 2242 tmp |= PWR_ISO_EN; 2243 value[0] = (u8) tmp; 2244 value[1] = (u8) (tmp >> 8); 2245 value[2] = (u8) (tmp >> 16); 2246 value[3] = (u8) (tmp >> 24); 2247 status = 2248 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2249 value, 4); 2250 msleep(PWR_SLEEP_INTERVAL); 2251 2252 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2253 value[0] = (u8) tmp; 2254 value[1] = (u8) (tmp >> 8); 2255 value[2] = (u8) (tmp >> 16); 2256 value[3] = (u8) (tmp >> 24); 2257 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2258 PWR_CTL_EN, value, 4); 2259 2260 /* reset state of xceive tuner */ 2261 dev->xc_fw_load_done = 0; 2262 break; 2263 2264 case POLARIS_AVMODE_ANALOGT_TV: 2265 2266 tmp |= PWR_DEMOD_EN; 2267 tmp |= (I2C_DEMOD_EN); 2268 value[0] = (u8) tmp; 2269 value[1] = (u8) (tmp >> 8); 2270 value[2] = (u8) (tmp >> 16); 2271 value[3] = (u8) (tmp >> 24); 2272 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2273 PWR_CTL_EN, value, 4); 2274 msleep(PWR_SLEEP_INTERVAL); 2275 2276 if (!(tmp & PWR_TUNER_EN)) { 2277 tmp |= (PWR_TUNER_EN); 2278 value[0] = (u8) tmp; 2279 value[1] = (u8) (tmp >> 8); 2280 value[2] = (u8) (tmp >> 16); 2281 value[3] = (u8) (tmp >> 24); 2282 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2283 PWR_CTL_EN, value, 4); 2284 msleep(PWR_SLEEP_INTERVAL); 2285 } 2286 2287 if (!(tmp & PWR_AV_EN)) { 2288 tmp |= PWR_AV_EN; 2289 value[0] = (u8) tmp; 2290 value[1] = (u8) (tmp >> 8); 2291 value[2] = (u8) (tmp >> 16); 2292 value[3] = (u8) (tmp >> 24); 2293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2294 PWR_CTL_EN, value, 4); 2295 msleep(PWR_SLEEP_INTERVAL); 2296 } 2297 if (!(tmp & PWR_ISO_EN)) { 2298 tmp |= PWR_ISO_EN; 2299 value[0] = (u8) tmp; 2300 value[1] = (u8) (tmp >> 8); 2301 value[2] = (u8) (tmp >> 16); 2302 value[3] = (u8) (tmp >> 24); 2303 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2304 PWR_CTL_EN, value, 4); 2305 msleep(PWR_SLEEP_INTERVAL); 2306 } 2307 2308 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2309 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2310 value[0] = (u8) tmp; 2311 value[1] = (u8) (tmp >> 8); 2312 value[2] = (u8) (tmp >> 16); 2313 value[3] = (u8) (tmp >> 24); 2314 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2315 PWR_CTL_EN, value, 4); 2316 msleep(PWR_SLEEP_INTERVAL); 2317 } 2318 2319 if (dev->board.tuner_type != TUNER_ABSENT) { 2320 /* Enable tuner */ 2321 cx231xx_enable_i2c_port_3(dev, true); 2322 2323 /* reset the Tuner */ 2324 if (dev->board.tuner_gpio) 2325 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2326 2327 if (dev->cx231xx_reset_analog_tuner) 2328 dev->cx231xx_reset_analog_tuner(dev); 2329 } 2330 2331 break; 2332 2333 case POLARIS_AVMODE_DIGITAL: 2334 if (!(tmp & PWR_TUNER_EN)) { 2335 tmp |= (PWR_TUNER_EN); 2336 value[0] = (u8) tmp; 2337 value[1] = (u8) (tmp >> 8); 2338 value[2] = (u8) (tmp >> 16); 2339 value[3] = (u8) (tmp >> 24); 2340 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2341 PWR_CTL_EN, value, 4); 2342 msleep(PWR_SLEEP_INTERVAL); 2343 } 2344 if (!(tmp & PWR_AV_EN)) { 2345 tmp |= PWR_AV_EN; 2346 value[0] = (u8) tmp; 2347 value[1] = (u8) (tmp >> 8); 2348 value[2] = (u8) (tmp >> 16); 2349 value[3] = (u8) (tmp >> 24); 2350 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2351 PWR_CTL_EN, value, 4); 2352 msleep(PWR_SLEEP_INTERVAL); 2353 } 2354 if (!(tmp & PWR_ISO_EN)) { 2355 tmp |= PWR_ISO_EN; 2356 value[0] = (u8) tmp; 2357 value[1] = (u8) (tmp >> 8); 2358 value[2] = (u8) (tmp >> 16); 2359 value[3] = (u8) (tmp >> 24); 2360 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2361 PWR_CTL_EN, value, 4); 2362 msleep(PWR_SLEEP_INTERVAL); 2363 } 2364 2365 tmp &= (~PWR_AV_MODE); 2366 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; 2367 value[0] = (u8) tmp; 2368 value[1] = (u8) (tmp >> 8); 2369 value[2] = (u8) (tmp >> 16); 2370 value[3] = (u8) (tmp >> 24); 2371 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2372 PWR_CTL_EN, value, 4); 2373 msleep(PWR_SLEEP_INTERVAL); 2374 2375 if (!(tmp & PWR_DEMOD_EN)) { 2376 tmp |= PWR_DEMOD_EN; 2377 value[0] = (u8) tmp; 2378 value[1] = (u8) (tmp >> 8); 2379 value[2] = (u8) (tmp >> 16); 2380 value[3] = (u8) (tmp >> 24); 2381 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2382 PWR_CTL_EN, value, 4); 2383 msleep(PWR_SLEEP_INTERVAL); 2384 } 2385 2386 if (dev->board.tuner_type != TUNER_ABSENT) { 2387 /* 2388 * Enable tuner 2389 * Hauppauge Exeter seems to need to do something different! 2390 */ 2391 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) 2392 cx231xx_enable_i2c_port_3(dev, false); 2393 else 2394 cx231xx_enable_i2c_port_3(dev, true); 2395 2396 /* reset the Tuner */ 2397 if (dev->board.tuner_gpio) 2398 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2399 2400 if (dev->cx231xx_reset_analog_tuner) 2401 dev->cx231xx_reset_analog_tuner(dev); 2402 } 2403 break; 2404 2405 default: 2406 break; 2407 } 2408 2409 msleep(PWR_SLEEP_INTERVAL); 2410 2411 /* For power saving, only enable Pwr_resetout_n 2412 when digital TV is selected. */ 2413 if (mode == POLARIS_AVMODE_DIGITAL) { 2414 tmp |= PWR_RESETOUT_EN; 2415 value[0] = (u8) tmp; 2416 value[1] = (u8) (tmp >> 8); 2417 value[2] = (u8) (tmp >> 16); 2418 value[3] = (u8) (tmp >> 24); 2419 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2420 PWR_CTL_EN, value, 4); 2421 msleep(PWR_SLEEP_INTERVAL); 2422 } 2423 2424 /* update power control for afe */ 2425 status = cx231xx_afe_update_power_control(dev, mode); 2426 2427 /* update power control for i2s_blk */ 2428 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2429 2430 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2431 4); 2432 2433 return status; 2434} 2435 2436int cx231xx_power_suspend(struct cx231xx *dev) 2437{ 2438 u8 value[4] = { 0, 0, 0, 0 }; 2439 u32 tmp = 0; 2440 int status = 0; 2441 2442 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 2443 value, 4); 2444 if (status > 0) 2445 return status; 2446 2447 tmp = le32_to_cpu(*((__le32 *) value)); 2448 tmp &= (~PWR_MODE_MASK); 2449 2450 value[0] = (u8) tmp; 2451 value[1] = (u8) (tmp >> 8); 2452 value[2] = (u8) (tmp >> 16); 2453 value[3] = (u8) (tmp >> 24); 2454 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2455 value, 4); 2456 2457 return status; 2458} 2459 2460/****************************************************************************** 2461 * S T R E A M C O N T R O L functions * 2462 ******************************************************************************/ 2463int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2464{ 2465 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2466 u32 tmp = 0; 2467 int status = 0; 2468 2469 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 2470 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2471 value, 4); 2472 if (status < 0) 2473 return status; 2474 2475 tmp = le32_to_cpu(*((__le32 *) value)); 2476 tmp |= ep_mask; 2477 value[0] = (u8) tmp; 2478 value[1] = (u8) (tmp >> 8); 2479 value[2] = (u8) (tmp >> 16); 2480 value[3] = (u8) (tmp >> 24); 2481 2482 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2483 value, 4); 2484 2485 return status; 2486} 2487 2488int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2489{ 2490 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2491 u32 tmp = 0; 2492 int status = 0; 2493 2494 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); 2495 status = 2496 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2497 if (status < 0) 2498 return status; 2499 2500 tmp = le32_to_cpu(*((__le32 *) value)); 2501 tmp &= (~ep_mask); 2502 value[0] = (u8) tmp; 2503 value[1] = (u8) (tmp >> 8); 2504 value[2] = (u8) (tmp >> 16); 2505 value[3] = (u8) (tmp >> 24); 2506 2507 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2508 value, 4); 2509 2510 return status; 2511} 2512 2513int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2514{ 2515 int status = 0; 2516 u32 value = 0; 2517 u8 val[4] = { 0, 0, 0, 0 }; 2518 2519 if (dev->udev->speed == USB_SPEED_HIGH) { 2520 switch (media_type) { 2521 case Audio: 2522 cx231xx_info("%s: Audio enter HANC\n", __func__); 2523 status = 2524 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2525 break; 2526 2527 case Vbi: 2528 cx231xx_info("%s: set vanc registers\n", __func__); 2529 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2530 break; 2531 2532 case Sliced_cc: 2533 cx231xx_info("%s: set hanc registers\n", __func__); 2534 status = 2535 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2536 break; 2537 2538 case Raw_Video: 2539 cx231xx_info("%s: set video registers\n", __func__); 2540 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2541 break; 2542 2543 case TS1_serial_mode: 2544 cx231xx_info("%s: set ts1 registers", __func__); 2545 2546 if (dev->board.has_417) { 2547 cx231xx_info(" MPEG\n"); 2548 value &= 0xFFFFFFFC; 2549 value |= 0x3; 2550 2551 status = cx231xx_mode_register(dev, TS_MODE_REG, value); 2552 2553 val[0] = 0x04; 2554 val[1] = 0xA3; 2555 val[2] = 0x3B; 2556 val[3] = 0x00; 2557 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2558 TS1_CFG_REG, val, 4); 2559 2560 val[0] = 0x00; 2561 val[1] = 0x08; 2562 val[2] = 0x00; 2563 val[3] = 0x08; 2564 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2565 TS1_LENGTH_REG, val, 4); 2566 2567 } else { 2568 cx231xx_info(" BDA\n"); 2569 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2570 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); 2571 } 2572 break; 2573 2574 case TS1_parallel_mode: 2575 cx231xx_info("%s: set ts1 parallel mode registers\n", 2576 __func__); 2577 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2578 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2579 break; 2580 } 2581 } else { 2582 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2583 } 2584 2585 return status; 2586} 2587 2588int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2589{ 2590 int rc = -1; 2591 u32 ep_mask = -1; 2592 struct pcb_config *pcb_config; 2593 2594 /* get EP for media type */ 2595 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2596 2597 if (pcb_config->config_num) { 2598 switch (media_type) { 2599 case Raw_Video: 2600 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2601 break; 2602 case Audio: 2603 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2604 break; 2605 case Vbi: 2606 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2607 break; 2608 case Sliced_cc: 2609 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2610 break; 2611 case TS1_serial_mode: 2612 case TS1_parallel_mode: 2613 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2614 break; 2615 case TS2: 2616 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2617 break; 2618 } 2619 } 2620 2621 if (start) { 2622 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2623 2624 if (rc < 0) 2625 return rc; 2626 2627 /* enable video capture */ 2628 if (ep_mask > 0) 2629 rc = cx231xx_start_stream(dev, ep_mask); 2630 } else { 2631 /* disable video capture */ 2632 if (ep_mask > 0) 2633 rc = cx231xx_stop_stream(dev, ep_mask); 2634 } 2635 2636 return rc; 2637} 2638EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2639 2640/***************************************************************************** 2641* G P I O B I T control functions * 2642******************************************************************************/ 2643static int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 gpio_val) 2644{ 2645 int status = 0; 2646 2647 gpio_val = (__force u32)cpu_to_le32(gpio_val); 2648 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&gpio_val, 4, 0, 0); 2649 2650 return status; 2651} 2652 2653static int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u32 *gpio_val) 2654{ 2655 __le32 tmp; 2656 int status = 0; 2657 2658 status = cx231xx_send_gpio_cmd(dev, gpio_bit, (u8 *)&tmp, 4, 0, 1); 2659 *gpio_val = le32_to_cpu(tmp); 2660 2661 return status; 2662} 2663 2664/* 2665* cx231xx_set_gpio_direction 2666* Sets the direction of the GPIO pin to input or output 2667* 2668* Parameters : 2669* pin_number : The GPIO Pin number to program the direction for 2670* from 0 to 31 2671* pin_value : The Direction of the GPIO Pin under reference. 2672* 0 = Input direction 2673* 1 = Output direction 2674*/ 2675int cx231xx_set_gpio_direction(struct cx231xx *dev, 2676 int pin_number, int pin_value) 2677{ 2678 int status = 0; 2679 u32 value = 0; 2680 2681 /* Check for valid pin_number - if 32 , bail out */ 2682 if (pin_number >= 32) 2683 return -EINVAL; 2684 2685 /* input */ 2686 if (pin_value == 0) 2687 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2688 else 2689 value = dev->gpio_dir | (1 << pin_number); 2690 2691 status = cx231xx_set_gpio_bit(dev, value, dev->gpio_val); 2692 2693 /* cache the value for future */ 2694 dev->gpio_dir = value; 2695 2696 return status; 2697} 2698 2699/* 2700* cx231xx_set_gpio_value 2701* Sets the value of the GPIO pin to Logic high or low. The Pin under 2702* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2703* 2704* Parameters : 2705* pin_number : The GPIO Pin number to program the direction for 2706* pin_value : The value of the GPIO Pin under reference. 2707* 0 = set it to 0 2708* 1 = set it to 1 2709*/ 2710int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2711{ 2712 int status = 0; 2713 u32 value = 0; 2714 2715 /* Check for valid pin_number - if 0xFF , bail out */ 2716 if (pin_number >= 32) 2717 return -EINVAL; 2718 2719 /* first do a sanity check - if the Pin is not output, make it output */ 2720 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2721 /* It was in input mode */ 2722 value = dev->gpio_dir | (1 << pin_number); 2723 dev->gpio_dir = value; 2724 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2725 dev->gpio_val); 2726 value = 0; 2727 } 2728 2729 if (pin_value == 0) 2730 value = dev->gpio_val & (~(1 << pin_number)); 2731 else 2732 value = dev->gpio_val | (1 << pin_number); 2733 2734 /* store the value */ 2735 dev->gpio_val = value; 2736 2737 /* toggle bit0 of GP_IO */ 2738 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2739 2740 return status; 2741} 2742 2743/***************************************************************************** 2744* G P I O I2C related functions * 2745******************************************************************************/ 2746int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2747{ 2748 int status = 0; 2749 2750 /* set SCL to output 1 ; set SDA to output 1 */ 2751 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2752 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2753 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2754 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2755 2756 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2757 if (status < 0) 2758 return -EINVAL; 2759 2760 /* set SCL to output 1; set SDA to output 0 */ 2761 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2762 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2763 2764 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2765 if (status < 0) 2766 return -EINVAL; 2767 2768 /* set SCL to output 0; set SDA to output 0 */ 2769 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2770 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2771 2772 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2773 if (status < 0) 2774 return -EINVAL; 2775 2776 return status; 2777} 2778 2779int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2780{ 2781 int status = 0; 2782 2783 /* set SCL to output 0; set SDA to output 0 */ 2784 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2785 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2786 2787 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2788 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2789 2790 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2791 if (status < 0) 2792 return -EINVAL; 2793 2794 /* set SCL to output 1; set SDA to output 0 */ 2795 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2796 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2797 2798 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2799 if (status < 0) 2800 return -EINVAL; 2801 2802 /* set SCL to input ,release SCL cable control 2803 set SDA to input ,release SDA cable control */ 2804 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2805 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2806 2807 status = 2808 cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2809 if (status < 0) 2810 return -EINVAL; 2811 2812 return status; 2813} 2814 2815int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2816{ 2817 int status = 0; 2818 u8 i; 2819 2820 /* set SCL to output ; set SDA to output */ 2821 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2822 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2823 2824 for (i = 0; i < 8; i++) { 2825 if (((data << i) & 0x80) == 0) { 2826 /* set SCL to output 0; set SDA to output 0 */ 2827 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2828 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2829 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2830 dev->gpio_val); 2831 2832 /* set SCL to output 1; set SDA to output 0 */ 2833 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2834 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2835 dev->gpio_val); 2836 2837 /* set SCL to output 0; set SDA to output 0 */ 2838 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2839 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2840 dev->gpio_val); 2841 } else { 2842 /* set SCL to output 0; set SDA to output 1 */ 2843 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2844 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2845 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2846 dev->gpio_val); 2847 2848 /* set SCL to output 1; set SDA to output 1 */ 2849 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2850 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2851 dev->gpio_val); 2852 2853 /* set SCL to output 0; set SDA to output 1 */ 2854 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2855 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2856 dev->gpio_val); 2857 } 2858 } 2859 return status; 2860} 2861 2862int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2863{ 2864 u8 value = 0; 2865 int status = 0; 2866 u32 gpio_logic_value = 0; 2867 u8 i; 2868 2869 /* read byte */ 2870 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2871 2872 /* set SCL to output 0; set SDA to input */ 2873 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2875 dev->gpio_val); 2876 2877 /* set SCL to output 1; set SDA to input */ 2878 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2879 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2880 dev->gpio_val); 2881 2882 /* get SDA data bit */ 2883 gpio_logic_value = dev->gpio_val; 2884 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2885 &dev->gpio_val); 2886 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2887 value |= (1 << (8 - i - 1)); 2888 2889 dev->gpio_val = gpio_logic_value; 2890 } 2891 2892 /* set SCL to output 0,finish the read latest SCL signal. 2893 !!!set SDA to input, never to modify SDA direction at 2894 the same times */ 2895 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2896 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2897 2898 /* store the value */ 2899 *buf = value & 0xff; 2900 2901 return status; 2902} 2903 2904int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2905{ 2906 int status = 0; 2907 u32 gpio_logic_value = 0; 2908 int nCnt = 10; 2909 int nInit = nCnt; 2910 2911 /* clock stretch; set SCL to input; set SDA to input; 2912 get SCL value till SCL = 1 */ 2913 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2914 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2915 2916 gpio_logic_value = dev->gpio_val; 2917 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2918 2919 do { 2920 msleep(2); 2921 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2922 &dev->gpio_val); 2923 nCnt--; 2924 } while (((dev->gpio_val & 2925 (1 << dev->board.tuner_scl_gpio)) == 0) && 2926 (nCnt > 0)); 2927 2928 if (nCnt == 0) 2929 cx231xx_info("No ACK after %d msec -GPIO I2C failed!", 2930 nInit * 10); 2931 2932 /* 2933 * readAck 2934 * through clock stretch, slave has given a SCL signal, 2935 * so the SDA data can be directly read. 2936 */ 2937 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, &dev->gpio_val); 2938 2939 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2940 dev->gpio_val = gpio_logic_value; 2941 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2942 status = 0; 2943 } else { 2944 dev->gpio_val = gpio_logic_value; 2945 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2946 } 2947 2948 /* read SDA end, set the SCL to output 0, after this operation, 2949 SDA direction can be changed. */ 2950 dev->gpio_val = gpio_logic_value; 2951 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2952 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2953 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2954 2955 return status; 2956} 2957 2958int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2959{ 2960 int status = 0; 2961 2962 /* set SDA to ouput */ 2963 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2964 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2965 2966 /* set SCL = 0 (output); set SDA = 0 (output) */ 2967 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2968 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2969 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2970 2971 /* set SCL = 1 (output); set SDA = 0 (output) */ 2972 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2973 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2974 2975 /* set SCL = 0 (output); set SDA = 0 (output) */ 2976 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2977 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2978 2979 /* set SDA to input,and then the slave will read data from SDA. */ 2980 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2981 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2982 2983 return status; 2984} 2985 2986int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 2987{ 2988 int status = 0; 2989 2990 /* set scl to output ; set sda to input */ 2991 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2992 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2993 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2994 2995 /* set scl to output 0; set sda to input */ 2996 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2997 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 2998 2999 /* set scl to output 1; set sda to input */ 3000 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 3001 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, dev->gpio_val); 3002 3003 return status; 3004} 3005 3006/***************************************************************************** 3007* G P I O I2C related functions * 3008******************************************************************************/ 3009/* cx231xx_gpio_i2c_read 3010 * Function to read data from gpio based I2C interface 3011 */ 3012int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3013{ 3014 int status = 0; 3015 int i = 0; 3016 3017 /* get the lock */ 3018 mutex_lock(&dev->gpio_i2c_lock); 3019 3020 /* start */ 3021 status = cx231xx_gpio_i2c_start(dev); 3022 3023 /* write dev_addr */ 3024 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3025 3026 /* readAck */ 3027 status = cx231xx_gpio_i2c_read_ack(dev); 3028 3029 /* read data */ 3030 for (i = 0; i < len; i++) { 3031 /* read data */ 3032 buf[i] = 0; 3033 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3034 3035 if ((i + 1) != len) { 3036 /* only do write ack if we more length */ 3037 status = cx231xx_gpio_i2c_write_ack(dev); 3038 } 3039 } 3040 3041 /* write NAK - inform reads are complete */ 3042 status = cx231xx_gpio_i2c_write_nak(dev); 3043 3044 /* write end */ 3045 status = cx231xx_gpio_i2c_end(dev); 3046 3047 /* release the lock */ 3048 mutex_unlock(&dev->gpio_i2c_lock); 3049 3050 return status; 3051} 3052 3053/* cx231xx_gpio_i2c_write 3054 * Function to write data to gpio based I2C interface 3055 */ 3056int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3057{ 3058 int i = 0; 3059 3060 /* get the lock */ 3061 mutex_lock(&dev->gpio_i2c_lock); 3062 3063 /* start */ 3064 cx231xx_gpio_i2c_start(dev); 3065 3066 /* write dev_addr */ 3067 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3068 3069 /* read Ack */ 3070 cx231xx_gpio_i2c_read_ack(dev); 3071 3072 for (i = 0; i < len; i++) { 3073 /* Write data */ 3074 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3075 3076 /* read Ack */ 3077 cx231xx_gpio_i2c_read_ack(dev); 3078 } 3079 3080 /* write End */ 3081 cx231xx_gpio_i2c_end(dev); 3082 3083 /* release the lock */ 3084 mutex_unlock(&dev->gpio_i2c_lock); 3085 3086 return 0; 3087} 3088