rtl8411.c revision 56cb3cc1872923b69fdeeb00362b7da4d6cf5590
1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG <wei_wang@realsil.com.cn> 20 * Roger Tseng <rogerable@realtek.com> 21 */ 22 23#include <linux/module.h> 24#include <linux/bitops.h> 25#include <linux/delay.h> 26#include <linux/mfd/rtsx_pci.h> 27 28#include "rtsx_pcr.h" 29 30static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr) 31{ 32 u8 val; 33 34 rtsx_pci_read_register(pcr, SYS_VER, &val); 35 return val & 0x0F; 36} 37 38static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr) 39{ 40 u8 val = 0; 41 42 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val); 43 44 if (val & 0x2) 45 return 1; 46 else 47 return 0; 48} 49 50static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr) 51{ 52 u32 reg1 = 0; 53 u8 reg3 = 0; 54 55 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); 56 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); 57 58 if (!rtsx_vendor_setting_valid(reg1)) 59 return; 60 61 pcr->aspm_en = rtsx_reg_to_aspm(reg1); 62 pcr->sd30_drive_sel_1v8 = 63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); 64 pcr->card_drive_sel &= 0x3F; 65 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); 66 67 rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3); 68 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); 69 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3); 70} 71 72static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr) 73{ 74 u32 reg = 0; 75 76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 77 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 78 79 if (!rtsx_vendor_setting_valid(reg)) 80 return; 81 82 pcr->aspm_en = rtsx_reg_to_aspm(reg); 83 pcr->sd30_drive_sel_1v8 = 84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); 85 pcr->sd30_drive_sel_3v3 = 86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); 87} 88 89static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 90{ 91 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07); 92} 93 94static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr) 95{ 96 rtsx_pci_init_cmd(pcr); 97 98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 99 0xFF, pcr->sd30_drive_sel_3v3); 100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 101 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 102 103 return rtsx_pci_send_cmd(pcr, 100); 104} 105 106static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr) 107{ 108 rtsx_pci_init_cmd(pcr); 109 110 if (rtl8411b_is_qfn48(pcr)) 111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 112 CARD_PULL_CTL3, 0xFF, 0xF5); 113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 114 0xFF, pcr->sd30_drive_sel_3v3); 115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 116 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL, 118 0x06, 0x00); 119 120 return rtsx_pci_send_cmd(pcr, 100); 121} 122 123static int rtl8411_turn_on_led(struct rtsx_pcr *pcr) 124{ 125 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00); 126} 127 128static int rtl8411_turn_off_led(struct rtsx_pcr *pcr) 129{ 130 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01); 131} 132 133static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr) 134{ 135 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D); 136} 137 138static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr) 139{ 140 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00); 141} 142 143static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card) 144{ 145 int err; 146 147 rtsx_pci_init_cmd(pcr); 148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 149 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 150 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL, 151 BPP_LDO_POWB, BPP_LDO_SUSPEND); 152 err = rtsx_pci_send_cmd(pcr, 100); 153 if (err < 0) 154 return err; 155 156 /* To avoid too large in-rush current */ 157 udelay(150); 158 159 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 160 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON); 161 if (err < 0) 162 return err; 163 164 udelay(150); 165 166 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 167 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON); 168 if (err < 0) 169 return err; 170 171 udelay(150); 172 173 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 174 BPP_POWER_MASK, BPP_POWER_ON); 175 if (err < 0) 176 return err; 177 178 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON); 179} 180 181static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card) 182{ 183 int err; 184 185 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 186 BPP_POWER_MASK, BPP_POWER_OFF); 187 if (err < 0) 188 return err; 189 190 return rtsx_pci_write_register(pcr, LDO_CTL, 191 BPP_LDO_POWB, BPP_LDO_SUSPEND); 192} 193 194static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage, 195 int bpp_tuned18_shift, int bpp_asic_1v8) 196{ 197 u8 mask, val; 198 int err; 199 200 mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK; 201 if (voltage == OUTPUT_3V3) { 202 err = rtsx_pci_write_register(pcr, 203 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); 204 if (err < 0) 205 return err; 206 val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3; 207 } else if (voltage == OUTPUT_1V8) { 208 err = rtsx_pci_write_register(pcr, 209 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); 210 if (err < 0) 211 return err; 212 val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8; 213 } else { 214 return -EINVAL; 215 } 216 217 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); 218} 219 220static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 221{ 222 return rtl8411_do_switch_output_voltage(pcr, voltage, 223 BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8); 224} 225 226static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 227{ 228 return rtl8411_do_switch_output_voltage(pcr, voltage, 229 BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0); 230} 231 232static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr) 233{ 234 unsigned int card_exist; 235 236 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 237 card_exist &= CARD_EXIST; 238 if (!card_exist) { 239 /* Enable card CD */ 240 rtsx_pci_write_register(pcr, CD_PAD_CTL, 241 CD_DISABLE_MASK, CD_ENABLE); 242 /* Enable card interrupt */ 243 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00); 244 return 0; 245 } 246 247 if (hweight32(card_exist) > 1) { 248 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 249 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 250 msleep(100); 251 252 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 253 if (card_exist & MS_EXIST) 254 card_exist = MS_EXIST; 255 else if (card_exist & SD_EXIST) 256 card_exist = SD_EXIST; 257 else 258 card_exist = 0; 259 260 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 261 BPP_POWER_MASK, BPP_POWER_OFF); 262 263 dev_dbg(&(pcr->pci->dev), 264 "After CD deglitch, card_exist = 0x%x\n", 265 card_exist); 266 } 267 268 if (card_exist & MS_EXIST) { 269 /* Disable SD interrupt */ 270 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40); 271 rtsx_pci_write_register(pcr, CD_PAD_CTL, 272 CD_DISABLE_MASK, MS_CD_EN_ONLY); 273 } else if (card_exist & SD_EXIST) { 274 /* Disable MS interrupt */ 275 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80); 276 rtsx_pci_write_register(pcr, CD_PAD_CTL, 277 CD_DISABLE_MASK, SD_CD_EN_ONLY); 278 } 279 280 return card_exist; 281} 282 283static int rtl8411_conv_clk_and_div_n(int input, int dir) 284{ 285 int output; 286 287 if (dir == CLK_TO_DIV_N) 288 output = input * 4 / 5 - 2; 289 else 290 output = (input + 2) * 5 / 4; 291 292 return output; 293} 294 295static const struct pcr_ops rtl8411_pcr_ops = { 296 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 297 .extra_init_hw = rtl8411_extra_init_hw, 298 .optimize_phy = NULL, 299 .turn_on_led = rtl8411_turn_on_led, 300 .turn_off_led = rtl8411_turn_off_led, 301 .enable_auto_blink = rtl8411_enable_auto_blink, 302 .disable_auto_blink = rtl8411_disable_auto_blink, 303 .card_power_on = rtl8411_card_power_on, 304 .card_power_off = rtl8411_card_power_off, 305 .switch_output_voltage = rtl8411_switch_output_voltage, 306 .cd_deglitch = rtl8411_cd_deglitch, 307 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 308 .force_power_down = rtl8411_force_power_down, 309}; 310 311static const struct pcr_ops rtl8402_pcr_ops = { 312 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 313 .extra_init_hw = rtl8411_extra_init_hw, 314 .optimize_phy = NULL, 315 .turn_on_led = rtl8411_turn_on_led, 316 .turn_off_led = rtl8411_turn_off_led, 317 .enable_auto_blink = rtl8411_enable_auto_blink, 318 .disable_auto_blink = rtl8411_disable_auto_blink, 319 .card_power_on = rtl8411_card_power_on, 320 .card_power_off = rtl8411_card_power_off, 321 .switch_output_voltage = rtl8402_switch_output_voltage, 322 .cd_deglitch = rtl8411_cd_deglitch, 323 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 324 .force_power_down = rtl8411_force_power_down, 325}; 326 327static const struct pcr_ops rtl8411b_pcr_ops = { 328 .fetch_vendor_settings = rtl8411b_fetch_vendor_settings, 329 .extra_init_hw = rtl8411b_extra_init_hw, 330 .optimize_phy = NULL, 331 .turn_on_led = rtl8411_turn_on_led, 332 .turn_off_led = rtl8411_turn_off_led, 333 .enable_auto_blink = rtl8411_enable_auto_blink, 334 .disable_auto_blink = rtl8411_disable_auto_blink, 335 .card_power_on = rtl8411_card_power_on, 336 .card_power_off = rtl8411_card_power_off, 337 .switch_output_voltage = rtl8411_switch_output_voltage, 338 .cd_deglitch = rtl8411_cd_deglitch, 339 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 340 .force_power_down = rtl8411_force_power_down, 341}; 342 343/* SD Pull Control Enable: 344 * SD_DAT[3:0] ==> pull up 345 * SD_CD ==> pull up 346 * SD_WP ==> pull up 347 * SD_CMD ==> pull up 348 * SD_CLK ==> pull down 349 */ 350static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = { 351 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 352 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 353 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9), 354 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 355 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09), 356 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 357 0, 358}; 359 360/* SD Pull Control Disable: 361 * SD_DAT[3:0] ==> pull down 362 * SD_CD ==> pull up 363 * SD_WP ==> pull down 364 * SD_CMD ==> pull down 365 * SD_CLK ==> pull down 366 */ 367static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = { 368 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 369 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 370 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 371 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 372 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 373 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 374 0, 375}; 376 377/* MS Pull Control Enable: 378 * MS CD ==> pull up 379 * others ==> pull down 380 */ 381static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = { 382 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 383 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 384 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 385 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05), 386 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 387 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 388 0, 389}; 390 391/* MS Pull Control Disable: 392 * MS CD ==> pull up 393 * others ==> pull down 394 */ 395static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = { 396 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 397 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 398 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 399 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 400 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 401 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 402 0, 403}; 404 405static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = { 406 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 407 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 408 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0), 409 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 410 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 411 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 412 0, 413}; 414 415static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = { 416 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 417 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90), 418 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11), 419 0, 420}; 421 422static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = { 423 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 424 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 425 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 426 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 427 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 428 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 429 0, 430}; 431 432static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = { 433 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 434 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 435 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 436 0, 437}; 438 439static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = { 440 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 441 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 442 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 443 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50), 444 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 445 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 446 0, 447}; 448 449static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = { 450 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 451 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 452 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 453 0, 454}; 455 456static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = { 457 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 458 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 459 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 460 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 461 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 462 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 463 0, 464}; 465 466static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = { 467 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 468 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 469 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 470 0, 471}; 472 473void rtl8411_init_common_params(struct rtsx_pcr *pcr) 474{ 475 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 476 pcr->num_slots = 2; 477 pcr->flags = 0; 478 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 479 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 480 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 481 pcr->aspm_en = ASPM_L1_EN; 482 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14); 483 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10); 484 pcr->ic_version = rtl8411_get_ic_version(pcr); 485} 486 487void rtl8411_init_params(struct rtsx_pcr *pcr) 488{ 489 rtl8411_init_common_params(pcr); 490 pcr->ops = &rtl8411_pcr_ops; 491 set_pull_ctrl_tables(pcr, rtl8411); 492} 493 494void rtl8411b_init_params(struct rtsx_pcr *pcr) 495{ 496 rtl8411_init_common_params(pcr); 497 pcr->ops = &rtl8411b_pcr_ops; 498 if (rtl8411b_is_qfn48(pcr)) 499 set_pull_ctrl_tables(pcr, rtl8411b_qfn48); 500 else 501 set_pull_ctrl_tables(pcr, rtl8411b_qfn64); 502} 503 504void rtl8402_init_params(struct rtsx_pcr *pcr) 505{ 506 rtl8411_init_common_params(pcr); 507 pcr->ops = &rtl8402_pcr_ops; 508 set_pull_ctrl_tables(pcr, rtl8411); 509} 510