rtl8411.c revision 5947c167d145f32d4475d647a87e2af2699efe45
1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG <wei_wang@realsil.com.cn> 20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 21 */ 22 23#include <linux/module.h> 24#include <linux/bitops.h> 25#include <linux/delay.h> 26#include <linux/mfd/rtsx_pci.h> 27 28#include "rtsx_pcr.h" 29 30static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr) 31{ 32 u8 val; 33 34 rtsx_pci_read_register(pcr, SYS_VER, &val); 35 return val & 0x0F; 36} 37 38static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr) 39{ 40 u8 val = 0; 41 42 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val); 43 44 if (val & 0x2) 45 return 1; 46 else 47 return 0; 48} 49 50static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr) 51{ 52 u32 reg1; 53 u8 reg3; 54 55 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); 56 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); 57 58 if (!rtsx_vendor_setting_valid(reg1)) 59 return; 60 61 pcr->aspm_en = rtsx_reg_to_aspm(reg1); 62 pcr->sd30_drive_sel_1v8 = 63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); 64 pcr->card_drive_sel &= 0x3F; 65 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); 66 67 rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3); 68 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); 69 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3); 70} 71 72static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr) 73{ 74 u32 reg; 75 76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 77 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 78 79 if (!rtsx_vendor_setting_valid(reg)) 80 return; 81 82 pcr->aspm_en = rtsx_reg_to_aspm(reg); 83 pcr->sd30_drive_sel_1v8 = 84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); 85 pcr->sd30_drive_sel_3v3 = 86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); 87} 88 89static void rtl8411_force_power_down(struct rtsx_pcr *pcr) 90{ 91 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07); 92} 93 94static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr) 95{ 96 rtsx_pci_init_cmd(pcr); 97 98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 99 0xFF, pcr->sd30_drive_sel_3v3); 100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 101 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 102 103 return rtsx_pci_send_cmd(pcr, 100); 104} 105 106static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr) 107{ 108 rtsx_pci_init_cmd(pcr); 109 110 if (rtl8411b_is_qfn48(pcr)) 111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 112 CARD_PULL_CTL3, 0xFF, 0xF5); 113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 114 0xFF, pcr->sd30_drive_sel_3v3); 115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 116 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 117 118 return rtsx_pci_send_cmd(pcr, 100); 119} 120 121static int rtl8411_turn_on_led(struct rtsx_pcr *pcr) 122{ 123 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00); 124} 125 126static int rtl8411_turn_off_led(struct rtsx_pcr *pcr) 127{ 128 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01); 129} 130 131static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr) 132{ 133 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D); 134} 135 136static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr) 137{ 138 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00); 139} 140 141static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card) 142{ 143 int err; 144 145 rtsx_pci_init_cmd(pcr); 146 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 147 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL, 149 BPP_LDO_POWB, BPP_LDO_SUSPEND); 150 err = rtsx_pci_send_cmd(pcr, 100); 151 if (err < 0) 152 return err; 153 154 /* To avoid too large in-rush current */ 155 udelay(150); 156 157 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 158 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON); 159 if (err < 0) 160 return err; 161 162 udelay(150); 163 164 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 165 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON); 166 if (err < 0) 167 return err; 168 169 udelay(150); 170 171 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 172 BPP_POWER_MASK, BPP_POWER_ON); 173 if (err < 0) 174 return err; 175 176 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON); 177} 178 179static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card) 180{ 181 int err; 182 183 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 184 BPP_POWER_MASK, BPP_POWER_OFF); 185 if (err < 0) 186 return err; 187 188 return rtsx_pci_write_register(pcr, LDO_CTL, 189 BPP_LDO_POWB, BPP_LDO_SUSPEND); 190} 191 192static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 193{ 194 u8 mask, val; 195 int err; 196 197 mask = (BPP_REG_TUNED18 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_MASK; 198 if (voltage == OUTPUT_3V3) { 199 err = rtsx_pci_write_register(pcr, 200 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); 201 if (err < 0) 202 return err; 203 val = (BPP_ASIC_3V3 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_3V3; 204 } else if (voltage == OUTPUT_1V8) { 205 err = rtsx_pci_write_register(pcr, 206 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); 207 if (err < 0) 208 return err; 209 val = (BPP_ASIC_1V8 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_1V8; 210 } else { 211 return -EINVAL; 212 } 213 214 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); 215} 216 217static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr) 218{ 219 unsigned int card_exist; 220 221 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 222 card_exist &= CARD_EXIST; 223 if (!card_exist) { 224 /* Enable card CD */ 225 rtsx_pci_write_register(pcr, CD_PAD_CTL, 226 CD_DISABLE_MASK, CD_ENABLE); 227 /* Enable card interrupt */ 228 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00); 229 return 0; 230 } 231 232 if (hweight32(card_exist) > 1) { 233 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 234 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 235 msleep(100); 236 237 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 238 if (card_exist & MS_EXIST) 239 card_exist = MS_EXIST; 240 else if (card_exist & SD_EXIST) 241 card_exist = SD_EXIST; 242 else 243 card_exist = 0; 244 245 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 246 BPP_POWER_MASK, BPP_POWER_OFF); 247 248 dev_dbg(&(pcr->pci->dev), 249 "After CD deglitch, card_exist = 0x%x\n", 250 card_exist); 251 } 252 253 if (card_exist & MS_EXIST) { 254 /* Disable SD interrupt */ 255 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40); 256 rtsx_pci_write_register(pcr, CD_PAD_CTL, 257 CD_DISABLE_MASK, MS_CD_EN_ONLY); 258 } else if (card_exist & SD_EXIST) { 259 /* Disable MS interrupt */ 260 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80); 261 rtsx_pci_write_register(pcr, CD_PAD_CTL, 262 CD_DISABLE_MASK, SD_CD_EN_ONLY); 263 } 264 265 return card_exist; 266} 267 268static int rtl8411_conv_clk_and_div_n(int input, int dir) 269{ 270 int output; 271 272 if (dir == CLK_TO_DIV_N) 273 output = input * 4 / 5 - 2; 274 else 275 output = (input + 2) * 5 / 4; 276 277 return output; 278} 279 280static const struct pcr_ops rtl8411_pcr_ops = { 281 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 282 .extra_init_hw = rtl8411_extra_init_hw, 283 .optimize_phy = NULL, 284 .turn_on_led = rtl8411_turn_on_led, 285 .turn_off_led = rtl8411_turn_off_led, 286 .enable_auto_blink = rtl8411_enable_auto_blink, 287 .disable_auto_blink = rtl8411_disable_auto_blink, 288 .card_power_on = rtl8411_card_power_on, 289 .card_power_off = rtl8411_card_power_off, 290 .switch_output_voltage = rtl8411_switch_output_voltage, 291 .cd_deglitch = rtl8411_cd_deglitch, 292 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 293 .force_power_down = rtl8411_force_power_down, 294}; 295 296static const struct pcr_ops rtl8411b_pcr_ops = { 297 .fetch_vendor_settings = rtl8411b_fetch_vendor_settings, 298 .extra_init_hw = rtl8411b_extra_init_hw, 299 .optimize_phy = NULL, 300 .turn_on_led = rtl8411_turn_on_led, 301 .turn_off_led = rtl8411_turn_off_led, 302 .enable_auto_blink = rtl8411_enable_auto_blink, 303 .disable_auto_blink = rtl8411_disable_auto_blink, 304 .card_power_on = rtl8411_card_power_on, 305 .card_power_off = rtl8411_card_power_off, 306 .switch_output_voltage = rtl8411_switch_output_voltage, 307 .cd_deglitch = rtl8411_cd_deglitch, 308 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 309 .force_power_down = rtl8411_force_power_down, 310}; 311 312/* SD Pull Control Enable: 313 * SD_DAT[3:0] ==> pull up 314 * SD_CD ==> pull up 315 * SD_WP ==> pull up 316 * SD_CMD ==> pull up 317 * SD_CLK ==> pull down 318 */ 319static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = { 320 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 321 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 322 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9), 323 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 324 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09), 325 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 326 0, 327}; 328 329/* SD Pull Control Disable: 330 * SD_DAT[3:0] ==> pull down 331 * SD_CD ==> pull up 332 * SD_WP ==> pull down 333 * SD_CMD ==> pull down 334 * SD_CLK ==> pull down 335 */ 336static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = { 337 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 338 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 339 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 340 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 341 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 342 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 343 0, 344}; 345 346/* MS Pull Control Enable: 347 * MS CD ==> pull up 348 * others ==> pull down 349 */ 350static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = { 351 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 352 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 353 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 354 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05), 355 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 356 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 357 0, 358}; 359 360/* MS Pull Control Disable: 361 * MS CD ==> pull up 362 * others ==> pull down 363 */ 364static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = { 365 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 366 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 367 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 368 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 369 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 370 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 371 0, 372}; 373 374static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = { 375 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 376 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 377 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0), 378 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 379 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 380 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 381 0, 382}; 383 384static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = { 385 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 386 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90), 387 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11), 388 0, 389}; 390 391static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = { 392 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 393 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 394 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 395 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 396 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 397 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 398 0, 399}; 400 401static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = { 402 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 403 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 404 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 405 0, 406}; 407 408static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = { 409 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 410 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 411 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 412 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50), 413 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 414 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 415 0, 416}; 417 418static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = { 419 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 420 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 421 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 422 0, 423}; 424 425static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = { 426 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 427 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 428 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 429 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 430 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 431 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 432 0, 433}; 434 435static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = { 436 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 437 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 438 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 439 0, 440}; 441 442void rtl8411_init_params(struct rtsx_pcr *pcr) 443{ 444 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 445 pcr->num_slots = 2; 446 pcr->ops = &rtl8411_pcr_ops; 447 448 pcr->flags = 0; 449 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 450 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 451 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 452 pcr->aspm_en = ASPM_L1_EN; 453 454 pcr->ic_version = rtl8411_get_ic_version(pcr); 455 pcr->sd_pull_ctl_enable_tbl = rtl8411_sd_pull_ctl_enable_tbl; 456 pcr->sd_pull_ctl_disable_tbl = rtl8411_sd_pull_ctl_disable_tbl; 457 pcr->ms_pull_ctl_enable_tbl = rtl8411_ms_pull_ctl_enable_tbl; 458 pcr->ms_pull_ctl_disable_tbl = rtl8411_ms_pull_ctl_disable_tbl; 459} 460 461void rtl8411b_init_params(struct rtsx_pcr *pcr) 462{ 463 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 464 pcr->num_slots = 2; 465 pcr->ops = &rtl8411b_pcr_ops; 466 467 pcr->flags = 0; 468 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 469 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 470 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 471 pcr->aspm_en = ASPM_L1_EN; 472 473 pcr->ic_version = rtl8411_get_ic_version(pcr); 474 475 if (rtl8411b_is_qfn48(pcr)) { 476 pcr->sd_pull_ctl_enable_tbl = 477 rtl8411b_qfn48_sd_pull_ctl_enable_tbl; 478 pcr->sd_pull_ctl_disable_tbl = 479 rtl8411b_qfn48_sd_pull_ctl_disable_tbl; 480 pcr->ms_pull_ctl_enable_tbl = 481 rtl8411b_qfn48_ms_pull_ctl_enable_tbl; 482 pcr->ms_pull_ctl_disable_tbl = 483 rtl8411b_qfn48_ms_pull_ctl_disable_tbl; 484 } else { 485 pcr->sd_pull_ctl_enable_tbl = 486 rtl8411b_qfn64_sd_pull_ctl_enable_tbl; 487 pcr->sd_pull_ctl_disable_tbl = 488 rtl8411b_qfn64_sd_pull_ctl_disable_tbl; 489 pcr->ms_pull_ctl_enable_tbl = 490 rtl8411b_qfn64_ms_pull_ctl_enable_tbl; 491 pcr->ms_pull_ctl_disable_tbl = 492 rtl8411b_qfn64_ms_pull_ctl_disable_tbl; 493 } 494} 495