rtl8411.c revision 773ccdfd9cc6f9bf8ec75a59fa742d7a663a5903
1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG <wei_wang@realsil.com.cn> 20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 21 */ 22 23#include <linux/module.h> 24#include <linux/bitops.h> 25#include <linux/delay.h> 26#include <linux/mfd/rtsx_pci.h> 27 28#include "rtsx_pcr.h" 29 30static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr) 31{ 32 u8 val; 33 34 rtsx_pci_read_register(pcr, SYS_VER, &val); 35 return val & 0x0F; 36} 37 38static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr) 39{ 40 u8 val = 0; 41 42 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val); 43 44 if (val & 0x2) 45 return 1; 46 else 47 return 0; 48} 49 50static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr) 51{ 52 u32 reg1; 53 u8 reg3; 54 55 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); 56 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); 57 58 if (!rtsx_vendor_setting_valid(reg1)) 59 return; 60 61 pcr->aspm_en = rtsx_reg_to_aspm(reg1); 62 pcr->sd30_drive_sel_1v8 = 63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); 64 pcr->card_drive_sel &= 0x3F; 65 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); 66 67 rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3); 68 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3); 69 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3); 70} 71 72static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr) 73{ 74 u32 reg; 75 76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 77 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 78 79 if (!rtsx_vendor_setting_valid(reg)) 80 return; 81 82 pcr->aspm_en = rtsx_reg_to_aspm(reg); 83 pcr->sd30_drive_sel_1v8 = 84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); 85 pcr->sd30_drive_sel_3v3 = 86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg)); 87} 88 89static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr) 90{ 91 rtsx_pci_init_cmd(pcr); 92 93 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 94 0xFF, pcr->sd30_drive_sel_3v3); 95 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 96 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 97 98 return rtsx_pci_send_cmd(pcr, 100); 99} 100 101static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr) 102{ 103 rtsx_pci_init_cmd(pcr); 104 105 if (rtl8411b_is_qfn48(pcr)) 106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 107 CARD_PULL_CTL3, 0xFF, 0xF5); 108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 109 0xFF, pcr->sd30_drive_sel_3v3); 110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL, 111 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE); 112 113 return rtsx_pci_send_cmd(pcr, 100); 114} 115 116static int rtl8411_turn_on_led(struct rtsx_pcr *pcr) 117{ 118 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00); 119} 120 121static int rtl8411_turn_off_led(struct rtsx_pcr *pcr) 122{ 123 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01); 124} 125 126static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr) 127{ 128 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D); 129} 130 131static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr) 132{ 133 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00); 134} 135 136static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card) 137{ 138 int err; 139 140 rtsx_pci_init_cmd(pcr); 141 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 142 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 143 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL, 144 BPP_LDO_POWB, BPP_LDO_SUSPEND); 145 err = rtsx_pci_send_cmd(pcr, 100); 146 if (err < 0) 147 return err; 148 149 /* To avoid too large in-rush current */ 150 udelay(150); 151 152 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 153 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON); 154 if (err < 0) 155 return err; 156 157 udelay(150); 158 159 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 160 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON); 161 if (err < 0) 162 return err; 163 164 udelay(150); 165 166 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 167 BPP_POWER_MASK, BPP_POWER_ON); 168 if (err < 0) 169 return err; 170 171 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON); 172} 173 174static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card) 175{ 176 int err; 177 178 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL, 179 BPP_POWER_MASK, BPP_POWER_OFF); 180 if (err < 0) 181 return err; 182 183 return rtsx_pci_write_register(pcr, LDO_CTL, 184 BPP_LDO_POWB, BPP_LDO_SUSPEND); 185} 186 187static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 188{ 189 u8 mask, val; 190 int err; 191 192 mask = (BPP_REG_TUNED18 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_MASK; 193 if (voltage == OUTPUT_3V3) { 194 err = rtsx_pci_write_register(pcr, 195 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); 196 if (err < 0) 197 return err; 198 val = (BPP_ASIC_3V3 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_3V3; 199 } else if (voltage == OUTPUT_1V8) { 200 err = rtsx_pci_write_register(pcr, 201 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); 202 if (err < 0) 203 return err; 204 val = (BPP_ASIC_1V8 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_1V8; 205 } else { 206 return -EINVAL; 207 } 208 209 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val); 210} 211 212static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr) 213{ 214 unsigned int card_exist; 215 216 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 217 card_exist &= CARD_EXIST; 218 if (!card_exist) { 219 /* Enable card CD */ 220 rtsx_pci_write_register(pcr, CD_PAD_CTL, 221 CD_DISABLE_MASK, CD_ENABLE); 222 /* Enable card interrupt */ 223 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00); 224 return 0; 225 } 226 227 if (hweight32(card_exist) > 1) { 228 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 229 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON); 230 msleep(100); 231 232 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR); 233 if (card_exist & MS_EXIST) 234 card_exist = MS_EXIST; 235 else if (card_exist & SD_EXIST) 236 card_exist = SD_EXIST; 237 else 238 card_exist = 0; 239 240 rtsx_pci_write_register(pcr, CARD_PWR_CTL, 241 BPP_POWER_MASK, BPP_POWER_OFF); 242 243 dev_dbg(&(pcr->pci->dev), 244 "After CD deglitch, card_exist = 0x%x\n", 245 card_exist); 246 } 247 248 if (card_exist & MS_EXIST) { 249 /* Disable SD interrupt */ 250 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40); 251 rtsx_pci_write_register(pcr, CD_PAD_CTL, 252 CD_DISABLE_MASK, MS_CD_EN_ONLY); 253 } else if (card_exist & SD_EXIST) { 254 /* Disable MS interrupt */ 255 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80); 256 rtsx_pci_write_register(pcr, CD_PAD_CTL, 257 CD_DISABLE_MASK, SD_CD_EN_ONLY); 258 } 259 260 return card_exist; 261} 262 263static int rtl8411_conv_clk_and_div_n(int input, int dir) 264{ 265 int output; 266 267 if (dir == CLK_TO_DIV_N) 268 output = input * 4 / 5 - 2; 269 else 270 output = (input + 2) * 5 / 4; 271 272 return output; 273} 274 275static const struct pcr_ops rtl8411_pcr_ops = { 276 .fetch_vendor_settings = rtl8411_fetch_vendor_settings, 277 .extra_init_hw = rtl8411_extra_init_hw, 278 .optimize_phy = NULL, 279 .turn_on_led = rtl8411_turn_on_led, 280 .turn_off_led = rtl8411_turn_off_led, 281 .enable_auto_blink = rtl8411_enable_auto_blink, 282 .disable_auto_blink = rtl8411_disable_auto_blink, 283 .card_power_on = rtl8411_card_power_on, 284 .card_power_off = rtl8411_card_power_off, 285 .switch_output_voltage = rtl8411_switch_output_voltage, 286 .cd_deglitch = rtl8411_cd_deglitch, 287 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 288}; 289 290static const struct pcr_ops rtl8411b_pcr_ops = { 291 .fetch_vendor_settings = rtl8411b_fetch_vendor_settings, 292 .extra_init_hw = rtl8411b_extra_init_hw, 293 .optimize_phy = NULL, 294 .turn_on_led = rtl8411_turn_on_led, 295 .turn_off_led = rtl8411_turn_off_led, 296 .enable_auto_blink = rtl8411_enable_auto_blink, 297 .disable_auto_blink = rtl8411_disable_auto_blink, 298 .card_power_on = rtl8411_card_power_on, 299 .card_power_off = rtl8411_card_power_off, 300 .switch_output_voltage = rtl8411_switch_output_voltage, 301 .cd_deglitch = rtl8411_cd_deglitch, 302 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n, 303}; 304 305/* SD Pull Control Enable: 306 * SD_DAT[3:0] ==> pull up 307 * SD_CD ==> pull up 308 * SD_WP ==> pull up 309 * SD_CMD ==> pull up 310 * SD_CLK ==> pull down 311 */ 312static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = { 313 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 314 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 315 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9), 316 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 317 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09), 318 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 319 0, 320}; 321 322/* SD Pull Control Disable: 323 * SD_DAT[3:0] ==> pull down 324 * SD_CD ==> pull up 325 * SD_WP ==> pull down 326 * SD_CMD ==> pull down 327 * SD_CLK ==> pull down 328 */ 329static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = { 330 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 331 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 332 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 333 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 334 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 335 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 336 0, 337}; 338 339/* MS Pull Control Enable: 340 * MS CD ==> pull up 341 * others ==> pull down 342 */ 343static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = { 344 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 345 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 346 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 347 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05), 348 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 349 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 350 0, 351}; 352 353/* MS Pull Control Disable: 354 * MS CD ==> pull up 355 * others ==> pull down 356 */ 357static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = { 358 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 359 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 360 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95), 361 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09), 362 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05), 363 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04), 364 0, 365}; 366 367static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = { 368 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA), 369 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 370 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0), 371 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 372 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 373 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 374 0, 375}; 376 377static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = { 378 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 379 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90), 380 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11), 381 0, 382}; 383 384static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = { 385 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 386 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 387 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 388 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 389 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 390 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 391 0, 392}; 393 394static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = { 395 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 396 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 397 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 398 0, 399}; 400 401static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = { 402 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 403 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 404 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 405 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50), 406 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 407 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 408 0, 409}; 410 411static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = { 412 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 413 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 414 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 415 0, 416}; 417 418static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = { 419 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65), 420 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 421 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0), 422 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50), 423 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50), 424 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 425 0, 426}; 427 428static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = { 429 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 430 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90), 431 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11), 432 0, 433}; 434 435void rtl8411_init_params(struct rtsx_pcr *pcr) 436{ 437 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 438 pcr->num_slots = 2; 439 pcr->ops = &rtl8411_pcr_ops; 440 441 pcr->flags = 0; 442 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 443 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 444 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 445 pcr->aspm_en = ASPM_L1_EN; 446 447 pcr->ic_version = rtl8411_get_ic_version(pcr); 448 pcr->sd_pull_ctl_enable_tbl = rtl8411_sd_pull_ctl_enable_tbl; 449 pcr->sd_pull_ctl_disable_tbl = rtl8411_sd_pull_ctl_disable_tbl; 450 pcr->ms_pull_ctl_enable_tbl = rtl8411_ms_pull_ctl_enable_tbl; 451 pcr->ms_pull_ctl_disable_tbl = rtl8411_ms_pull_ctl_disable_tbl; 452} 453 454void rtl8411b_init_params(struct rtsx_pcr *pcr) 455{ 456 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 457 pcr->num_slots = 2; 458 pcr->ops = &rtl8411b_pcr_ops; 459 460 pcr->flags = 0; 461 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT; 462 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 463 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 464 pcr->aspm_en = ASPM_L1_EN; 465 466 pcr->ic_version = rtl8411_get_ic_version(pcr); 467 468 if (rtl8411b_is_qfn48(pcr)) { 469 pcr->sd_pull_ctl_enable_tbl = 470 rtl8411b_qfn48_sd_pull_ctl_enable_tbl; 471 pcr->sd_pull_ctl_disable_tbl = 472 rtl8411b_qfn48_sd_pull_ctl_disable_tbl; 473 pcr->ms_pull_ctl_enable_tbl = 474 rtl8411b_qfn48_ms_pull_ctl_enable_tbl; 475 pcr->ms_pull_ctl_disable_tbl = 476 rtl8411b_qfn48_ms_pull_ctl_disable_tbl; 477 } else { 478 pcr->sd_pull_ctl_enable_tbl = 479 rtl8411b_qfn64_sd_pull_ctl_enable_tbl; 480 pcr->sd_pull_ctl_disable_tbl = 481 rtl8411b_qfn64_sd_pull_ctl_disable_tbl; 482 pcr->ms_pull_ctl_enable_tbl = 483 rtl8411b_qfn64_ms_pull_ctl_enable_tbl; 484 pcr->ms_pull_ctl_disable_tbl = 485 rtl8411b_qfn64_ms_pull_ctl_disable_tbl; 486 } 487} 488