twl4030-irq.c revision 3c699105d0376c14940ce7cf561754a94cdff8dd
1/* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30#include <linux/export.h> 31#include <linux/interrupt.h> 32#include <linux/irq.h> 33#include <linux/slab.h> 34#include <linux/of.h> 35#include <linux/irqdomain.h> 36#include <linux/i2c/twl.h> 37 38#include "twl-core.h" 39 40/* 41 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 42 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 43 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 44 * SIH modules are more traditional IRQ components, which support per-IRQ 45 * enable/disable and trigger controls; they do most of the work. 46 * 47 * These chips are designed to support IRQ handling from two different 48 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 49 * and mask registers in the PIH and SIH modules. 50 * 51 * We set up IRQs starting at a platform-specified base, always starting 52 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 53 * base + 0 .. base + 7 PIH 54 * base + 8 .. base + 15 SIH for PWR_INT 55 * base + 16 .. base + 33 SIH for GPIO 56 */ 57#define TWL4030_CORE_NR_IRQS 8 58#define TWL4030_PWR_NR_IRQS 8 59 60/* PIH register offsets */ 61#define REG_PIH_ISR_P1 0x01 62#define REG_PIH_ISR_P2 0x02 63#define REG_PIH_SIR 0x03 /* for testing */ 64 65/* Linux could (eventually) use either IRQ line */ 66static int irq_line; 67 68struct sih { 69 char name[8]; 70 u8 module; /* module id */ 71 u8 control_offset; /* for SIH_CTRL */ 72 bool set_cor; 73 74 u8 bits; /* valid in isr/imr */ 75 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 76 77 u8 edr_offset; 78 u8 bytes_edr; /* bytelen of EDR */ 79 80 u8 irq_lines; /* number of supported irq lines */ 81 82 /* SIR ignored -- set interrupt, for testing only */ 83 struct sih_irq_data { 84 u8 isr_offset; 85 u8 imr_offset; 86 } mask[2]; 87 /* + 2 bytes padding */ 88}; 89 90static const struct sih *sih_modules; 91static int nr_sih_modules; 92 93#define SIH_INITIALIZER(modname, nbits) \ 94 .module = TWL4030_MODULE_ ## modname, \ 95 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 96 .bits = nbits, \ 97 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 98 .edr_offset = TWL4030_ ## modname ## _EDR, \ 99 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 100 .irq_lines = 2, \ 101 .mask = { { \ 102 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 103 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 104 }, \ 105 { \ 106 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 107 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 108 }, }, 109 110/* register naming policies are inconsistent ... */ 111#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 112#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 113#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 114 115 116/* 117 * Order in this table matches order in PIH_ISR. That is, 118 * BIT(n) in PIH_ISR is sih_modules[n]. 119 */ 120/* sih_modules_twl4030 is used both in twl4030 and twl5030 */ 121static const struct sih sih_modules_twl4030[6] = { 122 [0] = { 123 .name = "gpio", 124 .module = TWL4030_MODULE_GPIO, 125 .control_offset = REG_GPIO_SIH_CTRL, 126 .set_cor = true, 127 .bits = TWL4030_GPIO_MAX, 128 .bytes_ixr = 3, 129 /* Note: *all* of these IRQs default to no-trigger */ 130 .edr_offset = REG_GPIO_EDR1, 131 .bytes_edr = 5, 132 .irq_lines = 2, 133 .mask = { { 134 .isr_offset = REG_GPIO_ISR1A, 135 .imr_offset = REG_GPIO_IMR1A, 136 }, { 137 .isr_offset = REG_GPIO_ISR1B, 138 .imr_offset = REG_GPIO_IMR1B, 139 }, }, 140 }, 141 [1] = { 142 .name = "keypad", 143 .set_cor = true, 144 SIH_INITIALIZER(KEYPAD_KEYP, 4) 145 }, 146 [2] = { 147 .name = "bci", 148 .module = TWL4030_MODULE_INTERRUPTS, 149 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 150 .set_cor = true, 151 .bits = 12, 152 .bytes_ixr = 2, 153 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 154 /* Note: most of these IRQs default to no-trigger */ 155 .bytes_edr = 3, 156 .irq_lines = 2, 157 .mask = { { 158 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 159 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 160 }, { 161 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 162 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 163 }, }, 164 }, 165 [3] = { 166 .name = "madc", 167 SIH_INITIALIZER(MADC, 4) 168 }, 169 [4] = { 170 /* USB doesn't use the same SIH organization */ 171 .name = "usb", 172 }, 173 [5] = { 174 .name = "power", 175 .set_cor = true, 176 SIH_INITIALIZER(INT_PWR, 8) 177 }, 178 /* there are no SIH modules #6 or #7 ... */ 179}; 180 181static const struct sih sih_modules_twl5031[8] = { 182 [0] = { 183 .name = "gpio", 184 .module = TWL4030_MODULE_GPIO, 185 .control_offset = REG_GPIO_SIH_CTRL, 186 .set_cor = true, 187 .bits = TWL4030_GPIO_MAX, 188 .bytes_ixr = 3, 189 /* Note: *all* of these IRQs default to no-trigger */ 190 .edr_offset = REG_GPIO_EDR1, 191 .bytes_edr = 5, 192 .irq_lines = 2, 193 .mask = { { 194 .isr_offset = REG_GPIO_ISR1A, 195 .imr_offset = REG_GPIO_IMR1A, 196 }, { 197 .isr_offset = REG_GPIO_ISR1B, 198 .imr_offset = REG_GPIO_IMR1B, 199 }, }, 200 }, 201 [1] = { 202 .name = "keypad", 203 .set_cor = true, 204 SIH_INITIALIZER(KEYPAD_KEYP, 4) 205 }, 206 [2] = { 207 .name = "bci", 208 .module = TWL5031_MODULE_INTERRUPTS, 209 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, 210 .bits = 7, 211 .bytes_ixr = 1, 212 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, 213 /* Note: most of these IRQs default to no-trigger */ 214 .bytes_edr = 2, 215 .irq_lines = 2, 216 .mask = { { 217 .isr_offset = TWL5031_INTERRUPTS_BCIISR1, 218 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, 219 }, { 220 .isr_offset = TWL5031_INTERRUPTS_BCIISR2, 221 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, 222 }, }, 223 }, 224 [3] = { 225 .name = "madc", 226 SIH_INITIALIZER(MADC, 4) 227 }, 228 [4] = { 229 /* USB doesn't use the same SIH organization */ 230 .name = "usb", 231 }, 232 [5] = { 233 .name = "power", 234 .set_cor = true, 235 SIH_INITIALIZER(INT_PWR, 8) 236 }, 237 [6] = { 238 /* 239 * ECI/DBI doesn't use the same SIH organization. 240 * For example, it supports only one interrupt output line. 241 * That is, the interrupts are seen on both INT1 and INT2 lines. 242 */ 243 .name = "eci_dbi", 244 .module = TWL5031_MODULE_ACCESSORY, 245 .bits = 9, 246 .bytes_ixr = 2, 247 .irq_lines = 1, 248 .mask = { { 249 .isr_offset = TWL5031_ACIIDR_LSB, 250 .imr_offset = TWL5031_ACIIMR_LSB, 251 }, }, 252 253 }, 254 [7] = { 255 /* Audio accessory */ 256 .name = "audio", 257 .module = TWL5031_MODULE_ACCESSORY, 258 .control_offset = TWL5031_ACCSIHCTRL, 259 .bits = 2, 260 .bytes_ixr = 1, 261 .edr_offset = TWL5031_ACCEDR1, 262 /* Note: most of these IRQs default to no-trigger */ 263 .bytes_edr = 1, 264 .irq_lines = 2, 265 .mask = { { 266 .isr_offset = TWL5031_ACCISR1, 267 .imr_offset = TWL5031_ACCIMR1, 268 }, { 269 .isr_offset = TWL5031_ACCISR2, 270 .imr_offset = TWL5031_ACCIMR2, 271 }, }, 272 }, 273}; 274 275#undef TWL4030_MODULE_KEYPAD_KEYP 276#undef TWL4030_MODULE_INT_PWR 277#undef TWL4030_INT_PWR_EDR 278 279/*----------------------------------------------------------------------*/ 280 281static unsigned twl4030_irq_base; 282 283/* 284 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 285 * This is a chained interrupt, so there is no desc->action method for it. 286 * Now we need to query the interrupt controller in the twl4030 to determine 287 * which module is generating the interrupt request. However, we can't do i2c 288 * transactions in interrupt context, so we must defer that work to a kernel 289 * thread. All we do here is acknowledge and mask the interrupt and wakeup 290 * the kernel thread. 291 */ 292static irqreturn_t handle_twl4030_pih(int irq, void *devid) 293{ 294 irqreturn_t ret; 295 u8 pih_isr; 296 297 ret = twl_i2c_read_u8(TWL_MODULE_PIH, &pih_isr, 298 REG_PIH_ISR_P1); 299 if (ret) { 300 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret); 301 return IRQ_NONE; 302 } 303 304 while (pih_isr) { 305 unsigned long pending = __ffs(pih_isr); 306 unsigned int irq; 307 308 pih_isr &= ~BIT(pending); 309 irq = pending + twl4030_irq_base; 310 handle_nested_irq(irq); 311 } 312 313 return IRQ_HANDLED; 314} 315 316/*----------------------------------------------------------------------*/ 317 318/* 319 * twl4030_init_sih_modules() ... start from a known state where no 320 * IRQs will be coming in, and where we can quickly enable them then 321 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 322 * 323 * NOTE: we don't touch EDR registers here; they stay with hardware 324 * defaults or whatever the last value was. Note that when both EDR 325 * bits for an IRQ are clear, that's as if its IMR bit is set... 326 */ 327static int twl4030_init_sih_modules(unsigned line) 328{ 329 const struct sih *sih; 330 u8 buf[4]; 331 int i; 332 int status; 333 334 /* line 0 == int1_n signal; line 1 == int2_n signal */ 335 if (line > 1) 336 return -EINVAL; 337 338 irq_line = line; 339 340 /* disable all interrupts on our line */ 341 memset(buf, 0xff, sizeof buf); 342 sih = sih_modules; 343 for (i = 0; i < nr_sih_modules; i++, sih++) { 344 /* skip USB -- it's funky */ 345 if (!sih->bytes_ixr) 346 continue; 347 348 /* Not all the SIH modules support multiple interrupt lines */ 349 if (sih->irq_lines <= line) 350 continue; 351 352 status = twl_i2c_write(sih->module, buf, 353 sih->mask[line].imr_offset, sih->bytes_ixr); 354 if (status < 0) 355 pr_err("twl4030: err %d initializing %s %s\n", 356 status, sih->name, "IMR"); 357 358 /* 359 * Maybe disable "exclusive" mode; buffer second pending irq; 360 * set Clear-On-Read (COR) bit. 361 * 362 * NOTE that sometimes COR polarity is documented as being 363 * inverted: for MADC, COR=1 means "clear on write". 364 * And for PWR_INT it's not documented... 365 */ 366 if (sih->set_cor) { 367 status = twl_i2c_write_u8(sih->module, 368 TWL4030_SIH_CTRL_COR_MASK, 369 sih->control_offset); 370 if (status < 0) 371 pr_err("twl4030: err %d initializing %s %s\n", 372 status, sih->name, "SIH_CTRL"); 373 } 374 } 375 376 sih = sih_modules; 377 for (i = 0; i < nr_sih_modules; i++, sih++) { 378 u8 rxbuf[4]; 379 int j; 380 381 /* skip USB */ 382 if (!sih->bytes_ixr) 383 continue; 384 385 /* Not all the SIH modules support multiple interrupt lines */ 386 if (sih->irq_lines <= line) 387 continue; 388 389 /* 390 * Clear pending interrupt status. Either the read was 391 * enough, or we need to write those bits. Repeat, in 392 * case an IRQ is pending (PENDDIS=0) ... that's not 393 * uncommon with PWR_INT.PWRON. 394 */ 395 for (j = 0; j < 2; j++) { 396 status = twl_i2c_read(sih->module, rxbuf, 397 sih->mask[line].isr_offset, sih->bytes_ixr); 398 if (status < 0) 399 pr_err("twl4030: err %d initializing %s %s\n", 400 status, sih->name, "ISR"); 401 402 if (!sih->set_cor) 403 status = twl_i2c_write(sih->module, buf, 404 sih->mask[line].isr_offset, 405 sih->bytes_ixr); 406 /* 407 * else COR=1 means read sufficed. 408 * (for most SIH modules...) 409 */ 410 } 411 } 412 413 return 0; 414} 415 416static inline void activate_irq(int irq) 417{ 418#ifdef CONFIG_ARM 419 /* 420 * ARM requires an extra step to clear IRQ_NOREQUEST, which it 421 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 422 */ 423 set_irq_flags(irq, IRQF_VALID); 424#else 425 /* same effect on other architectures */ 426 irq_set_noprobe(irq); 427#endif 428} 429 430/*----------------------------------------------------------------------*/ 431 432struct sih_agent { 433 int irq_base; 434 const struct sih *sih; 435 436 u32 imr; 437 bool imr_change_pending; 438 439 u32 edge_change; 440 441 struct mutex irq_lock; 442 char *irq_name; 443}; 444 445/*----------------------------------------------------------------------*/ 446 447/* 448 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 449 * which can't perform the underlying I2C operations (because they sleep). 450 * So we must hand them off to a thread (workqueue) and cope with asynch 451 * completion, potentially including some re-ordering, of these requests. 452 */ 453 454static void twl4030_sih_mask(struct irq_data *data) 455{ 456 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 457 458 agent->imr |= BIT(data->irq - agent->irq_base); 459 agent->imr_change_pending = true; 460} 461 462static void twl4030_sih_unmask(struct irq_data *data) 463{ 464 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 465 466 agent->imr &= ~BIT(data->irq - agent->irq_base); 467 agent->imr_change_pending = true; 468} 469 470static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) 471{ 472 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 473 474 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 475 return -EINVAL; 476 477 if (irqd_get_trigger_type(data) != trigger) 478 agent->edge_change |= BIT(data->irq - agent->irq_base); 479 480 return 0; 481} 482 483static void twl4030_sih_bus_lock(struct irq_data *data) 484{ 485 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 486 487 mutex_lock(&agent->irq_lock); 488} 489 490static void twl4030_sih_bus_sync_unlock(struct irq_data *data) 491{ 492 struct sih_agent *agent = irq_data_get_irq_chip_data(data); 493 const struct sih *sih = agent->sih; 494 int status; 495 496 if (agent->imr_change_pending) { 497 union { 498 u32 word; 499 u8 bytes[4]; 500 } imr; 501 502 /* byte[0] gets overwritten as we write ... */ 503 imr.word = cpu_to_le32(agent->imr); 504 agent->imr_change_pending = false; 505 506 /* write the whole mask ... simpler than subsetting it */ 507 status = twl_i2c_write(sih->module, imr.bytes, 508 sih->mask[irq_line].imr_offset, 509 sih->bytes_ixr); 510 if (status) 511 pr_err("twl4030: %s, %s --> %d\n", __func__, 512 "write", status); 513 } 514 515 if (agent->edge_change) { 516 u32 edge_change; 517 u8 bytes[6]; 518 519 edge_change = agent->edge_change; 520 agent->edge_change = 0; 521 522 /* 523 * Read, reserving first byte for write scratch. Yes, this 524 * could be cached for some speedup ... but be careful about 525 * any processor on the other IRQ line, EDR registers are 526 * shared. 527 */ 528 status = twl_i2c_read(sih->module, bytes, 529 sih->edr_offset, sih->bytes_edr); 530 if (status) { 531 pr_err("twl4030: %s, %s --> %d\n", __func__, 532 "read", status); 533 return; 534 } 535 536 /* Modify only the bits we know must change */ 537 while (edge_change) { 538 int i = fls(edge_change) - 1; 539 int byte = i >> 2; 540 int off = (i & 0x3) * 2; 541 unsigned int type; 542 543 bytes[byte] &= ~(0x03 << off); 544 545 type = irq_get_trigger_type(i + agent->irq_base); 546 if (type & IRQ_TYPE_EDGE_RISING) 547 bytes[byte] |= BIT(off + 1); 548 if (type & IRQ_TYPE_EDGE_FALLING) 549 bytes[byte] |= BIT(off + 0); 550 551 edge_change &= ~BIT(i); 552 } 553 554 /* Write */ 555 status = twl_i2c_write(sih->module, bytes, 556 sih->edr_offset, sih->bytes_edr); 557 if (status) 558 pr_err("twl4030: %s, %s --> %d\n", __func__, 559 "write", status); 560 } 561 562 mutex_unlock(&agent->irq_lock); 563} 564 565static struct irq_chip twl4030_sih_irq_chip = { 566 .name = "twl4030", 567 .irq_mask = twl4030_sih_mask, 568 .irq_unmask = twl4030_sih_unmask, 569 .irq_set_type = twl4030_sih_set_type, 570 .irq_bus_lock = twl4030_sih_bus_lock, 571 .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, 572 .flags = IRQCHIP_SKIP_SET_WAKE, 573}; 574 575/*----------------------------------------------------------------------*/ 576 577static inline int sih_read_isr(const struct sih *sih) 578{ 579 int status; 580 union { 581 u8 bytes[4]; 582 u32 word; 583 } isr; 584 585 /* FIXME need retry-on-error ... */ 586 587 isr.word = 0; 588 status = twl_i2c_read(sih->module, isr.bytes, 589 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 590 591 return (status < 0) ? status : le32_to_cpu(isr.word); 592} 593 594/* 595 * Generic handler for SIH interrupts ... we "know" this is called 596 * in task context, with IRQs enabled. 597 */ 598static irqreturn_t handle_twl4030_sih(int irq, void *data) 599{ 600 struct sih_agent *agent = irq_get_handler_data(irq); 601 const struct sih *sih = agent->sih; 602 int isr; 603 604 /* reading ISR acks the IRQs, using clear-on-read mode */ 605 isr = sih_read_isr(sih); 606 607 if (isr < 0) { 608 pr_err("twl4030: %s SIH, read ISR error %d\n", 609 sih->name, isr); 610 /* REVISIT: recover; eventually mask it all, etc */ 611 return IRQ_HANDLED; 612 } 613 614 while (isr) { 615 irq = fls(isr); 616 irq--; 617 isr &= ~BIT(irq); 618 619 if (irq < sih->bits) 620 handle_nested_irq(agent->irq_base + irq); 621 else 622 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 623 sih->name, irq); 624 } 625 return IRQ_HANDLED; 626} 627 628/* returns the first IRQ used by this SIH bank, or negative errno */ 629int twl4030_sih_setup(struct device *dev, int module, int irq_base) 630{ 631 int sih_mod; 632 const struct sih *sih = NULL; 633 struct sih_agent *agent; 634 int i, irq; 635 int status = -EINVAL; 636 637 /* only support modules with standard clear-on-read for now */ 638 for (sih_mod = 0, sih = sih_modules; sih_mod < nr_sih_modules; 639 sih_mod++, sih++) { 640 if (sih->module == module && sih->set_cor) { 641 status = 0; 642 break; 643 } 644 } 645 646 if (status < 0) 647 return status; 648 649 agent = kzalloc(sizeof *agent, GFP_KERNEL); 650 if (!agent) 651 return -ENOMEM; 652 653 agent->irq_base = irq_base; 654 agent->sih = sih; 655 agent->imr = ~0; 656 mutex_init(&agent->irq_lock); 657 658 for (i = 0; i < sih->bits; i++) { 659 irq = irq_base + i; 660 661 irq_set_chip_data(irq, agent); 662 irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, 663 handle_edge_irq); 664 irq_set_nested_thread(irq, 1); 665 activate_irq(irq); 666 } 667 668 /* replace generic PIH handler (handle_simple_irq) */ 669 irq = sih_mod + twl4030_irq_base; 670 irq_set_handler_data(irq, agent); 671 agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name); 672 status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 673 IRQF_EARLY_RESUME, 674 agent->irq_name ?: sih->name, NULL); 675 676 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", sih->name, 677 irq, irq_base, irq_base + i - 1); 678 679 return status < 0 ? status : irq_base; 680} 681 682/* FIXME need a call to reverse twl4030_sih_setup() ... */ 683 684/*----------------------------------------------------------------------*/ 685 686/* FIXME pass in which interrupt line we'll use ... */ 687#define twl_irq_line 0 688 689int twl4030_init_irq(struct device *dev, int irq_num) 690{ 691 static struct irq_chip twl4030_irq_chip; 692 int status, i; 693 int irq_base, irq_end, nr_irqs; 694 struct device_node *node = dev->of_node; 695 696 /* 697 * TWL core and pwr interrupts must be contiguous because 698 * the hwirqs numbers are defined contiguously from 1 to 15. 699 * Create only one domain for both. 700 */ 701 nr_irqs = TWL4030_PWR_NR_IRQS + TWL4030_CORE_NR_IRQS; 702 703 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 704 if (IS_ERR_VALUE(irq_base)) { 705 dev_err(dev, "Fail to allocate IRQ descs\n"); 706 return irq_base; 707 } 708 709 irq_domain_add_legacy(node, nr_irqs, irq_base, 0, 710 &irq_domain_simple_ops, NULL); 711 712 irq_end = irq_base + TWL4030_CORE_NR_IRQS; 713 714 /* 715 * Mask and clear all TWL4030 interrupts since initially we do 716 * not have any TWL4030 module interrupt handlers present 717 */ 718 status = twl4030_init_sih_modules(twl_irq_line); 719 if (status < 0) 720 return status; 721 722 twl4030_irq_base = irq_base; 723 724 /* 725 * Install an irq handler for each of the SIH modules; 726 * clone dummy irq_chip since PIH can't *do* anything 727 */ 728 twl4030_irq_chip = dummy_irq_chip; 729 twl4030_irq_chip.name = "twl4030"; 730 731 twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; 732 733 for (i = irq_base; i < irq_end; i++) { 734 irq_set_chip_and_handler(i, &twl4030_irq_chip, 735 handle_simple_irq); 736 irq_set_nested_thread(i, 1); 737 activate_irq(i); 738 } 739 740 dev_info(dev, "%s (irq %d) chaining IRQs %d..%d\n", "PIH", 741 irq_num, irq_base, irq_end); 742 743 /* ... and the PWR_INT module ... */ 744 status = twl4030_sih_setup(dev, TWL4030_MODULE_INT, irq_end); 745 if (status < 0) { 746 dev_err(dev, "sih_setup PWR INT --> %d\n", status); 747 goto fail; 748 } 749 750 /* install an irq handler to demultiplex the TWL4030 interrupt */ 751 status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, 752 IRQF_ONESHOT, 753 "TWL4030-PIH", NULL); 754 if (status < 0) { 755 dev_err(dev, "could not claim irq%d: %d\n", irq_num, status); 756 goto fail_rqirq; 757 } 758 enable_irq_wake(irq_num); 759 760 return irq_base; 761fail_rqirq: 762 /* clean up twl4030_sih_setup */ 763fail: 764 for (i = irq_base; i < irq_end; i++) { 765 irq_set_nested_thread(i, 0); 766 irq_set_chip_and_handler(i, NULL, NULL); 767 } 768 769 return status; 770} 771 772int twl4030_exit_irq(void) 773{ 774 /* FIXME undo twl_init_irq() */ 775 if (twl4030_irq_base) { 776 pr_err("twl4030: can't yet clean up IRQs?\n"); 777 return -ENOSYS; 778 } 779 return 0; 780} 781 782int twl4030_init_chip_irq(const char *chip) 783{ 784 if (!strcmp(chip, "twl5031")) { 785 sih_modules = sih_modules_twl5031; 786 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); 787 } else { 788 sih_modules = sih_modules_twl4030; 789 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); 790 } 791 792 return 0; 793} 794