twl4030-irq.c revision fc7b92fca4e546184557f1c53f84ad57c66b7695
1/* 2 * twl4030-irq.c - TWL4030/TPS659x0 irq support 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Modifications to defer interrupt handling to a kernel thread: 7 * Copyright (C) 2006 MontaVista Software, Inc. 8 * 9 * Based on tlv320aic23.c: 10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11 * 12 * Code cleanup and modifications to IRQ handler. 13 * by syed khasim <x0khasim@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28 */ 29 30#include <linux/init.h> 31#include <linux/interrupt.h> 32#include <linux/irq.h> 33#include <linux/kthread.h> 34 35#include <linux/i2c/twl.h> 36 37 38/* 39 * TWL4030 IRQ handling has two stages in hardware, and thus in software. 40 * The Primary Interrupt Handler (PIH) stage exposes status bits saying 41 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 42 * SIH modules are more traditional IRQ components, which support per-IRQ 43 * enable/disable and trigger controls; they do most of the work. 44 * 45 * These chips are designed to support IRQ handling from two different 46 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 47 * and mask registers in the PIH and SIH modules. 48 * 49 * We set up IRQs starting at a platform-specified base, always starting 50 * with PIH and the SIH for PWR_INT and then usually adding GPIO: 51 * base + 0 .. base + 7 PIH 52 * base + 8 .. base + 15 SIH for PWR_INT 53 * base + 16 .. base + 33 SIH for GPIO 54 */ 55 56/* PIH register offsets */ 57#define REG_PIH_ISR_P1 0x01 58#define REG_PIH_ISR_P2 0x02 59#define REG_PIH_SIR 0x03 /* for testing */ 60 61 62/* Linux could (eventually) use either IRQ line */ 63static int irq_line; 64 65struct sih { 66 char name[8]; 67 u8 module; /* module id */ 68 u8 control_offset; /* for SIH_CTRL */ 69 bool set_cor; 70 71 u8 bits; /* valid in isr/imr */ 72 u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 73 74 u8 edr_offset; 75 u8 bytes_edr; /* bytelen of EDR */ 76 77 u8 irq_lines; /* number of supported irq lines */ 78 79 /* SIR ignored -- set interrupt, for testing only */ 80 struct irq_data { 81 u8 isr_offset; 82 u8 imr_offset; 83 } mask[2]; 84 /* + 2 bytes padding */ 85}; 86 87static const struct sih *sih_modules; 88static int nr_sih_modules; 89 90#define SIH_INITIALIZER(modname, nbits) \ 91 .module = TWL4030_MODULE_ ## modname, \ 92 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 93 .bits = nbits, \ 94 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 95 .edr_offset = TWL4030_ ## modname ## _EDR, \ 96 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 97 .irq_lines = 2, \ 98 .mask = { { \ 99 .isr_offset = TWL4030_ ## modname ## _ISR1, \ 100 .imr_offset = TWL4030_ ## modname ## _IMR1, \ 101 }, \ 102 { \ 103 .isr_offset = TWL4030_ ## modname ## _ISR2, \ 104 .imr_offset = TWL4030_ ## modname ## _IMR2, \ 105 }, }, 106 107/* register naming policies are inconsistent ... */ 108#define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 109#define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 110#define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 111 112 113/* Order in this table matches order in PIH_ISR. That is, 114 * BIT(n) in PIH_ISR is sih_modules[n]. 115 */ 116/* sih_modules_twl4030 is used both in twl4030 and twl5030 */ 117static const struct sih sih_modules_twl4030[6] = { 118 [0] = { 119 .name = "gpio", 120 .module = TWL4030_MODULE_GPIO, 121 .control_offset = REG_GPIO_SIH_CTRL, 122 .set_cor = true, 123 .bits = TWL4030_GPIO_MAX, 124 .bytes_ixr = 3, 125 /* Note: *all* of these IRQs default to no-trigger */ 126 .edr_offset = REG_GPIO_EDR1, 127 .bytes_edr = 5, 128 .irq_lines = 2, 129 .mask = { { 130 .isr_offset = REG_GPIO_ISR1A, 131 .imr_offset = REG_GPIO_IMR1A, 132 }, { 133 .isr_offset = REG_GPIO_ISR1B, 134 .imr_offset = REG_GPIO_IMR1B, 135 }, }, 136 }, 137 [1] = { 138 .name = "keypad", 139 .set_cor = true, 140 SIH_INITIALIZER(KEYPAD_KEYP, 4) 141 }, 142 [2] = { 143 .name = "bci", 144 .module = TWL4030_MODULE_INTERRUPTS, 145 .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 146 .bits = 12, 147 .bytes_ixr = 2, 148 .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 149 /* Note: most of these IRQs default to no-trigger */ 150 .bytes_edr = 3, 151 .irq_lines = 2, 152 .mask = { { 153 .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 154 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 155 }, { 156 .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 157 .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 158 }, }, 159 }, 160 [3] = { 161 .name = "madc", 162 SIH_INITIALIZER(MADC, 4) 163 }, 164 [4] = { 165 /* USB doesn't use the same SIH organization */ 166 .name = "usb", 167 }, 168 [5] = { 169 .name = "power", 170 .set_cor = true, 171 SIH_INITIALIZER(INT_PWR, 8) 172 }, 173 /* there are no SIH modules #6 or #7 ... */ 174}; 175 176static const struct sih sih_modules_twl5031[8] = { 177 [0] = { 178 .name = "gpio", 179 .module = TWL4030_MODULE_GPIO, 180 .control_offset = REG_GPIO_SIH_CTRL, 181 .set_cor = true, 182 .bits = TWL4030_GPIO_MAX, 183 .bytes_ixr = 3, 184 /* Note: *all* of these IRQs default to no-trigger */ 185 .edr_offset = REG_GPIO_EDR1, 186 .bytes_edr = 5, 187 .irq_lines = 2, 188 .mask = { { 189 .isr_offset = REG_GPIO_ISR1A, 190 .imr_offset = REG_GPIO_IMR1A, 191 }, { 192 .isr_offset = REG_GPIO_ISR1B, 193 .imr_offset = REG_GPIO_IMR1B, 194 }, }, 195 }, 196 [1] = { 197 .name = "keypad", 198 .set_cor = true, 199 SIH_INITIALIZER(KEYPAD_KEYP, 4) 200 }, 201 [2] = { 202 .name = "bci", 203 .module = TWL5031_MODULE_INTERRUPTS, 204 .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, 205 .bits = 7, 206 .bytes_ixr = 1, 207 .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, 208 /* Note: most of these IRQs default to no-trigger */ 209 .bytes_edr = 2, 210 .irq_lines = 2, 211 .mask = { { 212 .isr_offset = TWL5031_INTERRUPTS_BCIISR1, 213 .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, 214 }, { 215 .isr_offset = TWL5031_INTERRUPTS_BCIISR2, 216 .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, 217 }, }, 218 }, 219 [3] = { 220 .name = "madc", 221 SIH_INITIALIZER(MADC, 4) 222 }, 223 [4] = { 224 /* USB doesn't use the same SIH organization */ 225 .name = "usb", 226 }, 227 [5] = { 228 .name = "power", 229 .set_cor = true, 230 SIH_INITIALIZER(INT_PWR, 8) 231 }, 232 [6] = { 233 /* 234 * ACI doesn't use the same SIH organization. 235 * For example, it supports only one interrupt line 236 */ 237 .name = "aci", 238 .module = TWL5031_MODULE_ACCESSORY, 239 .bits = 9, 240 .bytes_ixr = 2, 241 .irq_lines = 1, 242 .mask = { { 243 .isr_offset = TWL5031_ACIIDR_LSB, 244 .imr_offset = TWL5031_ACIIMR_LSB, 245 }, }, 246 247 }, 248 [7] = { 249 /* Accessory */ 250 .name = "acc", 251 .module = TWL5031_MODULE_ACCESSORY, 252 .control_offset = TWL5031_ACCSIHCTRL, 253 .bits = 2, 254 .bytes_ixr = 1, 255 .edr_offset = TWL5031_ACCEDR1, 256 /* Note: most of these IRQs default to no-trigger */ 257 .bytes_edr = 1, 258 .irq_lines = 2, 259 .mask = { { 260 .isr_offset = TWL5031_ACCISR1, 261 .imr_offset = TWL5031_ACCIMR1, 262 }, { 263 .isr_offset = TWL5031_ACCISR2, 264 .imr_offset = TWL5031_ACCIMR2, 265 }, }, 266 }, 267}; 268 269#undef TWL4030_MODULE_KEYPAD_KEYP 270#undef TWL4030_MODULE_INT_PWR 271#undef TWL4030_INT_PWR_EDR 272 273/*----------------------------------------------------------------------*/ 274 275static unsigned twl4030_irq_base; 276 277static struct completion irq_event; 278 279/* 280 * This thread processes interrupts reported by the Primary Interrupt Handler. 281 */ 282static int twl4030_irq_thread(void *data) 283{ 284 long irq = (long)data; 285 static unsigned i2c_errors; 286 static const unsigned max_i2c_errors = 100; 287 288 289 current->flags |= PF_NOFREEZE; 290 291 while (!kthread_should_stop()) { 292 int ret; 293 int module_irq; 294 u8 pih_isr; 295 296 /* Wait for IRQ, then read PIH irq status (also blocking) */ 297 wait_for_completion_interruptible(&irq_event); 298 299 ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 300 REG_PIH_ISR_P1); 301 if (ret) { 302 pr_warning("twl4030: I2C error %d reading PIH ISR\n", 303 ret); 304 if (++i2c_errors >= max_i2c_errors) { 305 printk(KERN_ERR "Maximum I2C error count" 306 " exceeded. Terminating %s.\n", 307 __func__); 308 break; 309 } 310 complete(&irq_event); 311 continue; 312 } 313 314 /* these handlers deal with the relevant SIH irq status */ 315 local_irq_disable(); 316 for (module_irq = twl4030_irq_base; 317 pih_isr; 318 pih_isr >>= 1, module_irq++) { 319 if (pih_isr & 0x1) { 320 struct irq_desc *d = irq_to_desc(module_irq); 321 322 if (!d) { 323 pr_err("twl4030: Invalid SIH IRQ: %d\n", 324 module_irq); 325 return -EINVAL; 326 } 327 328 /* These can't be masked ... always warn 329 * if we get any surprises. 330 */ 331 if (d->status & IRQ_DISABLED) 332 note_interrupt(module_irq, d, 333 IRQ_NONE); 334 else 335 d->handle_irq(module_irq, d); 336 } 337 } 338 local_irq_enable(); 339 340 enable_irq(irq); 341 } 342 343 return 0; 344} 345 346/* 347 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 348 * This is a chained interrupt, so there is no desc->action method for it. 349 * Now we need to query the interrupt controller in the twl4030 to determine 350 * which module is generating the interrupt request. However, we can't do i2c 351 * transactions in interrupt context, so we must defer that work to a kernel 352 * thread. All we do here is acknowledge and mask the interrupt and wakeup 353 * the kernel thread. 354 */ 355static irqreturn_t handle_twl4030_pih(int irq, void *devid) 356{ 357 /* Acknowledge, clear *AND* mask the interrupt... */ 358 disable_irq_nosync(irq); 359 complete(devid); 360 return IRQ_HANDLED; 361} 362/*----------------------------------------------------------------------*/ 363 364/* 365 * twl4030_init_sih_modules() ... start from a known state where no 366 * IRQs will be coming in, and where we can quickly enable them then 367 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 368 * 369 * NOTE: we don't touch EDR registers here; they stay with hardware 370 * defaults or whatever the last value was. Note that when both EDR 371 * bits for an IRQ are clear, that's as if its IMR bit is set... 372 */ 373static int twl4030_init_sih_modules(unsigned line) 374{ 375 const struct sih *sih; 376 u8 buf[4]; 377 int i; 378 int status; 379 380 /* line 0 == int1_n signal; line 1 == int2_n signal */ 381 if (line > 1) 382 return -EINVAL; 383 384 irq_line = line; 385 386 /* disable all interrupts on our line */ 387 memset(buf, 0xff, sizeof buf); 388 sih = sih_modules; 389 for (i = 0; i < nr_sih_modules; i++, sih++) { 390 391 /* skip USB -- it's funky */ 392 if (!sih->bytes_ixr) 393 continue; 394 395 /* Not all the SIH modules support multiple interrupt lines */ 396 if (sih->irq_lines <= line) 397 continue; 398 399 status = twl_i2c_write(sih->module, buf, 400 sih->mask[line].imr_offset, sih->bytes_ixr); 401 if (status < 0) 402 pr_err("twl4030: err %d initializing %s %s\n", 403 status, sih->name, "IMR"); 404 405 /* Maybe disable "exclusive" mode; buffer second pending irq; 406 * set Clear-On-Read (COR) bit. 407 * 408 * NOTE that sometimes COR polarity is documented as being 409 * inverted: for MADC and BCI, COR=1 means "clear on write". 410 * And for PWR_INT it's not documented... 411 */ 412 if (sih->set_cor) { 413 status = twl_i2c_write_u8(sih->module, 414 TWL4030_SIH_CTRL_COR_MASK, 415 sih->control_offset); 416 if (status < 0) 417 pr_err("twl4030: err %d initializing %s %s\n", 418 status, sih->name, "SIH_CTRL"); 419 } 420 } 421 422 sih = sih_modules; 423 for (i = 0; i < nr_sih_modules; i++, sih++) { 424 u8 rxbuf[4]; 425 int j; 426 427 /* skip USB */ 428 if (!sih->bytes_ixr) 429 continue; 430 431 /* Not all the SIH modules support multiple interrupt lines */ 432 if (sih->irq_lines <= line) 433 continue; 434 435 /* Clear pending interrupt status. Either the read was 436 * enough, or we need to write those bits. Repeat, in 437 * case an IRQ is pending (PENDDIS=0) ... that's not 438 * uncommon with PWR_INT.PWRON. 439 */ 440 for (j = 0; j < 2; j++) { 441 status = twl_i2c_read(sih->module, rxbuf, 442 sih->mask[line].isr_offset, sih->bytes_ixr); 443 if (status < 0) 444 pr_err("twl4030: err %d initializing %s %s\n", 445 status, sih->name, "ISR"); 446 447 if (!sih->set_cor) 448 status = twl_i2c_write(sih->module, buf, 449 sih->mask[line].isr_offset, 450 sih->bytes_ixr); 451 /* else COR=1 means read sufficed. 452 * (for most SIH modules...) 453 */ 454 } 455 } 456 457 return 0; 458} 459 460static inline void activate_irq(int irq) 461{ 462#ifdef CONFIG_ARM 463 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 464 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 465 */ 466 set_irq_flags(irq, IRQF_VALID); 467#else 468 /* same effect on other architectures */ 469 set_irq_noprobe(irq); 470#endif 471} 472 473/*----------------------------------------------------------------------*/ 474 475static DEFINE_SPINLOCK(sih_agent_lock); 476 477static struct workqueue_struct *wq; 478 479struct sih_agent { 480 int irq_base; 481 const struct sih *sih; 482 483 u32 imr; 484 bool imr_change_pending; 485 struct work_struct mask_work; 486 487 u32 edge_change; 488 struct work_struct edge_work; 489}; 490 491static void twl4030_sih_do_mask(struct work_struct *work) 492{ 493 struct sih_agent *agent; 494 const struct sih *sih; 495 union { 496 u8 bytes[4]; 497 u32 word; 498 } imr; 499 int status; 500 501 agent = container_of(work, struct sih_agent, mask_work); 502 503 /* see what work we have */ 504 spin_lock_irq(&sih_agent_lock); 505 if (agent->imr_change_pending) { 506 sih = agent->sih; 507 /* byte[0] gets overwritten as we write ... */ 508 imr.word = cpu_to_le32(agent->imr << 8); 509 agent->imr_change_pending = false; 510 } else 511 sih = NULL; 512 spin_unlock_irq(&sih_agent_lock); 513 if (!sih) 514 return; 515 516 /* write the whole mask ... simpler than subsetting it */ 517 status = twl_i2c_write(sih->module, imr.bytes, 518 sih->mask[irq_line].imr_offset, sih->bytes_ixr); 519 if (status) 520 pr_err("twl4030: %s, %s --> %d\n", __func__, 521 "write", status); 522} 523 524static void twl4030_sih_do_edge(struct work_struct *work) 525{ 526 struct sih_agent *agent; 527 const struct sih *sih; 528 u8 bytes[6]; 529 u32 edge_change; 530 int status; 531 532 agent = container_of(work, struct sih_agent, edge_work); 533 534 /* see what work we have */ 535 spin_lock_irq(&sih_agent_lock); 536 edge_change = agent->edge_change; 537 agent->edge_change = 0; 538 sih = edge_change ? agent->sih : NULL; 539 spin_unlock_irq(&sih_agent_lock); 540 if (!sih) 541 return; 542 543 /* Read, reserving first byte for write scratch. Yes, this 544 * could be cached for some speedup ... but be careful about 545 * any processor on the other IRQ line, EDR registers are 546 * shared. 547 */ 548 status = twl_i2c_read(sih->module, bytes + 1, 549 sih->edr_offset, sih->bytes_edr); 550 if (status) { 551 pr_err("twl4030: %s, %s --> %d\n", __func__, 552 "read", status); 553 return; 554 } 555 556 /* Modify only the bits we know must change */ 557 while (edge_change) { 558 int i = fls(edge_change) - 1; 559 struct irq_desc *d = irq_to_desc(i + agent->irq_base); 560 int byte = 1 + (i >> 2); 561 int off = (i & 0x3) * 2; 562 563 if (!d) { 564 pr_err("twl4030: Invalid IRQ: %d\n", 565 i + agent->irq_base); 566 return; 567 } 568 569 bytes[byte] &= ~(0x03 << off); 570 571 spin_lock_irq(&d->lock); 572 if (d->status & IRQ_TYPE_EDGE_RISING) 573 bytes[byte] |= BIT(off + 1); 574 if (d->status & IRQ_TYPE_EDGE_FALLING) 575 bytes[byte] |= BIT(off + 0); 576 spin_unlock_irq(&d->lock); 577 578 edge_change &= ~BIT(i); 579 } 580 581 /* Write */ 582 status = twl_i2c_write(sih->module, bytes, 583 sih->edr_offset, sih->bytes_edr); 584 if (status) 585 pr_err("twl4030: %s, %s --> %d\n", __func__, 586 "write", status); 587} 588 589/*----------------------------------------------------------------------*/ 590 591/* 592 * All irq_chip methods get issued from code holding irq_desc[irq].lock, 593 * which can't perform the underlying I2C operations (because they sleep). 594 * So we must hand them off to a thread (workqueue) and cope with asynch 595 * completion, potentially including some re-ordering, of these requests. 596 */ 597 598static void twl4030_sih_mask(unsigned irq) 599{ 600 struct sih_agent *sih = get_irq_chip_data(irq); 601 unsigned long flags; 602 603 spin_lock_irqsave(&sih_agent_lock, flags); 604 sih->imr |= BIT(irq - sih->irq_base); 605 sih->imr_change_pending = true; 606 queue_work(wq, &sih->mask_work); 607 spin_unlock_irqrestore(&sih_agent_lock, flags); 608} 609 610static void twl4030_sih_unmask(unsigned irq) 611{ 612 struct sih_agent *sih = get_irq_chip_data(irq); 613 unsigned long flags; 614 615 spin_lock_irqsave(&sih_agent_lock, flags); 616 sih->imr &= ~BIT(irq - sih->irq_base); 617 sih->imr_change_pending = true; 618 queue_work(wq, &sih->mask_work); 619 spin_unlock_irqrestore(&sih_agent_lock, flags); 620} 621 622static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 623{ 624 struct sih_agent *sih = get_irq_chip_data(irq); 625 struct irq_desc *desc = irq_to_desc(irq); 626 unsigned long flags; 627 628 if (!desc) { 629 pr_err("twl4030: Invalid IRQ: %d\n", irq); 630 return -EINVAL; 631 } 632 633 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 634 return -EINVAL; 635 636 spin_lock_irqsave(&sih_agent_lock, flags); 637 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { 638 desc->status &= ~IRQ_TYPE_SENSE_MASK; 639 desc->status |= trigger; 640 sih->edge_change |= BIT(irq - sih->irq_base); 641 queue_work(wq, &sih->edge_work); 642 } 643 spin_unlock_irqrestore(&sih_agent_lock, flags); 644 return 0; 645} 646 647static struct irq_chip twl4030_sih_irq_chip = { 648 .name = "twl4030", 649 .mask = twl4030_sih_mask, 650 .unmask = twl4030_sih_unmask, 651 .set_type = twl4030_sih_set_type, 652}; 653 654/*----------------------------------------------------------------------*/ 655 656static inline int sih_read_isr(const struct sih *sih) 657{ 658 int status; 659 union { 660 u8 bytes[4]; 661 u32 word; 662 } isr; 663 664 /* FIXME need retry-on-error ... */ 665 666 isr.word = 0; 667 status = twl_i2c_read(sih->module, isr.bytes, 668 sih->mask[irq_line].isr_offset, sih->bytes_ixr); 669 670 return (status < 0) ? status : le32_to_cpu(isr.word); 671} 672 673/* 674 * Generic handler for SIH interrupts ... we "know" this is called 675 * in task context, with IRQs enabled. 676 */ 677static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 678{ 679 struct sih_agent *agent = get_irq_data(irq); 680 const struct sih *sih = agent->sih; 681 int isr; 682 683 /* reading ISR acks the IRQs, using clear-on-read mode */ 684 local_irq_enable(); 685 isr = sih_read_isr(sih); 686 local_irq_disable(); 687 688 if (isr < 0) { 689 pr_err("twl4030: %s SIH, read ISR error %d\n", 690 sih->name, isr); 691 /* REVISIT: recover; eventually mask it all, etc */ 692 return; 693 } 694 695 while (isr) { 696 irq = fls(isr); 697 irq--; 698 isr &= ~BIT(irq); 699 700 if (irq < sih->bits) 701 generic_handle_irq(agent->irq_base + irq); 702 else 703 pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 704 sih->name, irq); 705 } 706} 707 708static unsigned twl4030_irq_next; 709 710/* returns the first IRQ used by this SIH bank, 711 * or negative errno 712 */ 713int twl4030_sih_setup(int module) 714{ 715 int sih_mod; 716 const struct sih *sih = NULL; 717 struct sih_agent *agent; 718 int i, irq; 719 int status = -EINVAL; 720 unsigned irq_base = twl4030_irq_next; 721 722 /* only support modules with standard clear-on-read for now */ 723 for (sih_mod = 0, sih = sih_modules; 724 sih_mod < nr_sih_modules; 725 sih_mod++, sih++) { 726 if (sih->module == module && sih->set_cor) { 727 if (!WARN((irq_base + sih->bits) > NR_IRQS, 728 "irq %d for %s too big\n", 729 irq_base + sih->bits, 730 sih->name)) 731 status = 0; 732 break; 733 } 734 } 735 if (status < 0) 736 return status; 737 738 agent = kzalloc(sizeof *agent, GFP_KERNEL); 739 if (!agent) 740 return -ENOMEM; 741 742 status = 0; 743 744 agent->irq_base = irq_base; 745 agent->sih = sih; 746 agent->imr = ~0; 747 INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); 748 INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); 749 750 for (i = 0; i < sih->bits; i++) { 751 irq = irq_base + i; 752 753 set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, 754 handle_edge_irq); 755 set_irq_chip_data(irq, agent); 756 activate_irq(irq); 757 } 758 759 status = irq_base; 760 twl4030_irq_next += i; 761 762 /* replace generic PIH handler (handle_simple_irq) */ 763 irq = sih_mod + twl4030_irq_base; 764 set_irq_data(irq, agent); 765 set_irq_chained_handler(irq, handle_twl4030_sih); 766 767 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 768 irq, irq_base, twl4030_irq_next - 1); 769 770 return status; 771} 772 773/* FIXME need a call to reverse twl4030_sih_setup() ... */ 774 775 776/*----------------------------------------------------------------------*/ 777 778/* FIXME pass in which interrupt line we'll use ... */ 779#define twl_irq_line 0 780 781int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 782{ 783 static struct irq_chip twl4030_irq_chip; 784 785 int status; 786 int i; 787 struct task_struct *task; 788 789 /* 790 * Mask and clear all TWL4030 interrupts since initially we do 791 * not have any TWL4030 module interrupt handlers present 792 */ 793 status = twl4030_init_sih_modules(twl_irq_line); 794 if (status < 0) 795 return status; 796 797 wq = create_singlethread_workqueue("twl4030-irqchip"); 798 if (!wq) { 799 pr_err("twl4030: workqueue FAIL\n"); 800 return -ESRCH; 801 } 802 803 twl4030_irq_base = irq_base; 804 805 /* install an irq handler for each of the SIH modules; 806 * clone dummy irq_chip since PIH can't *do* anything 807 */ 808 twl4030_irq_chip = dummy_irq_chip; 809 twl4030_irq_chip.name = "twl4030"; 810 811 twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; 812 813 for (i = irq_base; i < irq_end; i++) { 814 set_irq_chip_and_handler(i, &twl4030_irq_chip, 815 handle_simple_irq); 816 activate_irq(i); 817 } 818 twl4030_irq_next = i; 819 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 820 irq_num, irq_base, twl4030_irq_next - 1); 821 822 /* ... and the PWR_INT module ... */ 823 status = twl4030_sih_setup(TWL4030_MODULE_INT); 824 if (status < 0) { 825 pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 826 goto fail; 827 } 828 829 /* install an irq handler to demultiplex the TWL4030 interrupt */ 830 831 832 init_completion(&irq_event); 833 834 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, 835 "TWL4030-PIH", &irq_event); 836 if (status < 0) { 837 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); 838 goto fail_rqirq; 839 } 840 841 task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num, 842 "twl4030-irq"); 843 if (IS_ERR(task)) { 844 pr_err("twl4030: could not create irq %d thread!\n", irq_num); 845 status = PTR_ERR(task); 846 goto fail_kthread; 847 } 848 return status; 849fail_kthread: 850 free_irq(irq_num, &irq_event); 851fail_rqirq: 852 /* clean up twl4030_sih_setup */ 853fail: 854 for (i = irq_base; i < irq_end; i++) 855 set_irq_chip_and_handler(i, NULL, NULL); 856 destroy_workqueue(wq); 857 wq = NULL; 858 return status; 859} 860 861int twl_exit_irq(void) 862{ 863 /* FIXME undo twl_init_irq() */ 864 if (twl4030_irq_base) { 865 pr_err("twl4030: can't yet clean up IRQs?\n"); 866 return -ENOSYS; 867 } 868 return 0; 869} 870 871int twl_init_chip_irq(const char *chip) 872{ 873 if (!strcmp(chip, "twl5031")) { 874 sih_modules = sih_modules_twl5031; 875 nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); 876 } else { 877 sih_modules = sih_modules_twl4030; 878 nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); 879 } 880 881 return 0; 882} 883