wm831x-irq.c revision ca7a71824ac957b1b9d3322656c05aad38d7275c 
1/*
2 * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *  This program is free software; you can redistribute  it and/or modify it
9 *  under  the terms of  the GNU General  Public License as published by the
10 *  Free Software Foundation;  either version 2 of the  License, or (at your
11 *  option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/mfd/core.h>
20#include <linux/interrupt.h>
21
22#include <linux/mfd/wm831x/core.h>
23#include <linux/mfd/wm831x/pdata.h>
24#include <linux/mfd/wm831x/gpio.h>
25#include <linux/mfd/wm831x/irq.h>
26
27#include <linux/delay.h>
28
29struct wm831x_irq_data {
30	int primary;
31	int reg;
32	int mask;
33};
34
35static struct wm831x_irq_data wm831x_irqs[] = {
36	[WM831X_IRQ_TEMP_THW] = {
37		.primary = WM831X_TEMP_INT,
38		.reg = 1,
39		.mask = WM831X_TEMP_THW_EINT,
40	},
41	[WM831X_IRQ_GPIO_1] = {
42		.primary = WM831X_GP_INT,
43		.reg = 5,
44		.mask = WM831X_GP1_EINT,
45	},
46	[WM831X_IRQ_GPIO_2] = {
47		.primary = WM831X_GP_INT,
48		.reg = 5,
49		.mask = WM831X_GP2_EINT,
50	},
51	[WM831X_IRQ_GPIO_3] = {
52		.primary = WM831X_GP_INT,
53		.reg = 5,
54		.mask = WM831X_GP3_EINT,
55	},
56	[WM831X_IRQ_GPIO_4] = {
57		.primary = WM831X_GP_INT,
58		.reg = 5,
59		.mask = WM831X_GP4_EINT,
60	},
61	[WM831X_IRQ_GPIO_5] = {
62		.primary = WM831X_GP_INT,
63		.reg = 5,
64		.mask = WM831X_GP5_EINT,
65	},
66	[WM831X_IRQ_GPIO_6] = {
67		.primary = WM831X_GP_INT,
68		.reg = 5,
69		.mask = WM831X_GP6_EINT,
70	},
71	[WM831X_IRQ_GPIO_7] = {
72		.primary = WM831X_GP_INT,
73		.reg = 5,
74		.mask = WM831X_GP7_EINT,
75	},
76	[WM831X_IRQ_GPIO_8] = {
77		.primary = WM831X_GP_INT,
78		.reg = 5,
79		.mask = WM831X_GP8_EINT,
80	},
81	[WM831X_IRQ_GPIO_9] = {
82		.primary = WM831X_GP_INT,
83		.reg = 5,
84		.mask = WM831X_GP9_EINT,
85	},
86	[WM831X_IRQ_GPIO_10] = {
87		.primary = WM831X_GP_INT,
88		.reg = 5,
89		.mask = WM831X_GP10_EINT,
90	},
91	[WM831X_IRQ_GPIO_11] = {
92		.primary = WM831X_GP_INT,
93		.reg = 5,
94		.mask = WM831X_GP11_EINT,
95	},
96	[WM831X_IRQ_GPIO_12] = {
97		.primary = WM831X_GP_INT,
98		.reg = 5,
99		.mask = WM831X_GP12_EINT,
100	},
101	[WM831X_IRQ_GPIO_13] = {
102		.primary = WM831X_GP_INT,
103		.reg = 5,
104		.mask = WM831X_GP13_EINT,
105	},
106	[WM831X_IRQ_GPIO_14] = {
107		.primary = WM831X_GP_INT,
108		.reg = 5,
109		.mask = WM831X_GP14_EINT,
110	},
111	[WM831X_IRQ_GPIO_15] = {
112		.primary = WM831X_GP_INT,
113		.reg = 5,
114		.mask = WM831X_GP15_EINT,
115	},
116	[WM831X_IRQ_GPIO_16] = {
117		.primary = WM831X_GP_INT,
118		.reg = 5,
119		.mask = WM831X_GP16_EINT,
120	},
121	[WM831X_IRQ_ON] = {
122		.primary = WM831X_ON_PIN_INT,
123		.reg = 1,
124		.mask = WM831X_ON_PIN_EINT,
125	},
126	[WM831X_IRQ_PPM_SYSLO] = {
127		.primary = WM831X_PPM_INT,
128		.reg = 1,
129		.mask = WM831X_PPM_SYSLO_EINT,
130	},
131	[WM831X_IRQ_PPM_PWR_SRC] = {
132		.primary = WM831X_PPM_INT,
133		.reg = 1,
134		.mask = WM831X_PPM_PWR_SRC_EINT,
135	},
136	[WM831X_IRQ_PPM_USB_CURR] = {
137		.primary = WM831X_PPM_INT,
138		.reg = 1,
139		.mask = WM831X_PPM_USB_CURR_EINT,
140	},
141	[WM831X_IRQ_WDOG_TO] = {
142		.primary = WM831X_WDOG_INT,
143		.reg = 1,
144		.mask = WM831X_WDOG_TO_EINT,
145	},
146	[WM831X_IRQ_RTC_PER] = {
147		.primary = WM831X_RTC_INT,
148		.reg = 1,
149		.mask = WM831X_RTC_PER_EINT,
150	},
151	[WM831X_IRQ_RTC_ALM] = {
152		.primary = WM831X_RTC_INT,
153		.reg = 1,
154		.mask = WM831X_RTC_ALM_EINT,
155	},
156	[WM831X_IRQ_CHG_BATT_HOT] = {
157		.primary = WM831X_CHG_INT,
158		.reg = 2,
159		.mask = WM831X_CHG_BATT_HOT_EINT,
160	},
161	[WM831X_IRQ_CHG_BATT_COLD] = {
162		.primary = WM831X_CHG_INT,
163		.reg = 2,
164		.mask = WM831X_CHG_BATT_COLD_EINT,
165	},
166	[WM831X_IRQ_CHG_BATT_FAIL] = {
167		.primary = WM831X_CHG_INT,
168		.reg = 2,
169		.mask = WM831X_CHG_BATT_FAIL_EINT,
170	},
171	[WM831X_IRQ_CHG_OV] = {
172		.primary = WM831X_CHG_INT,
173		.reg = 2,
174		.mask = WM831X_CHG_OV_EINT,
175	},
176	[WM831X_IRQ_CHG_END] = {
177		.primary = WM831X_CHG_INT,
178		.reg = 2,
179		.mask = WM831X_CHG_END_EINT,
180	},
181	[WM831X_IRQ_CHG_TO] = {
182		.primary = WM831X_CHG_INT,
183		.reg = 2,
184		.mask = WM831X_CHG_TO_EINT,
185	},
186	[WM831X_IRQ_CHG_MODE] = {
187		.primary = WM831X_CHG_INT,
188		.reg = 2,
189		.mask = WM831X_CHG_MODE_EINT,
190	},
191	[WM831X_IRQ_CHG_START] = {
192		.primary = WM831X_CHG_INT,
193		.reg = 2,
194		.mask = WM831X_CHG_START_EINT,
195	},
196	[WM831X_IRQ_TCHDATA] = {
197		.primary = WM831X_TCHDATA_INT,
198		.reg = 1,
199		.mask = WM831X_TCHDATA_EINT,
200	},
201	[WM831X_IRQ_TCHPD] = {
202		.primary = WM831X_TCHPD_INT,
203		.reg = 1,
204		.mask = WM831X_TCHPD_EINT,
205	},
206	[WM831X_IRQ_AUXADC_DATA] = {
207		.primary = WM831X_AUXADC_INT,
208		.reg = 1,
209		.mask = WM831X_AUXADC_DATA_EINT,
210	},
211	[WM831X_IRQ_AUXADC_DCOMP1] = {
212		.primary = WM831X_AUXADC_INT,
213		.reg = 1,
214		.mask = WM831X_AUXADC_DCOMP1_EINT,
215	},
216	[WM831X_IRQ_AUXADC_DCOMP2] = {
217		.primary = WM831X_AUXADC_INT,
218		.reg = 1,
219		.mask = WM831X_AUXADC_DCOMP2_EINT,
220	},
221	[WM831X_IRQ_AUXADC_DCOMP3] = {
222		.primary = WM831X_AUXADC_INT,
223		.reg = 1,
224		.mask = WM831X_AUXADC_DCOMP3_EINT,
225	},
226	[WM831X_IRQ_AUXADC_DCOMP4] = {
227		.primary = WM831X_AUXADC_INT,
228		.reg = 1,
229		.mask = WM831X_AUXADC_DCOMP4_EINT,
230	},
231	[WM831X_IRQ_CS1] = {
232		.primary = WM831X_CS_INT,
233		.reg = 2,
234		.mask = WM831X_CS1_EINT,
235	},
236	[WM831X_IRQ_CS2] = {
237		.primary = WM831X_CS_INT,
238		.reg = 2,
239		.mask = WM831X_CS2_EINT,
240	},
241	[WM831X_IRQ_HC_DC1] = {
242		.primary = WM831X_HC_INT,
243		.reg = 4,
244		.mask = WM831X_HC_DC1_EINT,
245	},
246	[WM831X_IRQ_HC_DC2] = {
247		.primary = WM831X_HC_INT,
248		.reg = 4,
249		.mask = WM831X_HC_DC2_EINT,
250	},
251	[WM831X_IRQ_UV_LDO1] = {
252		.primary = WM831X_UV_INT,
253		.reg = 3,
254		.mask = WM831X_UV_LDO1_EINT,
255	},
256	[WM831X_IRQ_UV_LDO2] = {
257		.primary = WM831X_UV_INT,
258		.reg = 3,
259		.mask = WM831X_UV_LDO2_EINT,
260	},
261	[WM831X_IRQ_UV_LDO3] = {
262		.primary = WM831X_UV_INT,
263		.reg = 3,
264		.mask = WM831X_UV_LDO3_EINT,
265	},
266	[WM831X_IRQ_UV_LDO4] = {
267		.primary = WM831X_UV_INT,
268		.reg = 3,
269		.mask = WM831X_UV_LDO4_EINT,
270	},
271	[WM831X_IRQ_UV_LDO5] = {
272		.primary = WM831X_UV_INT,
273		.reg = 3,
274		.mask = WM831X_UV_LDO5_EINT,
275	},
276	[WM831X_IRQ_UV_LDO6] = {
277		.primary = WM831X_UV_INT,
278		.reg = 3,
279		.mask = WM831X_UV_LDO6_EINT,
280	},
281	[WM831X_IRQ_UV_LDO7] = {
282		.primary = WM831X_UV_INT,
283		.reg = 3,
284		.mask = WM831X_UV_LDO7_EINT,
285	},
286	[WM831X_IRQ_UV_LDO8] = {
287		.primary = WM831X_UV_INT,
288		.reg = 3,
289		.mask = WM831X_UV_LDO8_EINT,
290	},
291	[WM831X_IRQ_UV_LDO9] = {
292		.primary = WM831X_UV_INT,
293		.reg = 3,
294		.mask = WM831X_UV_LDO9_EINT,
295	},
296	[WM831X_IRQ_UV_LDO10] = {
297		.primary = WM831X_UV_INT,
298		.reg = 3,
299		.mask = WM831X_UV_LDO10_EINT,
300	},
301	[WM831X_IRQ_UV_DC1] = {
302		.primary = WM831X_UV_INT,
303		.reg = 4,
304		.mask = WM831X_UV_DC1_EINT,
305	},
306	[WM831X_IRQ_UV_DC2] = {
307		.primary = WM831X_UV_INT,
308		.reg = 4,
309		.mask = WM831X_UV_DC2_EINT,
310	},
311	[WM831X_IRQ_UV_DC3] = {
312		.primary = WM831X_UV_INT,
313		.reg = 4,
314		.mask = WM831X_UV_DC3_EINT,
315	},
316	[WM831X_IRQ_UV_DC4] = {
317		.primary = WM831X_UV_INT,
318		.reg = 4,
319		.mask = WM831X_UV_DC4_EINT,
320	},
321};
322
323static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
324{
325	return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
326}
327
328static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
329{
330	return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
331}
332
333static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
334							int irq)
335{
336	return &wm831x_irqs[irq - wm831x->irq_base];
337}
338
339static void wm831x_irq_lock(struct irq_data *data)
340{
341	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
342
343	mutex_lock(&wm831x->irq_lock);
344}
345
346static void wm831x_irq_sync_unlock(struct irq_data *data)
347{
348	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
349	int i;
350
351	for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
352		if (wm831x->gpio_update[i]) {
353			wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
354					WM831X_GPN_INT_MODE | WM831X_GPN_POL,
355					wm831x->gpio_update[i]);
356			wm831x->gpio_update[i] = 0;
357		}
358	}
359
360	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
361		/* If there's been a change in the mask write it back
362		 * to the hardware. */
363		if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
364			dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
365				WM831X_INTERRUPT_STATUS_1_MASK + i,
366				wm831x->irq_masks_cur[i]);
367
368			wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
369			wm831x_reg_write(wm831x,
370					 WM831X_INTERRUPT_STATUS_1_MASK + i,
371					 wm831x->irq_masks_cur[i]);
372		}
373	}
374
375	mutex_unlock(&wm831x->irq_lock);
376}
377
378static void wm831x_irq_enable(struct irq_data *data)
379{
380	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
381	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
382							     data->irq);
383
384	wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
385}
386
387static void wm831x_irq_disable(struct irq_data *data)
388{
389	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
390	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
391							     data->irq);
392
393	wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
394}
395
396static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
397{
398	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
399	int irq;
400
401	irq = data->irq - wm831x->irq_base;
402
403	if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
404		/* Ignore internal-only IRQs */
405		if (irq >= 0 && irq < WM831X_NUM_IRQS)
406			return 0;
407		else
408			return -EINVAL;
409	}
410
411	/* We set the high bit to flag that we need an update; don't
412	 * do the update here as we can be called with the bus lock
413	 * held.
414	 */
415	switch (type) {
416	case IRQ_TYPE_EDGE_BOTH:
417		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
418		break;
419	case IRQ_TYPE_EDGE_RISING:
420		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
421		break;
422	case IRQ_TYPE_EDGE_FALLING:
423		wm831x->gpio_update[irq] = 0x10000;
424		break;
425	default:
426		return -EINVAL;
427	}
428
429	return 0;
430}
431
432static struct irq_chip wm831x_irq_chip = {
433	.name			= "wm831x",
434	.irq_bus_lock		= wm831x_irq_lock,
435	.irq_bus_sync_unlock	= wm831x_irq_sync_unlock,
436	.irq_disable		= wm831x_irq_disable,
437	.irq_enable		= wm831x_irq_enable,
438	.irq_set_type		= wm831x_irq_set_type,
439};
440
441/* The processing of the primary interrupt occurs in a thread so that
442 * we can interact with the device over I2C or SPI. */
443static irqreturn_t wm831x_irq_thread(int irq, void *data)
444{
445	struct wm831x *wm831x = data;
446	unsigned int i;
447	int primary;
448	int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
449	int read[WM831X_NUM_IRQ_REGS] = { 0 };
450	int *status;
451
452	primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
453	if (primary < 0) {
454		dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
455			primary);
456		goto out;
457	}
458
459	/* The touch interrupts are visible in the primary register as
460	 * an optimisation; open code this to avoid complicating the
461	 * main handling loop and so we can also skip iterating the
462	 * descriptors.
463	 */
464	if (primary & WM831X_TCHPD_INT)
465		handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
466	if (primary & WM831X_TCHDATA_INT)
467		handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
468	if (primary & (WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT))
469		goto out;
470
471	for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
472		int offset = wm831x_irqs[i].reg - 1;
473
474		if (!(primary & wm831x_irqs[i].primary))
475			continue;
476
477		status = &status_regs[offset];
478
479		/* Hopefully there should only be one register to read
480		 * each time otherwise we ought to do a block read. */
481		if (!read[offset]) {
482			*status = wm831x_reg_read(wm831x,
483				     irq_data_to_status_reg(&wm831x_irqs[i]));
484			if (*status < 0) {
485				dev_err(wm831x->dev,
486					"Failed to read IRQ status: %d\n",
487					*status);
488				goto out;
489			}
490
491			read[offset] = 1;
492		}
493
494		/* Report it if it isn't masked, or forget the status. */
495		if ((*status & ~wm831x->irq_masks_cur[offset])
496		    & wm831x_irqs[i].mask)
497			handle_nested_irq(wm831x->irq_base + i);
498		else
499			*status &= ~wm831x_irqs[i].mask;
500	}
501
502out:
503	/* Touchscreen interrupts are handled specially in the driver */
504	status_regs[0] &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
505
506	for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
507		if (status_regs[i])
508			wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
509					 status_regs[i]);
510	}
511
512	return IRQ_HANDLED;
513}
514
515int wm831x_irq_init(struct wm831x *wm831x, int irq)
516{
517	struct wm831x_pdata *pdata = wm831x->dev->platform_data;
518	int i, cur_irq, ret;
519
520	mutex_init(&wm831x->irq_lock);
521
522	/* Mask the individual interrupt sources */
523	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
524		wm831x->irq_masks_cur[i] = 0xffff;
525		wm831x->irq_masks_cache[i] = 0xffff;
526		wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
527				 0xffff);
528	}
529
530	if (!pdata || !pdata->irq_base) {
531		dev_err(wm831x->dev,
532			"No interrupt base specified, no interrupts\n");
533		return 0;
534	}
535
536	if (pdata->irq_cmos)
537		i = 0;
538	else
539		i = WM831X_IRQ_OD;
540
541	wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
542			WM831X_IRQ_OD, i);
543
544	/* Try to flag /IRQ as a wake source; there are a number of
545	 * unconditional wake sources in the PMIC so this isn't
546	 * conditional but we don't actually care *too* much if it
547	 * fails.
548	 */
549	ret = enable_irq_wake(irq);
550	if (ret != 0) {
551		dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
552			 ret);
553	}
554
555	wm831x->irq = irq;
556	wm831x->irq_base = pdata->irq_base;
557
558	/* Register them with genirq */
559	for (cur_irq = wm831x->irq_base;
560	     cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
561	     cur_irq++) {
562		irq_set_chip_data(cur_irq, wm831x);
563		irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
564					 handle_edge_irq);
565		irq_set_nested_thread(cur_irq, 1);
566
567		/* ARM needs us to explicitly flag the IRQ as valid
568		 * and will set them noprobe when we do so. */
569#ifdef CONFIG_ARM
570		set_irq_flags(cur_irq, IRQF_VALID);
571#else
572		irq_set_noprobe(cur_irq);
573#endif
574	}
575
576	if (irq) {
577		ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
578					   IRQF_TRIGGER_LOW | IRQF_ONESHOT,
579					   "wm831x", wm831x);
580		if (ret != 0) {
581			dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
582				irq, ret);
583			return ret;
584		}
585	} else {
586		dev_warn(wm831x->dev,
587			 "No interrupt specified - functionality limited\n");
588	}
589
590
591
592	/* Enable top level interrupts, we mask at secondary level */
593	wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
594
595	return 0;
596}
597
598void wm831x_irq_exit(struct wm831x *wm831x)
599{
600	if (wm831x->irq)
601		free_irq(wm831x->irq, wm831x);
602}
603