pci-me.c revision e13fa90ce42d8e7ee501426ea414c8ae4a5366ef 
1/*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 */
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/fs.h>
21#include <linux/errno.h>
22#include <linux/types.h>
23#include <linux/fcntl.h>
24#include <linux/aio.h>
25#include <linux/pci.h>
26#include <linux/poll.h>
27#include <linux/ioctl.h>
28#include <linux/cdev.h>
29#include <linux/sched.h>
30#include <linux/uuid.h>
31#include <linux/compat.h>
32#include <linux/jiffies.h>
33#include <linux/interrupt.h>
34#include <linux/miscdevice.h>
35
36#include <linux/pm_runtime.h>
37
38#include <linux/mei.h>
39
40#include "mei_dev.h"
41#include "client.h"
42#include "hw-me-regs.h"
43#include "hw-me.h"
44
45/* mei_pci_tbl - PCI Device ID Table */
46static const struct pci_device_id mei_me_pci_tbl[] = {
47	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
48	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
49	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
50	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
51	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
52	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
53	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
54	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
55	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
56	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
57	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
58	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
59	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
60	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
61	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
62	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
63	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
64	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
65	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
66	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
67	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
68	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
69	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
70	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
71	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
72	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
73	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
74	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
75	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
76	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
77	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
78	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_H)},
79	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_W)},
80	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_LP)},
81	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_LPT_HR)},
82	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_WPT_LP)},
83
84	/* required last entry */
85	{0, }
86};
87
88MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
89
90#ifdef CONFIG_PM_RUNTIME
91static inline void mei_me_set_pm_domain(struct mei_device *dev);
92static inline void mei_me_unset_pm_domain(struct mei_device *dev);
93#else
94static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
95static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
96#endif /* CONFIG_PM_RUNTIME */
97
98/**
99 * mei_quirk_probe - probe for devices that doesn't valid ME interface
100 *
101 * @pdev: PCI device structure
102 * @ent: entry into pci_device_table
103 *
104 * returns true if ME Interface is valid, false otherwise
105 */
106static bool mei_me_quirk_probe(struct pci_dev *pdev,
107				const struct pci_device_id *ent)
108{
109	u32 reg;
110	/* Cougar Point || Patsburg */
111	if (ent->device == MEI_DEV_ID_CPT_1 ||
112	    ent->device == MEI_DEV_ID_PBG_1) {
113		pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
114		/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
115		if ((reg & 0x600) == 0x200)
116			goto no_mei;
117	}
118
119	/* Lynx Point */
120	if (ent->device == MEI_DEV_ID_LPT_H  ||
121	    ent->device == MEI_DEV_ID_LPT_W  ||
122	    ent->device == MEI_DEV_ID_LPT_HR) {
123		/* Read ME FW Status check for SPS Firmware */
124		pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
125		/* if bits [19:16] = 15, running SPS Firmware */
126		if ((reg & 0xf0000) == 0xf0000)
127			goto no_mei;
128	}
129
130	return true;
131
132no_mei:
133	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
134	return false;
135}
136/**
137 * mei_probe - Device Initialization Routine
138 *
139 * @pdev: PCI device structure
140 * @ent: entry in kcs_pci_tbl
141 *
142 * returns 0 on success, <0 on failure.
143 */
144static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
145{
146	struct mei_device *dev;
147	struct mei_me_hw *hw;
148	int err;
149
150
151	if (!mei_me_quirk_probe(pdev, ent)) {
152		err = -ENODEV;
153		goto end;
154	}
155
156	/* enable pci dev */
157	err = pci_enable_device(pdev);
158	if (err) {
159		dev_err(&pdev->dev, "failed to enable pci device.\n");
160		goto end;
161	}
162	/* set PCI host mastering  */
163	pci_set_master(pdev);
164	/* pci request regions for mei driver */
165	err = pci_request_regions(pdev, KBUILD_MODNAME);
166	if (err) {
167		dev_err(&pdev->dev, "failed to get pci regions.\n");
168		goto disable_device;
169	}
170
171	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
172	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
173
174		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
175		if (err)
176			err = dma_set_coherent_mask(&pdev->dev,
177						    DMA_BIT_MASK(32));
178	}
179	if (err) {
180		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
181		goto release_regions;
182	}
183
184
185	/* allocates and initializes the mei dev structure */
186	dev = mei_me_dev_init(pdev);
187	if (!dev) {
188		err = -ENOMEM;
189		goto release_regions;
190	}
191	hw = to_me_hw(dev);
192	/* mapping  IO device memory */
193	hw->mem_addr = pci_iomap(pdev, 0, 0);
194	if (!hw->mem_addr) {
195		dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
196		err = -ENOMEM;
197		goto free_device;
198	}
199	pci_enable_msi(pdev);
200
201	 /* request and enable interrupt */
202	if (pci_dev_msi_enabled(pdev))
203		err = request_threaded_irq(pdev->irq,
204			NULL,
205			mei_me_irq_thread_handler,
206			IRQF_ONESHOT, KBUILD_MODNAME, dev);
207	else
208		err = request_threaded_irq(pdev->irq,
209			mei_me_irq_quick_handler,
210			mei_me_irq_thread_handler,
211			IRQF_SHARED, KBUILD_MODNAME, dev);
212
213	if (err) {
214		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
215		       pdev->irq);
216		goto disable_msi;
217	}
218
219	if (mei_start(dev)) {
220		dev_err(&pdev->dev, "init hw failure.\n");
221		err = -ENODEV;
222		goto release_irq;
223	}
224
225	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
226	pm_runtime_use_autosuspend(&pdev->dev);
227
228	err = mei_register(dev);
229	if (err)
230		goto release_irq;
231
232	pci_set_drvdata(pdev, dev);
233
234	schedule_delayed_work(&dev->timer_work, HZ);
235
236	/*
237	* For not wake-able HW runtime pm framework
238	* can't be used on pci device level.
239	* Use domain runtime pm callbacks instead.
240	*/
241	if (!pci_dev_run_wake(pdev))
242		mei_me_set_pm_domain(dev);
243
244	if (mei_pg_is_enabled(dev))
245		pm_runtime_put_noidle(&pdev->dev);
246
247	dev_dbg(&pdev->dev, "initialization successful.\n");
248
249	return 0;
250
251release_irq:
252	mei_cancel_work(dev);
253	mei_disable_interrupts(dev);
254	free_irq(pdev->irq, dev);
255disable_msi:
256	pci_disable_msi(pdev);
257	pci_iounmap(pdev, hw->mem_addr);
258free_device:
259	kfree(dev);
260release_regions:
261	pci_release_regions(pdev);
262disable_device:
263	pci_disable_device(pdev);
264end:
265	dev_err(&pdev->dev, "initialization failed.\n");
266	return err;
267}
268
269/**
270 * mei_remove - Device Removal Routine
271 *
272 * @pdev: PCI device structure
273 *
274 * mei_remove is called by the PCI subsystem to alert the driver
275 * that it should release a PCI device.
276 */
277static void mei_me_remove(struct pci_dev *pdev)
278{
279	struct mei_device *dev;
280	struct mei_me_hw *hw;
281
282	dev = pci_get_drvdata(pdev);
283	if (!dev)
284		return;
285
286	if (mei_pg_is_enabled(dev))
287		pm_runtime_get_noresume(&pdev->dev);
288
289	hw = to_me_hw(dev);
290
291
292	dev_dbg(&pdev->dev, "stop\n");
293	mei_stop(dev);
294
295	if (!pci_dev_run_wake(pdev))
296		mei_me_unset_pm_domain(dev);
297
298	/* disable interrupts */
299	mei_disable_interrupts(dev);
300
301	free_irq(pdev->irq, dev);
302	pci_disable_msi(pdev);
303
304	if (hw->mem_addr)
305		pci_iounmap(pdev, hw->mem_addr);
306
307	mei_deregister(dev);
308
309	kfree(dev);
310
311	pci_release_regions(pdev);
312	pci_disable_device(pdev);
313
314
315}
316#ifdef CONFIG_PM_SLEEP
317static int mei_me_pci_suspend(struct device *device)
318{
319	struct pci_dev *pdev = to_pci_dev(device);
320	struct mei_device *dev = pci_get_drvdata(pdev);
321
322	if (!dev)
323		return -ENODEV;
324
325	dev_dbg(&pdev->dev, "suspend\n");
326
327	mei_stop(dev);
328
329	mei_disable_interrupts(dev);
330
331	free_irq(pdev->irq, dev);
332	pci_disable_msi(pdev);
333
334	return 0;
335}
336
337static int mei_me_pci_resume(struct device *device)
338{
339	struct pci_dev *pdev = to_pci_dev(device);
340	struct mei_device *dev;
341	int err;
342
343	dev = pci_get_drvdata(pdev);
344	if (!dev)
345		return -ENODEV;
346
347	pci_enable_msi(pdev);
348
349	/* request and enable interrupt */
350	if (pci_dev_msi_enabled(pdev))
351		err = request_threaded_irq(pdev->irq,
352			NULL,
353			mei_me_irq_thread_handler,
354			IRQF_ONESHOT, KBUILD_MODNAME, dev);
355	else
356		err = request_threaded_irq(pdev->irq,
357			mei_me_irq_quick_handler,
358			mei_me_irq_thread_handler,
359			IRQF_SHARED, KBUILD_MODNAME, dev);
360
361	if (err) {
362		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
363				pdev->irq);
364		return err;
365	}
366
367	err = mei_restart(dev);
368	if (err)
369		return err;
370
371	/* Start timer if stopped in suspend */
372	schedule_delayed_work(&dev->timer_work, HZ);
373
374	return 0;
375}
376#endif /* CONFIG_PM_SLEEP */
377
378#ifdef CONFIG_PM_RUNTIME
379static int mei_me_pm_runtime_idle(struct device *device)
380{
381	struct pci_dev *pdev = to_pci_dev(device);
382	struct mei_device *dev;
383
384	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
385
386	dev = pci_get_drvdata(pdev);
387	if (!dev)
388		return -ENODEV;
389	if (mei_write_is_idle(dev))
390		pm_schedule_suspend(device, MEI_ME_RPM_TIMEOUT * 2);
391
392	return -EBUSY;
393}
394
395static int mei_me_pm_runtime_suspend(struct device *device)
396{
397	struct pci_dev *pdev = to_pci_dev(device);
398	struct mei_device *dev;
399	int ret;
400
401	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
402
403	dev = pci_get_drvdata(pdev);
404	if (!dev)
405		return -ENODEV;
406
407	mutex_lock(&dev->device_lock);
408
409	if (mei_write_is_idle(dev))
410		ret = mei_me_pg_set_sync(dev);
411	else
412		ret = -EAGAIN;
413
414	mutex_unlock(&dev->device_lock);
415
416	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
417
418	return ret;
419}
420
421static int mei_me_pm_runtime_resume(struct device *device)
422{
423	struct pci_dev *pdev = to_pci_dev(device);
424	struct mei_device *dev;
425	int ret;
426
427	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
428
429	dev = pci_get_drvdata(pdev);
430	if (!dev)
431		return -ENODEV;
432
433	mutex_lock(&dev->device_lock);
434
435	ret = mei_me_pg_unset_sync(dev);
436
437	mutex_unlock(&dev->device_lock);
438
439	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
440
441	return ret;
442}
443
444/**
445 * mei_me_set_pm_domain - fill and set pm domian stucture for device
446 *
447 * @dev: mei_device
448 */
449static inline void mei_me_set_pm_domain(struct mei_device *dev)
450{
451	struct pci_dev *pdev  = dev->pdev;
452
453	if (pdev->dev.bus && pdev->dev.bus->pm) {
454		dev->pg_domain.ops = *pdev->dev.bus->pm;
455
456		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
457		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
458		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
459
460		pdev->dev.pm_domain = &dev->pg_domain;
461	}
462}
463
464/**
465 * mei_me_unset_pm_domain - clean pm domian stucture for device
466 *
467 * @dev: mei_device
468 */
469static inline void mei_me_unset_pm_domain(struct mei_device *dev)
470{
471	/* stop using pm callbacks if any */
472	dev->pdev->dev.pm_domain = NULL;
473}
474#endif /* CONFIG_PM_RUNTIME */
475
476#ifdef CONFIG_PM
477static const struct dev_pm_ops mei_me_pm_ops = {
478	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
479				mei_me_pci_resume)
480	SET_RUNTIME_PM_OPS(
481		mei_me_pm_runtime_suspend,
482		mei_me_pm_runtime_resume,
483		mei_me_pm_runtime_idle)
484};
485
486#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
487#else
488#define MEI_ME_PM_OPS	NULL
489#endif /* CONFIG_PM */
490/*
491 *  PCI driver structure
492 */
493static struct pci_driver mei_me_driver = {
494	.name = KBUILD_MODNAME,
495	.id_table = mei_me_pci_tbl,
496	.probe = mei_me_probe,
497	.remove = mei_me_remove,
498	.shutdown = mei_me_remove,
499	.driver.pm = MEI_ME_PM_OPS,
500};
501
502module_pci_driver(mei_me_driver);
503
504MODULE_AUTHOR("Intel Corporation");
505MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
506MODULE_LICENSE("GPL v2");
507