pch_phub.c revision 25b8a88c10770e8c3f14bf2e222691dc6e79de78
1/* 2 * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/types.h> 21#include <linux/fs.h> 22#include <linux/uaccess.h> 23#include <linux/string.h> 24#include <linux/pci.h> 25#include <linux/io.h> 26#include <linux/delay.h> 27#include <linux/mutex.h> 28#include <linux/if_ether.h> 29#include <linux/ctype.h> 30#include <linux/dmi.h> 31 32#define PHUB_STATUS 0x00 /* Status Register offset */ 33#define PHUB_CONTROL 0x04 /* Control Register offset */ 34#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 35#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 36#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 37#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 38 offset */ 39#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 40 offset */ 41#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 42 (Intel EG20T PCH)*/ 43#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 44 offset(OKI SEMICONDUCTOR ML7213) 45 */ 46#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 47 offset(OKI SEMICONDUCTOR ML7223) 48 */ 49 50/* MAX number of INT_REDUCE_CONTROL registers */ 51#define MAX_NUM_INT_REDUCE_CONTROL_REG 128 52#define PCI_DEVICE_ID_PCH1_PHUB 0x8801 53#define PCH_MINOR_NOS 1 54#define CLKCFG_CAN_50MHZ 0x12000000 55#define CLKCFG_CANCLK_MASK 0xFF000000 56#define CLKCFG_UART_MASK 0xFFFFFF 57 58/* CM-iTC */ 59#define CLKCFG_UART_48MHZ (1 << 16) 60#define CLKCFG_BAUDDIV (2 << 20) 61#define CLKCFG_PLL2VCO (8 << 9) 62#define CLKCFG_UARTCLKSEL (1 << 18) 63 64/* Macros for ML7213 */ 65#define PCI_VENDOR_ID_ROHM 0x10db 66#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 67 68/* Macros for ML7213 */ 69#define PCI_VENDOR_ID_ROHM 0x10db 70#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 71 72/* Macros for ML7223 */ 73#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 74#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 75 76/* SROM ACCESS Macro */ 77#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 78 79/* Registers address offset */ 80#define PCH_PHUB_ID_REG 0x0000 81#define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 82#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 83#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 84#define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 85#define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 86#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 87#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 88#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 89#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 90#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 91#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 92#define CLKCFG_REG_OFFSET 0x500 93#define FUNCSEL_REG_OFFSET 0x508 94 95#define PCH_PHUB_OROM_SIZE 15360 96 97/** 98 * struct pch_phub_reg - PHUB register structure 99 * @phub_id_reg: PHUB_ID register val 100 * @q_pri_val_reg: QUEUE_PRI_VAL register val 101 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 102 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 103 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 104 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 105 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 106 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 107 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 108 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 109 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 110 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 111 * @clkcfg_reg: CLK CFG register val 112 * @funcsel_reg: Function select register value 113 * @pch_phub_base_address: Register base address 114 * @pch_phub_extrom_base_address: external rom base address 115 * @pch_mac_start_address: MAC address area start address 116 * @pch_opt_rom_start_address: Option ROM start address 117 * @ioh_type: Save IOH type 118 */ 119struct pch_phub_reg { 120 u32 phub_id_reg; 121 u32 q_pri_val_reg; 122 u32 rc_q_maxsize_reg; 123 u32 bri_q_maxsize_reg; 124 u32 comp_resp_timeout_reg; 125 u32 bus_slave_control_reg; 126 u32 deadlock_avoid_type_reg; 127 u32 intpin_reg_wpermit_reg0; 128 u32 intpin_reg_wpermit_reg1; 129 u32 intpin_reg_wpermit_reg2; 130 u32 intpin_reg_wpermit_reg3; 131 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 132 u32 clkcfg_reg; 133 u32 funcsel_reg; 134 void __iomem *pch_phub_base_address; 135 void __iomem *pch_phub_extrom_base_address; 136 u32 pch_mac_start_address; 137 u32 pch_opt_rom_start_address; 138 int ioh_type; 139}; 140 141/* SROM SPEC for MAC address assignment offset */ 142static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 143 144static DEFINE_MUTEX(pch_phub_mutex); 145 146/** 147 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 148 * @reg_addr_offset: Register offset address value. 149 * @data: Writing value. 150 * @mask: Mask value. 151 */ 152static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 153 unsigned int reg_addr_offset, 154 unsigned int data, unsigned int mask) 155{ 156 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 157 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 158} 159 160/* pch_phub_save_reg_conf - saves register configuration */ 161static void pch_phub_save_reg_conf(struct pci_dev *pdev) 162{ 163 unsigned int i; 164 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 165 166 void __iomem *p = chip->pch_phub_base_address; 167 168 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); 169 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); 170 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 171 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 172 chip->comp_resp_timeout_reg = 173 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 174 chip->bus_slave_control_reg = 175 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 176 chip->deadlock_avoid_type_reg = 177 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 178 chip->intpin_reg_wpermit_reg0 = 179 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 180 chip->intpin_reg_wpermit_reg1 = 181 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 182 chip->intpin_reg_wpermit_reg2 = 183 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 184 chip->intpin_reg_wpermit_reg3 = 185 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 186 dev_dbg(&pdev->dev, "%s : " 187 "chip->phub_id_reg=%x, " 188 "chip->q_pri_val_reg=%x, " 189 "chip->rc_q_maxsize_reg=%x, " 190 "chip->bri_q_maxsize_reg=%x, " 191 "chip->comp_resp_timeout_reg=%x, " 192 "chip->bus_slave_control_reg=%x, " 193 "chip->deadlock_avoid_type_reg=%x, " 194 "chip->intpin_reg_wpermit_reg0=%x, " 195 "chip->intpin_reg_wpermit_reg1=%x, " 196 "chip->intpin_reg_wpermit_reg2=%x, " 197 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 198 chip->phub_id_reg, 199 chip->q_pri_val_reg, 200 chip->rc_q_maxsize_reg, 201 chip->bri_q_maxsize_reg, 202 chip->comp_resp_timeout_reg, 203 chip->bus_slave_control_reg, 204 chip->deadlock_avoid_type_reg, 205 chip->intpin_reg_wpermit_reg0, 206 chip->intpin_reg_wpermit_reg1, 207 chip->intpin_reg_wpermit_reg2, 208 chip->intpin_reg_wpermit_reg3); 209 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 210 chip->int_reduce_control_reg[i] = 211 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 212 dev_dbg(&pdev->dev, "%s : " 213 "chip->int_reduce_control_reg[%d]=%x\n", 214 __func__, i, chip->int_reduce_control_reg[i]); 215 } 216 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); 217 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 218 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); 219} 220 221/* pch_phub_restore_reg_conf - restore register configuration */ 222static void pch_phub_restore_reg_conf(struct pci_dev *pdev) 223{ 224 unsigned int i; 225 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 226 void __iomem *p; 227 p = chip->pch_phub_base_address; 228 229 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); 230 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); 231 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 232 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 233 iowrite32(chip->comp_resp_timeout_reg, 234 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 235 iowrite32(chip->bus_slave_control_reg, 236 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 237 iowrite32(chip->deadlock_avoid_type_reg, 238 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 239 iowrite32(chip->intpin_reg_wpermit_reg0, 240 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 241 iowrite32(chip->intpin_reg_wpermit_reg1, 242 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 243 iowrite32(chip->intpin_reg_wpermit_reg2, 244 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 245 iowrite32(chip->intpin_reg_wpermit_reg3, 246 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 247 dev_dbg(&pdev->dev, "%s : " 248 "chip->phub_id_reg=%x, " 249 "chip->q_pri_val_reg=%x, " 250 "chip->rc_q_maxsize_reg=%x, " 251 "chip->bri_q_maxsize_reg=%x, " 252 "chip->comp_resp_timeout_reg=%x, " 253 "chip->bus_slave_control_reg=%x, " 254 "chip->deadlock_avoid_type_reg=%x, " 255 "chip->intpin_reg_wpermit_reg0=%x, " 256 "chip->intpin_reg_wpermit_reg1=%x, " 257 "chip->intpin_reg_wpermit_reg2=%x, " 258 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 259 chip->phub_id_reg, 260 chip->q_pri_val_reg, 261 chip->rc_q_maxsize_reg, 262 chip->bri_q_maxsize_reg, 263 chip->comp_resp_timeout_reg, 264 chip->bus_slave_control_reg, 265 chip->deadlock_avoid_type_reg, 266 chip->intpin_reg_wpermit_reg0, 267 chip->intpin_reg_wpermit_reg1, 268 chip->intpin_reg_wpermit_reg2, 269 chip->intpin_reg_wpermit_reg3); 270 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 271 iowrite32(chip->int_reduce_control_reg[i], 272 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 273 dev_dbg(&pdev->dev, "%s : " 274 "chip->int_reduce_control_reg[%d]=%x\n", 275 __func__, i, chip->int_reduce_control_reg[i]); 276 } 277 278 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); 279 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 280 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); 281} 282 283/** 284 * pch_phub_read_serial_rom() - Reading Serial ROM 285 * @offset_address: Serial ROM offset address to read. 286 * @data: Read buffer for specified Serial ROM value. 287 */ 288static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 289 unsigned int offset_address, u8 *data) 290{ 291 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 292 offset_address; 293 294 *data = ioread8(mem_addr); 295} 296 297/** 298 * pch_phub_write_serial_rom() - Writing Serial ROM 299 * @offset_address: Serial ROM offset address. 300 * @data: Serial ROM value to write. 301 */ 302static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 303 unsigned int offset_address, u8 data) 304{ 305 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 306 (offset_address & PCH_WORD_ADDR_MASK); 307 int i; 308 unsigned int word_data; 309 unsigned int pos; 310 unsigned int mask; 311 pos = (offset_address % 4) * 8; 312 mask = ~(0xFF << pos); 313 314 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 315 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 316 317 word_data = ioread32(mem_addr); 318 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 319 320 i = 0; 321 while (ioread8(chip->pch_phub_extrom_base_address + 322 PHUB_STATUS) != 0x00) { 323 msleep(1); 324 if (i == PHUB_TIMEOUT) 325 return -ETIMEDOUT; 326 i++; 327 } 328 329 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 330 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 331 332 return 0; 333} 334 335/** 336 * pch_phub_read_serial_rom_val() - Read Serial ROM value 337 * @offset_address: Serial ROM address offset value. 338 * @data: Serial ROM value to read. 339 */ 340static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 341 unsigned int offset_address, u8 *data) 342{ 343 unsigned int mem_addr; 344 345 mem_addr = chip->pch_mac_start_address + 346 pch_phub_mac_offset[offset_address]; 347 348 pch_phub_read_serial_rom(chip, mem_addr, data); 349} 350 351/** 352 * pch_phub_write_serial_rom_val() - writing Serial ROM value 353 * @offset_address: Serial ROM address offset value. 354 * @data: Serial ROM value. 355 */ 356static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 357 unsigned int offset_address, u8 data) 358{ 359 int retval; 360 unsigned int mem_addr; 361 362 mem_addr = chip->pch_mac_start_address + 363 pch_phub_mac_offset[offset_address]; 364 365 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 366 367 return retval; 368} 369 370/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 371 * for Gigabit Ethernet MAC address 372 */ 373static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 374{ 375 int retval; 376 377 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 378 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 379 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 380 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 381 382 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 383 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 384 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 385 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 386 387 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 388 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 389 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 390 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 391 392 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 393 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 394 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 395 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 396 397 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 398 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 399 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 400 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 401 402 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 403 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 404 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 405 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 406 407 return retval; 408} 409 410/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 411 * for Gigabit Ethernet MAC address 412 */ 413static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 414{ 415 int retval; 416 u32 offset_addr; 417 418 offset_addr = 0x200; 419 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 420 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 421 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 422 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 423 424 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 425 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 426 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 427 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 428 429 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 430 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 431 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 432 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 433 434 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 435 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 436 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 437 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 438 439 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 440 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 441 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 442 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 443 444 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 445 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 446 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 447 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 448 449 return retval; 450} 451 452/** 453 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 454 * @offset_address: Gigabit Ethernet MAC address offset value. 455 * @data: Buffer of the Gigabit Ethernet MAC address value. 456 */ 457static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 458{ 459 int i; 460 for (i = 0; i < ETH_ALEN; i++) 461 pch_phub_read_serial_rom_val(chip, i, &data[i]); 462} 463 464/** 465 * pch_phub_write_gbe_mac_addr() - Write MAC address 466 * @offset_address: Gigabit Ethernet MAC address offset value. 467 * @data: Gigabit Ethernet MAC address value. 468 */ 469static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 470{ 471 int retval; 472 int i; 473 474 if (chip->ioh_type == 1) /* EG20T */ 475 retval = pch_phub_gbe_serial_rom_conf(chip); 476 else /* ML7223 */ 477 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 478 if (retval) 479 return retval; 480 481 for (i = 0; i < ETH_ALEN; i++) { 482 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 483 if (retval) 484 return retval; 485 } 486 487 return retval; 488} 489 490static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 491 struct bin_attribute *attr, char *buf, 492 loff_t off, size_t count) 493{ 494 unsigned int rom_signature; 495 unsigned char rom_length; 496 unsigned int tmp; 497 unsigned int addr_offset; 498 unsigned int orom_size; 499 int ret; 500 int err; 501 502 struct pch_phub_reg *chip = 503 dev_get_drvdata(container_of(kobj, struct device, kobj)); 504 505 ret = mutex_lock_interruptible(&pch_phub_mutex); 506 if (ret) { 507 err = -ERESTARTSYS; 508 goto return_err_nomutex; 509 } 510 511 /* Get Rom signature */ 512 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 513 (unsigned char *)&rom_signature); 514 rom_signature &= 0xff; 515 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 516 (unsigned char *)&tmp); 517 rom_signature |= (tmp & 0xff) << 8; 518 if (rom_signature == 0xAA55) { 519 pch_phub_read_serial_rom(chip, 520 chip->pch_opt_rom_start_address + 2, 521 &rom_length); 522 orom_size = rom_length * 512; 523 if (orom_size < off) { 524 addr_offset = 0; 525 goto return_ok; 526 } 527 if (orom_size < count) { 528 addr_offset = 0; 529 goto return_ok; 530 } 531 532 for (addr_offset = 0; addr_offset < count; addr_offset++) { 533 pch_phub_read_serial_rom(chip, 534 chip->pch_opt_rom_start_address + addr_offset + off, 535 &buf[addr_offset]); 536 } 537 } else { 538 err = -ENODATA; 539 goto return_err; 540 } 541return_ok: 542 mutex_unlock(&pch_phub_mutex); 543 return addr_offset; 544 545return_err: 546 mutex_unlock(&pch_phub_mutex); 547return_err_nomutex: 548 return err; 549} 550 551static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 552 struct bin_attribute *attr, 553 char *buf, loff_t off, size_t count) 554{ 555 int err; 556 unsigned int addr_offset; 557 int ret; 558 struct pch_phub_reg *chip = 559 dev_get_drvdata(container_of(kobj, struct device, kobj)); 560 561 ret = mutex_lock_interruptible(&pch_phub_mutex); 562 if (ret) 563 return -ERESTARTSYS; 564 565 if (off > PCH_PHUB_OROM_SIZE) { 566 addr_offset = 0; 567 goto return_ok; 568 } 569 if (count > PCH_PHUB_OROM_SIZE) { 570 addr_offset = 0; 571 goto return_ok; 572 } 573 574 for (addr_offset = 0; addr_offset < count; addr_offset++) { 575 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 576 goto return_ok; 577 578 ret = pch_phub_write_serial_rom(chip, 579 chip->pch_opt_rom_start_address + addr_offset + off, 580 buf[addr_offset]); 581 if (ret) { 582 err = ret; 583 goto return_err; 584 } 585 } 586 587return_ok: 588 mutex_unlock(&pch_phub_mutex); 589 return addr_offset; 590 591return_err: 592 mutex_unlock(&pch_phub_mutex); 593 return err; 594} 595 596static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 597 char *buf) 598{ 599 u8 mac[8]; 600 struct pch_phub_reg *chip = dev_get_drvdata(dev); 601 602 pch_phub_read_gbe_mac_addr(chip, mac); 603 604 return sprintf(buf, "%pM\n", mac); 605} 606 607static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 608 const char *buf, size_t count) 609{ 610 u8 mac[6]; 611 struct pch_phub_reg *chip = dev_get_drvdata(dev); 612 613 if (count != 18) 614 return -EINVAL; 615 616 sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", 617 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3], 618 (u32 *)&mac[4], (u32 *)&mac[5]); 619 620 pch_phub_write_gbe_mac_addr(chip, mac); 621 622 return count; 623} 624 625static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 626 627static struct bin_attribute pch_bin_attr = { 628 .attr = { 629 .name = "pch_firmware", 630 .mode = S_IRUGO | S_IWUSR, 631 }, 632 .size = PCH_PHUB_OROM_SIZE + 1, 633 .read = pch_phub_bin_read, 634 .write = pch_phub_bin_write, 635}; 636 637static int __devinit pch_phub_probe(struct pci_dev *pdev, 638 const struct pci_device_id *id) 639{ 640 int retval; 641 642 int ret; 643 ssize_t rom_size; 644 struct pch_phub_reg *chip; 645 646 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); 647 if (chip == NULL) 648 return -ENOMEM; 649 650 ret = pci_enable_device(pdev); 651 if (ret) { 652 dev_err(&pdev->dev, 653 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 654 goto err_pci_enable_dev; 655 } 656 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 657 ret); 658 659 ret = pci_request_regions(pdev, KBUILD_MODNAME); 660 if (ret) { 661 dev_err(&pdev->dev, 662 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 663 goto err_req_regions; 664 } 665 dev_dbg(&pdev->dev, "%s : " 666 "pci_request_regions returns %d\n", __func__, ret); 667 668 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 669 670 671 if (chip->pch_phub_base_address == 0) { 672 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 673 ret = -ENOMEM; 674 goto err_pci_iomap; 675 } 676 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 677 "in pch_phub_base_address variable is %p\n", __func__, 678 chip->pch_phub_base_address); 679 680 if (id->driver_data != 3) { 681 chip->pch_phub_extrom_base_address =\ 682 pci_map_rom(pdev, &rom_size); 683 if (chip->pch_phub_extrom_base_address == 0) { 684 dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__); 685 ret = -ENOMEM; 686 goto err_pci_map; 687 } 688 dev_dbg(&pdev->dev, "%s : " 689 "pci_map_rom SUCCESS and value in " 690 "pch_phub_extrom_base_address variable is %p\n", 691 __func__, chip->pch_phub_extrom_base_address); 692 } 693 694 if (id->driver_data == 1) { /* EG20T PCH */ 695 const char *board_name; 696 697 retval = sysfs_create_file(&pdev->dev.kobj, 698 &dev_attr_pch_mac.attr); 699 if (retval) 700 goto err_sysfs_create; 701 702 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 703 if (retval) 704 goto exit_bin_attr; 705 706 pch_phub_read_modify_write_reg(chip, 707 (unsigned int)CLKCFG_REG_OFFSET, 708 CLKCFG_CAN_50MHZ, 709 CLKCFG_CANCLK_MASK); 710 711 /* quirk for CM-iTC board */ 712 board_name = dmi_get_system_info(DMI_BOARD_NAME); 713 if (board_name && strstr(board_name, "CM-iTC")) 714 pch_phub_read_modify_write_reg(chip, 715 (unsigned int)CLKCFG_REG_OFFSET, 716 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 717 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 718 CLKCFG_UART_MASK); 719 720 /* set the prefech value */ 721 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 722 /* set the interrupt delay value */ 723 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 724 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 725 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 726 } else if (id->driver_data == 2) { /* ML7213 IOH */ 727 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 728 if (retval) 729 goto err_sysfs_create; 730 /* set the prefech value 731 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 732 * Device4(SDIO #0,1,2):f 733 * Device6(SATA 2):f 734 * Device8(USB OHCI #0/ USB EHCI #0):a 735 */ 736 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 737 chip->pch_opt_rom_start_address =\ 738 PCH_PHUB_ROM_START_ADDR_ML7213; 739 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ 740 /* set the prefech value 741 * Device8(GbE) 742 */ 743 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 744 /* set the interrupt delay value */ 745 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 746 chip->pch_opt_rom_start_address =\ 747 PCH_PHUB_ROM_START_ADDR_ML7223; 748 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 749 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ 750 retval = sysfs_create_file(&pdev->dev.kobj, 751 &dev_attr_pch_mac.attr); 752 if (retval) 753 goto err_sysfs_create; 754 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 755 if (retval) 756 goto exit_bin_attr; 757 /* set the prefech value 758 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 759 * Device4(SDIO #0,1):f 760 * Device6(SATA 2):f 761 */ 762 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 763 chip->pch_opt_rom_start_address =\ 764 PCH_PHUB_ROM_START_ADDR_ML7223; 765 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 766 } 767 768 chip->ioh_type = id->driver_data; 769 pci_set_drvdata(pdev, chip); 770 771 return 0; 772exit_bin_attr: 773 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 774 775err_sysfs_create: 776 pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); 777err_pci_map: 778 pci_iounmap(pdev, chip->pch_phub_base_address); 779err_pci_iomap: 780 pci_release_regions(pdev); 781err_req_regions: 782 pci_disable_device(pdev); 783err_pci_enable_dev: 784 kfree(chip); 785 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 786 return ret; 787} 788 789static void __devexit pch_phub_remove(struct pci_dev *pdev) 790{ 791 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 792 793 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 794 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 795 pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); 796 pci_iounmap(pdev, chip->pch_phub_base_address); 797 pci_release_regions(pdev); 798 pci_disable_device(pdev); 799 kfree(chip); 800} 801 802#ifdef CONFIG_PM 803 804static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state) 805{ 806 int ret; 807 808 pch_phub_save_reg_conf(pdev); 809 ret = pci_save_state(pdev); 810 if (ret) { 811 dev_err(&pdev->dev, 812 " %s -pci_save_state returns %d\n", __func__, ret); 813 return ret; 814 } 815 pci_enable_wake(pdev, PCI_D3hot, 0); 816 pci_disable_device(pdev); 817 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 818 819 return 0; 820} 821 822static int pch_phub_resume(struct pci_dev *pdev) 823{ 824 int ret; 825 826 pci_set_power_state(pdev, PCI_D0); 827 pci_restore_state(pdev); 828 ret = pci_enable_device(pdev); 829 if (ret) { 830 dev_err(&pdev->dev, 831 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 832 return ret; 833 } 834 835 pci_enable_wake(pdev, PCI_D3hot, 0); 836 pch_phub_restore_reg_conf(pdev); 837 838 return 0; 839} 840#else 841#define pch_phub_suspend NULL 842#define pch_phub_resume NULL 843#endif /* CONFIG_PM */ 844 845static struct pci_device_id pch_phub_pcidev_id[] = { 846 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, 847 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, 848 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, }, 849 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, }, 850 { } 851}; 852MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 853 854static struct pci_driver pch_phub_driver = { 855 .name = "pch_phub", 856 .id_table = pch_phub_pcidev_id, 857 .probe = pch_phub_probe, 858 .remove = __devexit_p(pch_phub_remove), 859 .suspend = pch_phub_suspend, 860 .resume = pch_phub_resume 861}; 862 863static int __init pch_phub_pci_init(void) 864{ 865 return pci_register_driver(&pch_phub_driver); 866} 867 868static void __exit pch_phub_pci_exit(void) 869{ 870 pci_unregister_driver(&pch_phub_driver); 871} 872 873module_init(pch_phub_pci_init); 874module_exit(pch_phub_pci_exit); 875 876MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB"); 877MODULE_LICENSE("GPL"); 878