pch_phub.c revision 7f2732c8d7c06f97cc1d530177b7635cb8890b35
1/* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/types.h> 21#include <linux/fs.h> 22#include <linux/uaccess.h> 23#include <linux/string.h> 24#include <linux/pci.h> 25#include <linux/io.h> 26#include <linux/delay.h> 27#include <linux/mutex.h> 28#include <linux/if_ether.h> 29#include <linux/ctype.h> 30#include <linux/dmi.h> 31 32#define PHUB_STATUS 0x00 /* Status Register offset */ 33#define PHUB_CONTROL 0x04 /* Control Register offset */ 34#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */ 35#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */ 36#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */ 37#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address 38 offset */ 39#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address 40 offset */ 41#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset 42 (Intel EG20T PCH)*/ 43#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address 44 offset(LAPIS Semicon ML7213) 45 */ 46#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address 47 offset(LAPIS Semicon ML7223) 48 */ 49 50/* MAX number of INT_REDUCE_CONTROL registers */ 51#define MAX_NUM_INT_REDUCE_CONTROL_REG 128 52#define PCI_DEVICE_ID_PCH1_PHUB 0x8801 53#define PCH_MINOR_NOS 1 54#define CLKCFG_CAN_50MHZ 0x12000000 55#define CLKCFG_CANCLK_MASK 0xFF000000 56#define CLKCFG_UART_MASK 0xFFFFFF 57 58/* CM-iTC */ 59#define CLKCFG_UART_48MHZ (1 << 16) 60#define CLKCFG_BAUDDIV (2 << 20) 61#define CLKCFG_PLL2VCO (8 << 9) 62#define CLKCFG_UARTCLKSEL (1 << 18) 63 64/* Macros for ML7213 */ 65#define PCI_VENDOR_ID_ROHM 0x10db 66#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 67 68/* Macros for ML7213 */ 69#define PCI_VENDOR_ID_ROHM 0x10db 70#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A 71 72/* Macros for ML7223 */ 73#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */ 74#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */ 75 76/* Macros for ML7831 */ 77#define PCI_DEVICE_ID_ROHM_ML7831_PHUB 0x8801 78 79/* SROM ACCESS Macro */ 80#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1)) 81 82/* Registers address offset */ 83#define PCH_PHUB_ID_REG 0x0000 84#define PCH_PHUB_QUEUE_PRI_VAL_REG 0x0004 85#define PCH_PHUB_RC_QUEUE_MAXSIZE_REG 0x0008 86#define PCH_PHUB_BRI_QUEUE_MAXSIZE_REG 0x000C 87#define PCH_PHUB_COMP_RESP_TIMEOUT_REG 0x0010 88#define PCH_PHUB_BUS_SLAVE_CONTROL_REG 0x0014 89#define PCH_PHUB_DEADLOCK_AVOID_TYPE_REG 0x0018 90#define PCH_PHUB_INTPIN_REG_WPERMIT_REG0 0x0020 91#define PCH_PHUB_INTPIN_REG_WPERMIT_REG1 0x0024 92#define PCH_PHUB_INTPIN_REG_WPERMIT_REG2 0x0028 93#define PCH_PHUB_INTPIN_REG_WPERMIT_REG3 0x002C 94#define PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE 0x0040 95#define CLKCFG_REG_OFFSET 0x500 96#define FUNCSEL_REG_OFFSET 0x508 97 98#define PCH_PHUB_OROM_SIZE 15360 99 100/** 101 * struct pch_phub_reg - PHUB register structure 102 * @phub_id_reg: PHUB_ID register val 103 * @q_pri_val_reg: QUEUE_PRI_VAL register val 104 * @rc_q_maxsize_reg: RC_QUEUE_MAXSIZE register val 105 * @bri_q_maxsize_reg: BRI_QUEUE_MAXSIZE register val 106 * @comp_resp_timeout_reg: COMP_RESP_TIMEOUT register val 107 * @bus_slave_control_reg: BUS_SLAVE_CONTROL_REG register val 108 * @deadlock_avoid_type_reg: DEADLOCK_AVOID_TYPE register val 109 * @intpin_reg_wpermit_reg0: INTPIN_REG_WPERMIT register 0 val 110 * @intpin_reg_wpermit_reg1: INTPIN_REG_WPERMIT register 1 val 111 * @intpin_reg_wpermit_reg2: INTPIN_REG_WPERMIT register 2 val 112 * @intpin_reg_wpermit_reg3: INTPIN_REG_WPERMIT register 3 val 113 * @int_reduce_control_reg: INT_REDUCE_CONTROL registers val 114 * @clkcfg_reg: CLK CFG register val 115 * @funcsel_reg: Function select register value 116 * @pch_phub_base_address: Register base address 117 * @pch_phub_extrom_base_address: external rom base address 118 * @pch_mac_start_address: MAC address area start address 119 * @pch_opt_rom_start_address: Option ROM start address 120 * @ioh_type: Save IOH type 121 */ 122struct pch_phub_reg { 123 u32 phub_id_reg; 124 u32 q_pri_val_reg; 125 u32 rc_q_maxsize_reg; 126 u32 bri_q_maxsize_reg; 127 u32 comp_resp_timeout_reg; 128 u32 bus_slave_control_reg; 129 u32 deadlock_avoid_type_reg; 130 u32 intpin_reg_wpermit_reg0; 131 u32 intpin_reg_wpermit_reg1; 132 u32 intpin_reg_wpermit_reg2; 133 u32 intpin_reg_wpermit_reg3; 134 u32 int_reduce_control_reg[MAX_NUM_INT_REDUCE_CONTROL_REG]; 135 u32 clkcfg_reg; 136 u32 funcsel_reg; 137 void __iomem *pch_phub_base_address; 138 void __iomem *pch_phub_extrom_base_address; 139 u32 pch_mac_start_address; 140 u32 pch_opt_rom_start_address; 141 int ioh_type; 142}; 143 144/* SROM SPEC for MAC address assignment offset */ 145static const int pch_phub_mac_offset[ETH_ALEN] = {0x3, 0x2, 0x1, 0x0, 0xb, 0xa}; 146 147static DEFINE_MUTEX(pch_phub_mutex); 148 149/** 150 * pch_phub_read_modify_write_reg() - Reading modifying and writing register 151 * @reg_addr_offset: Register offset address value. 152 * @data: Writing value. 153 * @mask: Mask value. 154 */ 155static void pch_phub_read_modify_write_reg(struct pch_phub_reg *chip, 156 unsigned int reg_addr_offset, 157 unsigned int data, unsigned int mask) 158{ 159 void __iomem *reg_addr = chip->pch_phub_base_address + reg_addr_offset; 160 iowrite32(((ioread32(reg_addr) & ~mask)) | data, reg_addr); 161} 162 163/* pch_phub_save_reg_conf - saves register configuration */ 164static void pch_phub_save_reg_conf(struct pci_dev *pdev) 165{ 166 unsigned int i; 167 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 168 169 void __iomem *p = chip->pch_phub_base_address; 170 171 chip->phub_id_reg = ioread32(p + PCH_PHUB_ID_REG); 172 chip->q_pri_val_reg = ioread32(p + PCH_PHUB_QUEUE_PRI_VAL_REG); 173 chip->rc_q_maxsize_reg = ioread32(p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 174 chip->bri_q_maxsize_reg = ioread32(p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 175 chip->comp_resp_timeout_reg = 176 ioread32(p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 177 chip->bus_slave_control_reg = 178 ioread32(p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 179 chip->deadlock_avoid_type_reg = 180 ioread32(p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 181 chip->intpin_reg_wpermit_reg0 = 182 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 183 chip->intpin_reg_wpermit_reg1 = 184 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 185 chip->intpin_reg_wpermit_reg2 = 186 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 187 chip->intpin_reg_wpermit_reg3 = 188 ioread32(p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 189 dev_dbg(&pdev->dev, "%s : " 190 "chip->phub_id_reg=%x, " 191 "chip->q_pri_val_reg=%x, " 192 "chip->rc_q_maxsize_reg=%x, " 193 "chip->bri_q_maxsize_reg=%x, " 194 "chip->comp_resp_timeout_reg=%x, " 195 "chip->bus_slave_control_reg=%x, " 196 "chip->deadlock_avoid_type_reg=%x, " 197 "chip->intpin_reg_wpermit_reg0=%x, " 198 "chip->intpin_reg_wpermit_reg1=%x, " 199 "chip->intpin_reg_wpermit_reg2=%x, " 200 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 201 chip->phub_id_reg, 202 chip->q_pri_val_reg, 203 chip->rc_q_maxsize_reg, 204 chip->bri_q_maxsize_reg, 205 chip->comp_resp_timeout_reg, 206 chip->bus_slave_control_reg, 207 chip->deadlock_avoid_type_reg, 208 chip->intpin_reg_wpermit_reg0, 209 chip->intpin_reg_wpermit_reg1, 210 chip->intpin_reg_wpermit_reg2, 211 chip->intpin_reg_wpermit_reg3); 212 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 213 chip->int_reduce_control_reg[i] = 214 ioread32(p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 215 dev_dbg(&pdev->dev, "%s : " 216 "chip->int_reduce_control_reg[%d]=%x\n", 217 __func__, i, chip->int_reduce_control_reg[i]); 218 } 219 chip->clkcfg_reg = ioread32(p + CLKCFG_REG_OFFSET); 220 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 221 chip->funcsel_reg = ioread32(p + FUNCSEL_REG_OFFSET); 222} 223 224/* pch_phub_restore_reg_conf - restore register configuration */ 225static void pch_phub_restore_reg_conf(struct pci_dev *pdev) 226{ 227 unsigned int i; 228 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 229 void __iomem *p; 230 p = chip->pch_phub_base_address; 231 232 iowrite32(chip->phub_id_reg, p + PCH_PHUB_ID_REG); 233 iowrite32(chip->q_pri_val_reg, p + PCH_PHUB_QUEUE_PRI_VAL_REG); 234 iowrite32(chip->rc_q_maxsize_reg, p + PCH_PHUB_RC_QUEUE_MAXSIZE_REG); 235 iowrite32(chip->bri_q_maxsize_reg, p + PCH_PHUB_BRI_QUEUE_MAXSIZE_REG); 236 iowrite32(chip->comp_resp_timeout_reg, 237 p + PCH_PHUB_COMP_RESP_TIMEOUT_REG); 238 iowrite32(chip->bus_slave_control_reg, 239 p + PCH_PHUB_BUS_SLAVE_CONTROL_REG); 240 iowrite32(chip->deadlock_avoid_type_reg, 241 p + PCH_PHUB_DEADLOCK_AVOID_TYPE_REG); 242 iowrite32(chip->intpin_reg_wpermit_reg0, 243 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG0); 244 iowrite32(chip->intpin_reg_wpermit_reg1, 245 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG1); 246 iowrite32(chip->intpin_reg_wpermit_reg2, 247 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG2); 248 iowrite32(chip->intpin_reg_wpermit_reg3, 249 p + PCH_PHUB_INTPIN_REG_WPERMIT_REG3); 250 dev_dbg(&pdev->dev, "%s : " 251 "chip->phub_id_reg=%x, " 252 "chip->q_pri_val_reg=%x, " 253 "chip->rc_q_maxsize_reg=%x, " 254 "chip->bri_q_maxsize_reg=%x, " 255 "chip->comp_resp_timeout_reg=%x, " 256 "chip->bus_slave_control_reg=%x, " 257 "chip->deadlock_avoid_type_reg=%x, " 258 "chip->intpin_reg_wpermit_reg0=%x, " 259 "chip->intpin_reg_wpermit_reg1=%x, " 260 "chip->intpin_reg_wpermit_reg2=%x, " 261 "chip->intpin_reg_wpermit_reg3=%x\n", __func__, 262 chip->phub_id_reg, 263 chip->q_pri_val_reg, 264 chip->rc_q_maxsize_reg, 265 chip->bri_q_maxsize_reg, 266 chip->comp_resp_timeout_reg, 267 chip->bus_slave_control_reg, 268 chip->deadlock_avoid_type_reg, 269 chip->intpin_reg_wpermit_reg0, 270 chip->intpin_reg_wpermit_reg1, 271 chip->intpin_reg_wpermit_reg2, 272 chip->intpin_reg_wpermit_reg3); 273 for (i = 0; i < MAX_NUM_INT_REDUCE_CONTROL_REG; i++) { 274 iowrite32(chip->int_reduce_control_reg[i], 275 p + PCH_PHUB_INT_REDUCE_CONTROL_REG_BASE + 4 * i); 276 dev_dbg(&pdev->dev, "%s : " 277 "chip->int_reduce_control_reg[%d]=%x\n", 278 __func__, i, chip->int_reduce_control_reg[i]); 279 } 280 281 iowrite32(chip->clkcfg_reg, p + CLKCFG_REG_OFFSET); 282 if ((chip->ioh_type == 2) || (chip->ioh_type == 4)) 283 iowrite32(chip->funcsel_reg, p + FUNCSEL_REG_OFFSET); 284} 285 286/** 287 * pch_phub_read_serial_rom() - Reading Serial ROM 288 * @offset_address: Serial ROM offset address to read. 289 * @data: Read buffer for specified Serial ROM value. 290 */ 291static void pch_phub_read_serial_rom(struct pch_phub_reg *chip, 292 unsigned int offset_address, u8 *data) 293{ 294 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 295 offset_address; 296 297 *data = ioread8(mem_addr); 298} 299 300/** 301 * pch_phub_write_serial_rom() - Writing Serial ROM 302 * @offset_address: Serial ROM offset address. 303 * @data: Serial ROM value to write. 304 */ 305static int pch_phub_write_serial_rom(struct pch_phub_reg *chip, 306 unsigned int offset_address, u8 data) 307{ 308 void __iomem *mem_addr = chip->pch_phub_extrom_base_address + 309 (offset_address & PCH_WORD_ADDR_MASK); 310 int i; 311 unsigned int word_data; 312 unsigned int pos; 313 unsigned int mask; 314 pos = (offset_address % 4) * 8; 315 mask = ~(0xFF << pos); 316 317 iowrite32(PCH_PHUB_ROM_WRITE_ENABLE, 318 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 319 320 word_data = ioread32(mem_addr); 321 iowrite32((word_data & mask) | (u32)data << pos, mem_addr); 322 323 i = 0; 324 while (ioread8(chip->pch_phub_extrom_base_address + 325 PHUB_STATUS) != 0x00) { 326 msleep(1); 327 if (i == PHUB_TIMEOUT) 328 return -ETIMEDOUT; 329 i++; 330 } 331 332 iowrite32(PCH_PHUB_ROM_WRITE_DISABLE, 333 chip->pch_phub_extrom_base_address + PHUB_CONTROL); 334 335 return 0; 336} 337 338/** 339 * pch_phub_read_serial_rom_val() - Read Serial ROM value 340 * @offset_address: Serial ROM address offset value. 341 * @data: Serial ROM value to read. 342 */ 343static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip, 344 unsigned int offset_address, u8 *data) 345{ 346 unsigned int mem_addr; 347 348 mem_addr = chip->pch_mac_start_address + 349 pch_phub_mac_offset[offset_address]; 350 351 pch_phub_read_serial_rom(chip, mem_addr, data); 352} 353 354/** 355 * pch_phub_write_serial_rom_val() - writing Serial ROM value 356 * @offset_address: Serial ROM address offset value. 357 * @data: Serial ROM value. 358 */ 359static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip, 360 unsigned int offset_address, u8 data) 361{ 362 int retval; 363 unsigned int mem_addr; 364 365 mem_addr = chip->pch_mac_start_address + 366 pch_phub_mac_offset[offset_address]; 367 368 retval = pch_phub_write_serial_rom(chip, mem_addr, data); 369 370 return retval; 371} 372 373/* pch_phub_gbe_serial_rom_conf - makes Serial ROM header format configuration 374 * for Gigabit Ethernet MAC address 375 */ 376static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip) 377{ 378 int retval; 379 380 retval = pch_phub_write_serial_rom(chip, 0x0b, 0xbc); 381 retval |= pch_phub_write_serial_rom(chip, 0x0a, 0x10); 382 retval |= pch_phub_write_serial_rom(chip, 0x09, 0x01); 383 retval |= pch_phub_write_serial_rom(chip, 0x08, 0x02); 384 385 retval |= pch_phub_write_serial_rom(chip, 0x0f, 0x00); 386 retval |= pch_phub_write_serial_rom(chip, 0x0e, 0x00); 387 retval |= pch_phub_write_serial_rom(chip, 0x0d, 0x00); 388 retval |= pch_phub_write_serial_rom(chip, 0x0c, 0x80); 389 390 retval |= pch_phub_write_serial_rom(chip, 0x13, 0xbc); 391 retval |= pch_phub_write_serial_rom(chip, 0x12, 0x10); 392 retval |= pch_phub_write_serial_rom(chip, 0x11, 0x01); 393 retval |= pch_phub_write_serial_rom(chip, 0x10, 0x18); 394 395 retval |= pch_phub_write_serial_rom(chip, 0x1b, 0xbc); 396 retval |= pch_phub_write_serial_rom(chip, 0x1a, 0x10); 397 retval |= pch_phub_write_serial_rom(chip, 0x19, 0x01); 398 retval |= pch_phub_write_serial_rom(chip, 0x18, 0x19); 399 400 retval |= pch_phub_write_serial_rom(chip, 0x23, 0xbc); 401 retval |= pch_phub_write_serial_rom(chip, 0x22, 0x10); 402 retval |= pch_phub_write_serial_rom(chip, 0x21, 0x01); 403 retval |= pch_phub_write_serial_rom(chip, 0x20, 0x3a); 404 405 retval |= pch_phub_write_serial_rom(chip, 0x27, 0x01); 406 retval |= pch_phub_write_serial_rom(chip, 0x26, 0x00); 407 retval |= pch_phub_write_serial_rom(chip, 0x25, 0x00); 408 retval |= pch_phub_write_serial_rom(chip, 0x24, 0x00); 409 410 return retval; 411} 412 413/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration 414 * for Gigabit Ethernet MAC address 415 */ 416static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip) 417{ 418 int retval; 419 u32 offset_addr; 420 421 offset_addr = 0x200; 422 retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc); 423 retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00); 424 retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40); 425 retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02); 426 427 retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00); 428 retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00); 429 retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00); 430 retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80); 431 432 retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc); 433 retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00); 434 retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40); 435 retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18); 436 437 retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc); 438 retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00); 439 retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40); 440 retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19); 441 442 retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc); 443 retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00); 444 retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40); 445 retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a); 446 447 retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01); 448 retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00); 449 retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00); 450 retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00); 451 452 return retval; 453} 454 455/** 456 * pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address 457 * @offset_address: Gigabit Ethernet MAC address offset value. 458 * @data: Buffer of the Gigabit Ethernet MAC address value. 459 */ 460static void pch_phub_read_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 461{ 462 int i; 463 for (i = 0; i < ETH_ALEN; i++) 464 pch_phub_read_serial_rom_val(chip, i, &data[i]); 465} 466 467/** 468 * pch_phub_write_gbe_mac_addr() - Write MAC address 469 * @offset_address: Gigabit Ethernet MAC address offset value. 470 * @data: Gigabit Ethernet MAC address value. 471 */ 472static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data) 473{ 474 int retval; 475 int i; 476 477 if (chip->ioh_type == 1) /* EG20T */ 478 retval = pch_phub_gbe_serial_rom_conf(chip); 479 else /* ML7223 */ 480 retval = pch_phub_gbe_serial_rom_conf_mp(chip); 481 if (retval) 482 return retval; 483 484 for (i = 0; i < ETH_ALEN; i++) { 485 retval = pch_phub_write_serial_rom_val(chip, i, data[i]); 486 if (retval) 487 return retval; 488 } 489 490 return retval; 491} 492 493static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj, 494 struct bin_attribute *attr, char *buf, 495 loff_t off, size_t count) 496{ 497 unsigned int rom_signature; 498 unsigned char rom_length; 499 unsigned int tmp; 500 unsigned int addr_offset; 501 unsigned int orom_size; 502 int ret; 503 int err; 504 505 struct pch_phub_reg *chip = 506 dev_get_drvdata(container_of(kobj, struct device, kobj)); 507 508 ret = mutex_lock_interruptible(&pch_phub_mutex); 509 if (ret) { 510 err = -ERESTARTSYS; 511 goto return_err_nomutex; 512 } 513 514 /* Get Rom signature */ 515 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address, 516 (unsigned char *)&rom_signature); 517 rom_signature &= 0xff; 518 pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1, 519 (unsigned char *)&tmp); 520 rom_signature |= (tmp & 0xff) << 8; 521 if (rom_signature == 0xAA55) { 522 pch_phub_read_serial_rom(chip, 523 chip->pch_opt_rom_start_address + 2, 524 &rom_length); 525 orom_size = rom_length * 512; 526 if (orom_size < off) { 527 addr_offset = 0; 528 goto return_ok; 529 } 530 if (orom_size < count) { 531 addr_offset = 0; 532 goto return_ok; 533 } 534 535 for (addr_offset = 0; addr_offset < count; addr_offset++) { 536 pch_phub_read_serial_rom(chip, 537 chip->pch_opt_rom_start_address + addr_offset + off, 538 &buf[addr_offset]); 539 } 540 } else { 541 err = -ENODATA; 542 goto return_err; 543 } 544return_ok: 545 mutex_unlock(&pch_phub_mutex); 546 return addr_offset; 547 548return_err: 549 mutex_unlock(&pch_phub_mutex); 550return_err_nomutex: 551 return err; 552} 553 554static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj, 555 struct bin_attribute *attr, 556 char *buf, loff_t off, size_t count) 557{ 558 int err; 559 unsigned int addr_offset; 560 int ret; 561 struct pch_phub_reg *chip = 562 dev_get_drvdata(container_of(kobj, struct device, kobj)); 563 564 ret = mutex_lock_interruptible(&pch_phub_mutex); 565 if (ret) 566 return -ERESTARTSYS; 567 568 if (off > PCH_PHUB_OROM_SIZE) { 569 addr_offset = 0; 570 goto return_ok; 571 } 572 if (count > PCH_PHUB_OROM_SIZE) { 573 addr_offset = 0; 574 goto return_ok; 575 } 576 577 for (addr_offset = 0; addr_offset < count; addr_offset++) { 578 if (PCH_PHUB_OROM_SIZE < off + addr_offset) 579 goto return_ok; 580 581 ret = pch_phub_write_serial_rom(chip, 582 chip->pch_opt_rom_start_address + addr_offset + off, 583 buf[addr_offset]); 584 if (ret) { 585 err = ret; 586 goto return_err; 587 } 588 } 589 590return_ok: 591 mutex_unlock(&pch_phub_mutex); 592 return addr_offset; 593 594return_err: 595 mutex_unlock(&pch_phub_mutex); 596 return err; 597} 598 599static ssize_t show_pch_mac(struct device *dev, struct device_attribute *attr, 600 char *buf) 601{ 602 u8 mac[8]; 603 struct pch_phub_reg *chip = dev_get_drvdata(dev); 604 605 pch_phub_read_gbe_mac_addr(chip, mac); 606 607 return sprintf(buf, "%pM\n", mac); 608} 609 610static ssize_t store_pch_mac(struct device *dev, struct device_attribute *attr, 611 const char *buf, size_t count) 612{ 613 u8 mac[6]; 614 struct pch_phub_reg *chip = dev_get_drvdata(dev); 615 616 if (count != 18) 617 return -EINVAL; 618 619 sscanf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", 620 (u32 *)&mac[0], (u32 *)&mac[1], (u32 *)&mac[2], (u32 *)&mac[3], 621 (u32 *)&mac[4], (u32 *)&mac[5]); 622 623 pch_phub_write_gbe_mac_addr(chip, mac); 624 625 return count; 626} 627 628static DEVICE_ATTR(pch_mac, S_IRUGO | S_IWUSR, show_pch_mac, store_pch_mac); 629 630static struct bin_attribute pch_bin_attr = { 631 .attr = { 632 .name = "pch_firmware", 633 .mode = S_IRUGO | S_IWUSR, 634 }, 635 .size = PCH_PHUB_OROM_SIZE + 1, 636 .read = pch_phub_bin_read, 637 .write = pch_phub_bin_write, 638}; 639 640static int __devinit pch_phub_probe(struct pci_dev *pdev, 641 const struct pci_device_id *id) 642{ 643 int retval; 644 645 int ret; 646 ssize_t rom_size; 647 struct pch_phub_reg *chip; 648 649 chip = kzalloc(sizeof(struct pch_phub_reg), GFP_KERNEL); 650 if (chip == NULL) 651 return -ENOMEM; 652 653 ret = pci_enable_device(pdev); 654 if (ret) { 655 dev_err(&pdev->dev, 656 "%s : pci_enable_device FAILED(ret=%d)", __func__, ret); 657 goto err_pci_enable_dev; 658 } 659 dev_dbg(&pdev->dev, "%s : pci_enable_device returns %d\n", __func__, 660 ret); 661 662 ret = pci_request_regions(pdev, KBUILD_MODNAME); 663 if (ret) { 664 dev_err(&pdev->dev, 665 "%s : pci_request_regions FAILED(ret=%d)", __func__, ret); 666 goto err_req_regions; 667 } 668 dev_dbg(&pdev->dev, "%s : " 669 "pci_request_regions returns %d\n", __func__, ret); 670 671 chip->pch_phub_base_address = pci_iomap(pdev, 1, 0); 672 673 674 if (chip->pch_phub_base_address == 0) { 675 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__); 676 ret = -ENOMEM; 677 goto err_pci_iomap; 678 } 679 dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value " 680 "in pch_phub_base_address variable is %p\n", __func__, 681 chip->pch_phub_base_address); 682 683 if (id->driver_data != 3) { 684 chip->pch_phub_extrom_base_address =\ 685 pci_map_rom(pdev, &rom_size); 686 if (chip->pch_phub_extrom_base_address == 0) { 687 dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__); 688 ret = -ENOMEM; 689 goto err_pci_map; 690 } 691 dev_dbg(&pdev->dev, "%s : " 692 "pci_map_rom SUCCESS and value in " 693 "pch_phub_extrom_base_address variable is %p\n", 694 __func__, chip->pch_phub_extrom_base_address); 695 } 696 697 if (id->driver_data == 1) { /* EG20T PCH */ 698 const char *board_name; 699 700 retval = sysfs_create_file(&pdev->dev.kobj, 701 &dev_attr_pch_mac.attr); 702 if (retval) 703 goto err_sysfs_create; 704 705 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 706 if (retval) 707 goto exit_bin_attr; 708 709 pch_phub_read_modify_write_reg(chip, 710 (unsigned int)CLKCFG_REG_OFFSET, 711 CLKCFG_CAN_50MHZ, 712 CLKCFG_CANCLK_MASK); 713 714 /* quirk for CM-iTC board */ 715 board_name = dmi_get_system_info(DMI_BOARD_NAME); 716 if (board_name && strstr(board_name, "CM-iTC")) 717 pch_phub_read_modify_write_reg(chip, 718 (unsigned int)CLKCFG_REG_OFFSET, 719 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV | 720 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL, 721 CLKCFG_UART_MASK); 722 723 /* set the prefech value */ 724 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 725 /* set the interrupt delay value */ 726 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 727 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 728 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 729 } else if (id->driver_data == 2) { /* ML7213 IOH */ 730 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 731 if (retval) 732 goto err_sysfs_create; 733 /* set the prefech value 734 * Device2(USB OHCI #1/ USB EHCI #1/ USB Device):a 735 * Device4(SDIO #0,1,2):f 736 * Device6(SATA 2):f 737 * Device8(USB OHCI #0/ USB EHCI #0):a 738 */ 739 iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14); 740 chip->pch_opt_rom_start_address =\ 741 PCH_PHUB_ROM_START_ADDR_ML7213; 742 } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/ 743 /* set the prefech value 744 * Device8(GbE) 745 */ 746 iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14); 747 /* set the interrupt delay value */ 748 iowrite32(0x25, chip->pch_phub_base_address + 0x140); 749 chip->pch_opt_rom_start_address =\ 750 PCH_PHUB_ROM_START_ADDR_ML7223; 751 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 752 } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/ 753 retval = sysfs_create_file(&pdev->dev.kobj, 754 &dev_attr_pch_mac.attr); 755 if (retval) 756 goto err_sysfs_create; 757 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 758 if (retval) 759 goto exit_bin_attr; 760 /* set the prefech value 761 * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a 762 * Device4(SDIO #0,1):f 763 * Device6(SATA 2):f 764 */ 765 iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14); 766 chip->pch_opt_rom_start_address =\ 767 PCH_PHUB_ROM_START_ADDR_ML7223; 768 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223; 769 } else if (id->driver_data == 5) { /* ML7831 */ 770 retval = sysfs_create_file(&pdev->dev.kobj, 771 &dev_attr_pch_mac.attr); 772 if (retval) 773 goto err_sysfs_create; 774 775 retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr); 776 if (retval) 777 goto exit_bin_attr; 778 779 /* set the prefech value */ 780 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 781 /* set the interrupt delay value */ 782 iowrite32(0x25, chip->pch_phub_base_address + 0x44); 783 chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T; 784 chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T; 785 } 786 787 chip->ioh_type = id->driver_data; 788 pci_set_drvdata(pdev, chip); 789 790 return 0; 791exit_bin_attr: 792 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 793 794err_sysfs_create: 795 pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); 796err_pci_map: 797 pci_iounmap(pdev, chip->pch_phub_base_address); 798err_pci_iomap: 799 pci_release_regions(pdev); 800err_req_regions: 801 pci_disable_device(pdev); 802err_pci_enable_dev: 803 kfree(chip); 804 dev_err(&pdev->dev, "%s returns %d\n", __func__, ret); 805 return ret; 806} 807 808static void __devexit pch_phub_remove(struct pci_dev *pdev) 809{ 810 struct pch_phub_reg *chip = pci_get_drvdata(pdev); 811 812 sysfs_remove_file(&pdev->dev.kobj, &dev_attr_pch_mac.attr); 813 sysfs_remove_bin_file(&pdev->dev.kobj, &pch_bin_attr); 814 pci_unmap_rom(pdev, chip->pch_phub_extrom_base_address); 815 pci_iounmap(pdev, chip->pch_phub_base_address); 816 pci_release_regions(pdev); 817 pci_disable_device(pdev); 818 kfree(chip); 819} 820 821#ifdef CONFIG_PM 822 823static int pch_phub_suspend(struct pci_dev *pdev, pm_message_t state) 824{ 825 int ret; 826 827 pch_phub_save_reg_conf(pdev); 828 ret = pci_save_state(pdev); 829 if (ret) { 830 dev_err(&pdev->dev, 831 " %s -pci_save_state returns %d\n", __func__, ret); 832 return ret; 833 } 834 pci_enable_wake(pdev, PCI_D3hot, 0); 835 pci_disable_device(pdev); 836 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 837 838 return 0; 839} 840 841static int pch_phub_resume(struct pci_dev *pdev) 842{ 843 int ret; 844 845 pci_set_power_state(pdev, PCI_D0); 846 pci_restore_state(pdev); 847 ret = pci_enable_device(pdev); 848 if (ret) { 849 dev_err(&pdev->dev, 850 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 851 return ret; 852 } 853 854 pci_enable_wake(pdev, PCI_D3hot, 0); 855 pch_phub_restore_reg_conf(pdev); 856 857 return 0; 858} 859#else 860#define pch_phub_suspend NULL 861#define pch_phub_resume NULL 862#endif /* CONFIG_PM */ 863 864static struct pci_device_id pch_phub_pcidev_id[] = { 865 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, }, 866 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, }, 867 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, }, 868 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, }, 869 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7831_PHUB), 5, }, 870 { } 871}; 872MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id); 873 874static struct pci_driver pch_phub_driver = { 875 .name = "pch_phub", 876 .id_table = pch_phub_pcidev_id, 877 .probe = pch_phub_probe, 878 .remove = __devexit_p(pch_phub_remove), 879 .suspend = pch_phub_suspend, 880 .resume = pch_phub_resume 881}; 882 883static int __init pch_phub_pci_init(void) 884{ 885 return pci_register_driver(&pch_phub_driver); 886} 887 888static void __exit pch_phub_pci_exit(void) 889{ 890 pci_unregister_driver(&pch_phub_driver); 891} 892 893module_init(pch_phub_pci_init); 894module_exit(pch_phub_pci_exit); 895 896MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor IOH(ML7213/ML7223) PHUB"); 897MODULE_LICENSE("GPL"); 898