davinci_mmc.c revision 7f8bea7f75618165d015f083c77f1db3e4584f88
1/* 2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver 3 * 4 * Copyright (C) 2006 Texas Instruments. 5 * Original author: Purushotam Kumar 6 * Copyright (C) 2009 David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/module.h> 24#include <linux/ioport.h> 25#include <linux/platform_device.h> 26#include <linux/clk.h> 27#include <linux/err.h> 28#include <linux/cpufreq.h> 29#include <linux/mmc/host.h> 30#include <linux/io.h> 31#include <linux/irq.h> 32#include <linux/delay.h> 33#include <linux/dma-mapping.h> 34#include <linux/mmc/mmc.h> 35 36#include <mach/mmc.h> 37#include <mach/edma.h> 38 39/* 40 * Register Definitions 41 */ 42#define DAVINCI_MMCCTL 0x00 /* Control Register */ 43#define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */ 44#define DAVINCI_MMCST0 0x08 /* Status Register 0 */ 45#define DAVINCI_MMCST1 0x0C /* Status Register 1 */ 46#define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */ 47#define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */ 48#define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */ 49#define DAVINCI_MMCBLEN 0x1C /* Block Length Register */ 50#define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */ 51#define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */ 52#define DAVINCI_MMCDRR 0x28 /* Data Receive Register */ 53#define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */ 54#define DAVINCI_MMCCMD 0x30 /* Command Register */ 55#define DAVINCI_MMCARGHL 0x34 /* Argument Register */ 56#define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */ 57#define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */ 58#define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */ 59#define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */ 60#define DAVINCI_MMCDRSP 0x48 /* Data Response Register */ 61#define DAVINCI_MMCETOK 0x4C 62#define DAVINCI_MMCCIDX 0x50 /* Command Index Register */ 63#define DAVINCI_MMCCKC 0x54 64#define DAVINCI_MMCTORC 0x58 65#define DAVINCI_MMCTODC 0x5C 66#define DAVINCI_MMCBLNC 0x60 67#define DAVINCI_SDIOCTL 0x64 68#define DAVINCI_SDIOST0 0x68 69#define DAVINCI_SDIOIEN 0x6C 70#define DAVINCI_SDIOIST 0x70 71#define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */ 72 73/* DAVINCI_MMCCTL definitions */ 74#define MMCCTL_DATRST (1 << 0) 75#define MMCCTL_CMDRST (1 << 1) 76#define MMCCTL_WIDTH_8_BIT (1 << 8) 77#define MMCCTL_WIDTH_4_BIT (1 << 2) 78#define MMCCTL_DATEG_DISABLED (0 << 6) 79#define MMCCTL_DATEG_RISING (1 << 6) 80#define MMCCTL_DATEG_FALLING (2 << 6) 81#define MMCCTL_DATEG_BOTH (3 << 6) 82#define MMCCTL_PERMDR_LE (0 << 9) 83#define MMCCTL_PERMDR_BE (1 << 9) 84#define MMCCTL_PERMDX_LE (0 << 10) 85#define MMCCTL_PERMDX_BE (1 << 10) 86 87/* DAVINCI_MMCCLK definitions */ 88#define MMCCLK_CLKEN (1 << 8) 89#define MMCCLK_CLKRT_MASK (0xFF << 0) 90 91/* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ 92#define MMCST0_DATDNE BIT(0) /* data done */ 93#define MMCST0_BSYDNE BIT(1) /* busy done */ 94#define MMCST0_RSPDNE BIT(2) /* command done */ 95#define MMCST0_TOUTRD BIT(3) /* data read timeout */ 96#define MMCST0_TOUTRS BIT(4) /* command response timeout */ 97#define MMCST0_CRCWR BIT(5) /* data write CRC error */ 98#define MMCST0_CRCRD BIT(6) /* data read CRC error */ 99#define MMCST0_CRCRS BIT(7) /* command response CRC error */ 100#define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */ 101#define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/ 102#define MMCST0_DATED BIT(11) /* DAT3 edge detect */ 103#define MMCST0_TRNDNE BIT(12) /* transfer done */ 104 105/* DAVINCI_MMCST1 definitions */ 106#define MMCST1_BUSY (1 << 0) 107 108/* DAVINCI_MMCCMD definitions */ 109#define MMCCMD_CMD_MASK (0x3F << 0) 110#define MMCCMD_PPLEN (1 << 7) 111#define MMCCMD_BSYEXP (1 << 8) 112#define MMCCMD_RSPFMT_MASK (3 << 9) 113#define MMCCMD_RSPFMT_NONE (0 << 9) 114#define MMCCMD_RSPFMT_R1456 (1 << 9) 115#define MMCCMD_RSPFMT_R2 (2 << 9) 116#define MMCCMD_RSPFMT_R3 (3 << 9) 117#define MMCCMD_DTRW (1 << 11) 118#define MMCCMD_STRMTP (1 << 12) 119#define MMCCMD_WDATX (1 << 13) 120#define MMCCMD_INITCK (1 << 14) 121#define MMCCMD_DCLR (1 << 15) 122#define MMCCMD_DMATRIG (1 << 16) 123 124/* DAVINCI_MMCFIFOCTL definitions */ 125#define MMCFIFOCTL_FIFORST (1 << 0) 126#define MMCFIFOCTL_FIFODIR_WR (1 << 1) 127#define MMCFIFOCTL_FIFODIR_RD (0 << 1) 128#define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */ 129#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */ 130#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */ 131#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */ 132#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */ 133 134/* DAVINCI_SDIOST0 definitions */ 135#define SDIOST0_DAT1_HI BIT(0) 136 137/* DAVINCI_SDIOIEN definitions */ 138#define SDIOIEN_IOINTEN BIT(0) 139 140/* DAVINCI_SDIOIST definitions */ 141#define SDIOIST_IOINT BIT(0) 142 143/* MMCSD Init clock in Hz in opendrain mode */ 144#define MMCSD_INIT_CLOCK 200000 145 146/* 147 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units, 148 * and we handle up to MAX_NR_SG segments. MMC_BLOCK_BOUNCE kicks in only 149 * for drivers with max_segs == 1, making the segments bigger (64KB) 150 * than the page or two that's otherwise typical. nr_sg (passed from 151 * platform data) == 16 gives at least the same throughput boost, using 152 * EDMA transfer linkage instead of spending CPU time copying pages. 153 */ 154#define MAX_CCNT ((1 << 16) - 1) 155 156#define MAX_NR_SG 16 157 158static unsigned rw_threshold = 32; 159module_param(rw_threshold, uint, S_IRUGO); 160MODULE_PARM_DESC(rw_threshold, 161 "Read/Write threshold. Default = 32"); 162 163static unsigned poll_threshold = 128; 164module_param(poll_threshold, uint, S_IRUGO); 165MODULE_PARM_DESC(poll_threshold, 166 "Polling transaction size threshold. Default = 128"); 167 168static unsigned poll_loopcount = 32; 169module_param(poll_loopcount, uint, S_IRUGO); 170MODULE_PARM_DESC(poll_loopcount, 171 "Maximum polling loop count. Default = 32"); 172 173static unsigned __initdata use_dma = 1; 174module_param(use_dma, uint, 0); 175MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1"); 176 177struct mmc_davinci_host { 178 struct mmc_command *cmd; 179 struct mmc_data *data; 180 struct mmc_host *mmc; 181 struct clk *clk; 182 unsigned int mmc_input_clk; 183 void __iomem *base; 184 struct resource *mem_res; 185 int mmc_irq, sdio_irq; 186 unsigned char bus_mode; 187 188#define DAVINCI_MMC_DATADIR_NONE 0 189#define DAVINCI_MMC_DATADIR_READ 1 190#define DAVINCI_MMC_DATADIR_WRITE 2 191 unsigned char data_dir; 192 unsigned char suspended; 193 194 /* buffer is used during PIO of one scatterlist segment, and 195 * is updated along with buffer_bytes_left. bytes_left applies 196 * to all N blocks of the PIO transfer. 197 */ 198 u8 *buffer; 199 u32 buffer_bytes_left; 200 u32 bytes_left; 201 202 u32 rxdma, txdma; 203 bool use_dma; 204 bool do_dma; 205 bool sdio_int; 206 bool active_request; 207 208 /* Scatterlist DMA uses one or more parameter RAM entries: 209 * the main one (associated with rxdma or txdma) plus zero or 210 * more links. The entries for a given transfer differ only 211 * by memory buffer (address, length) and link field. 212 */ 213 struct edmacc_param tx_template; 214 struct edmacc_param rx_template; 215 unsigned n_link; 216 u32 links[MAX_NR_SG - 1]; 217 218 /* For PIO we walk scatterlists one segment at a time. */ 219 unsigned int sg_len; 220 struct scatterlist *sg; 221 222 /* Version of the MMC/SD controller */ 223 u8 version; 224 /* for ns in one cycle calculation */ 225 unsigned ns_in_one_cycle; 226 /* Number of sg segments */ 227 u8 nr_sg; 228#ifdef CONFIG_CPU_FREQ 229 struct notifier_block freq_transition; 230#endif 231}; 232 233static irqreturn_t mmc_davinci_irq(int irq, void *dev_id); 234 235/* PIO only */ 236static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host) 237{ 238 host->buffer_bytes_left = sg_dma_len(host->sg); 239 host->buffer = sg_virt(host->sg); 240 if (host->buffer_bytes_left > host->bytes_left) 241 host->buffer_bytes_left = host->bytes_left; 242} 243 244static void davinci_fifo_data_trans(struct mmc_davinci_host *host, 245 unsigned int n) 246{ 247 u8 *p; 248 unsigned int i; 249 250 if (host->buffer_bytes_left == 0) { 251 host->sg = sg_next(host->data->sg); 252 mmc_davinci_sg_to_buf(host); 253 } 254 255 p = host->buffer; 256 if (n > host->buffer_bytes_left) 257 n = host->buffer_bytes_left; 258 host->buffer_bytes_left -= n; 259 host->bytes_left -= n; 260 261 /* NOTE: we never transfer more than rw_threshold bytes 262 * to/from the fifo here; there's no I/O overlap. 263 * This also assumes that access width( i.e. ACCWD) is 4 bytes 264 */ 265 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 266 for (i = 0; i < (n >> 2); i++) { 267 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 268 p = p + 4; 269 } 270 if (n & 3) { 271 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 272 p = p + (n & 3); 273 } 274 } else { 275 for (i = 0; i < (n >> 2); i++) { 276 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 277 p = p + 4; 278 } 279 if (n & 3) { 280 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 281 p = p + (n & 3); 282 } 283 } 284 host->buffer = p; 285} 286 287static void mmc_davinci_start_command(struct mmc_davinci_host *host, 288 struct mmc_command *cmd) 289{ 290 u32 cmd_reg = 0; 291 u32 im_val; 292 293 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n", 294 cmd->opcode, cmd->arg, 295 ({ char *s; 296 switch (mmc_resp_type(cmd)) { 297 case MMC_RSP_R1: 298 s = ", R1/R5/R6/R7 response"; 299 break; 300 case MMC_RSP_R1B: 301 s = ", R1b response"; 302 break; 303 case MMC_RSP_R2: 304 s = ", R2 response"; 305 break; 306 case MMC_RSP_R3: 307 s = ", R3/R4 response"; 308 break; 309 default: 310 s = ", (R? response)"; 311 break; 312 }; s; })); 313 host->cmd = cmd; 314 315 switch (mmc_resp_type(cmd)) { 316 case MMC_RSP_R1B: 317 /* There's some spec confusion about when R1B is 318 * allowed, but if the card doesn't issue a BUSY 319 * then it's harmless for us to allow it. 320 */ 321 cmd_reg |= MMCCMD_BSYEXP; 322 /* FALLTHROUGH */ 323 case MMC_RSP_R1: /* 48 bits, CRC */ 324 cmd_reg |= MMCCMD_RSPFMT_R1456; 325 break; 326 case MMC_RSP_R2: /* 136 bits, CRC */ 327 cmd_reg |= MMCCMD_RSPFMT_R2; 328 break; 329 case MMC_RSP_R3: /* 48 bits, no CRC */ 330 cmd_reg |= MMCCMD_RSPFMT_R3; 331 break; 332 default: 333 cmd_reg |= MMCCMD_RSPFMT_NONE; 334 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n", 335 mmc_resp_type(cmd)); 336 break; 337 } 338 339 /* Set command index */ 340 cmd_reg |= cmd->opcode; 341 342 /* Enable EDMA transfer triggers */ 343 if (host->do_dma) 344 cmd_reg |= MMCCMD_DMATRIG; 345 346 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL && 347 host->data_dir == DAVINCI_MMC_DATADIR_READ) 348 cmd_reg |= MMCCMD_DMATRIG; 349 350 /* Setting whether command involves data transfer or not */ 351 if (cmd->data) 352 cmd_reg |= MMCCMD_WDATX; 353 354 /* Setting whether stream or block transfer */ 355 if (cmd->flags & MMC_DATA_STREAM) 356 cmd_reg |= MMCCMD_STRMTP; 357 358 /* Setting whether data read or write */ 359 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 360 cmd_reg |= MMCCMD_DTRW; 361 362 if (host->bus_mode == MMC_BUSMODE_PUSHPULL) 363 cmd_reg |= MMCCMD_PPLEN; 364 365 /* set Command timeout */ 366 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 367 368 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ 369 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; 370 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 371 im_val |= MMCST0_DATDNE | MMCST0_CRCWR; 372 373 if (!host->do_dma) 374 im_val |= MMCST0_DXRDY; 375 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) { 376 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; 377 378 if (!host->do_dma) 379 im_val |= MMCST0_DRRDY; 380 } 381 382 /* 383 * Before non-DMA WRITE commands the controller needs priming: 384 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size 385 */ 386 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)) 387 davinci_fifo_data_trans(host, rw_threshold); 388 389 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 390 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 391 392 host->active_request = true; 393 394 if (!host->do_dma && host->bytes_left <= poll_threshold) { 395 u32 count = poll_loopcount; 396 397 while (host->active_request && count--) { 398 mmc_davinci_irq(0, host); 399 cpu_relax(); 400 } 401 } 402 403 if (host->active_request) 404 writel(im_val, host->base + DAVINCI_MMCIM); 405} 406 407/*----------------------------------------------------------------------*/ 408 409/* DMA infrastructure */ 410 411static void davinci_abort_dma(struct mmc_davinci_host *host) 412{ 413 int sync_dev; 414 415 if (host->data_dir == DAVINCI_MMC_DATADIR_READ) 416 sync_dev = host->rxdma; 417 else 418 sync_dev = host->txdma; 419 420 edma_stop(sync_dev); 421 edma_clean_channel(sync_dev); 422} 423 424static void 425mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data); 426 427static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data) 428{ 429 if (DMA_COMPLETE != ch_status) { 430 struct mmc_davinci_host *host = data; 431 432 /* Currently means: DMA Event Missed, or "null" transfer 433 * request was seen. In the future, TC errors (like bad 434 * addresses) might be presented too. 435 */ 436 dev_warn(mmc_dev(host->mmc), "DMA %s error\n", 437 (host->data->flags & MMC_DATA_WRITE) 438 ? "write" : "read"); 439 host->data->error = -EIO; 440 mmc_davinci_xfer_done(host, host->data); 441 } 442} 443 444/* Set up tx or rx template, to be modified and updated later */ 445static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host, 446 bool tx, struct edmacc_param *template) 447{ 448 unsigned sync_dev; 449 const u16 acnt = 4; 450 const u16 bcnt = rw_threshold >> 2; 451 const u16 ccnt = 0; 452 u32 src_port = 0; 453 u32 dst_port = 0; 454 s16 src_bidx, dst_bidx; 455 s16 src_cidx, dst_cidx; 456 457 /* 458 * A-B Sync transfer: each DMA request is for one "frame" of 459 * rw_threshold bytes, broken into "acnt"-size chunks repeated 460 * "bcnt" times. Each segment needs "ccnt" such frames; since 461 * we tell the block layer our mmc->max_seg_size limit, we can 462 * trust (later) that it's within bounds. 463 * 464 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and 465 * EDMA will optimize memory operations to use larger bursts. 466 */ 467 if (tx) { 468 sync_dev = host->txdma; 469 470 /* src_prt, ccnt, and link to be set up later */ 471 src_bidx = acnt; 472 src_cidx = acnt * bcnt; 473 474 dst_port = host->mem_res->start + DAVINCI_MMCDXR; 475 dst_bidx = 0; 476 dst_cidx = 0; 477 } else { 478 sync_dev = host->rxdma; 479 480 src_port = host->mem_res->start + DAVINCI_MMCDRR; 481 src_bidx = 0; 482 src_cidx = 0; 483 484 /* dst_prt, ccnt, and link to be set up later */ 485 dst_bidx = acnt; 486 dst_cidx = acnt * bcnt; 487 } 488 489 /* 490 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses 491 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT 492 * parameter is ignored. 493 */ 494 edma_set_src(sync_dev, src_port, INCR, W8BIT); 495 edma_set_dest(sync_dev, dst_port, INCR, W8BIT); 496 497 edma_set_src_index(sync_dev, src_bidx, src_cidx); 498 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); 499 500 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); 501 502 edma_read_slot(sync_dev, template); 503 504 /* don't bother with irqs or chaining */ 505 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; 506} 507 508static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host, 509 struct mmc_data *data) 510{ 511 struct edmacc_param *template; 512 int channel, slot; 513 unsigned link; 514 struct scatterlist *sg; 515 unsigned sg_len; 516 unsigned bytes_left = host->bytes_left; 517 const unsigned shift = ffs(rw_threshold) - 1; 518 519 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) { 520 template = &host->tx_template; 521 channel = host->txdma; 522 } else { 523 template = &host->rx_template; 524 channel = host->rxdma; 525 } 526 527 /* We know sg_len and ccnt will never be out of range because 528 * we told the mmc layer which in turn tells the block layer 529 * to ensure that it only hands us one scatterlist segment 530 * per EDMA PARAM entry. Update the PARAM 531 * entries needed for each segment of this scatterlist. 532 */ 533 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len; 534 sg_len-- != 0 && bytes_left; 535 sg = sg_next(sg), slot = host->links[link++]) { 536 u32 buf = sg_dma_address(sg); 537 unsigned count = sg_dma_len(sg); 538 539 template->link_bcntrld = sg_len 540 ? (EDMA_CHAN_SLOT(host->links[link]) << 5) 541 : 0xffff; 542 543 if (count > bytes_left) 544 count = bytes_left; 545 bytes_left -= count; 546 547 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) 548 template->src = buf; 549 else 550 template->dst = buf; 551 template->ccnt = count >> shift; 552 553 edma_write_slot(slot, template); 554 } 555 556 if (host->version == MMC_CTLR_VERSION_2) 557 edma_clear_event(channel); 558 559 edma_start(channel); 560} 561 562static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host, 563 struct mmc_data *data) 564{ 565 int i; 566 int mask = rw_threshold - 1; 567 568 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 569 ((data->flags & MMC_DATA_WRITE) 570 ? DMA_TO_DEVICE 571 : DMA_FROM_DEVICE)); 572 573 /* no individual DMA segment should need a partial FIFO */ 574 for (i = 0; i < host->sg_len; i++) { 575 if (sg_dma_len(data->sg + i) & mask) { 576 dma_unmap_sg(mmc_dev(host->mmc), 577 data->sg, data->sg_len, 578 (data->flags & MMC_DATA_WRITE) 579 ? DMA_TO_DEVICE 580 : DMA_FROM_DEVICE); 581 return -1; 582 } 583 } 584 585 host->do_dma = 1; 586 mmc_davinci_send_dma_request(host, data); 587 588 return 0; 589} 590 591static void __init_or_module 592davinci_release_dma_channels(struct mmc_davinci_host *host) 593{ 594 unsigned i; 595 596 if (!host->use_dma) 597 return; 598 599 for (i = 0; i < host->n_link; i++) 600 edma_free_slot(host->links[i]); 601 602 edma_free_channel(host->txdma); 603 edma_free_channel(host->rxdma); 604} 605 606static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host) 607{ 608 u32 link_size; 609 int r, i; 610 611 /* Acquire master DMA write channel */ 612 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host, 613 EVENTQ_DEFAULT); 614 if (r < 0) { 615 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 616 "tx", r); 617 return r; 618 } 619 mmc_davinci_dma_setup(host, true, &host->tx_template); 620 621 /* Acquire master DMA read channel */ 622 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host, 623 EVENTQ_DEFAULT); 624 if (r < 0) { 625 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n", 626 "rx", r); 627 goto free_master_write; 628 } 629 mmc_davinci_dma_setup(host, false, &host->rx_template); 630 631 /* Allocate parameter RAM slots, which will later be bound to a 632 * channel as needed to handle a scatterlist. 633 */ 634 link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); 635 for (i = 0; i < link_size; i++) { 636 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); 637 if (r < 0) { 638 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n", 639 r); 640 break; 641 } 642 host->links[i] = r; 643 } 644 host->n_link = i; 645 646 return 0; 647 648free_master_write: 649 edma_free_channel(host->txdma); 650 651 return r; 652} 653 654/*----------------------------------------------------------------------*/ 655 656static void 657mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req) 658{ 659 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0; 660 int timeout; 661 struct mmc_data *data = req->data; 662 663 if (host->version == MMC_CTLR_VERSION_2) 664 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; 665 666 host->data = data; 667 if (data == NULL) { 668 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 669 writel(0, host->base + DAVINCI_MMCBLEN); 670 writel(0, host->base + DAVINCI_MMCNBLK); 671 return; 672 } 673 674 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n", 675 (data->flags & MMC_DATA_STREAM) ? "stream" : "block", 676 (data->flags & MMC_DATA_WRITE) ? "write" : "read", 677 data->blocks, data->blksz); 678 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n", 679 data->timeout_clks, data->timeout_ns); 680 timeout = data->timeout_clks + 681 (data->timeout_ns / host->ns_in_one_cycle); 682 if (timeout > 0xffff) 683 timeout = 0xffff; 684 685 writel(timeout, host->base + DAVINCI_MMCTOD); 686 writel(data->blocks, host->base + DAVINCI_MMCNBLK); 687 writel(data->blksz, host->base + DAVINCI_MMCBLEN); 688 689 /* Configure the FIFO */ 690 switch (data->flags & MMC_DATA_WRITE) { 691 case MMC_DATA_WRITE: 692 host->data_dir = DAVINCI_MMC_DATADIR_WRITE; 693 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, 694 host->base + DAVINCI_MMCFIFOCTL); 695 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, 696 host->base + DAVINCI_MMCFIFOCTL); 697 break; 698 699 default: 700 host->data_dir = DAVINCI_MMC_DATADIR_READ; 701 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, 702 host->base + DAVINCI_MMCFIFOCTL); 703 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, 704 host->base + DAVINCI_MMCFIFOCTL); 705 break; 706 } 707 708 host->buffer = NULL; 709 host->bytes_left = data->blocks * data->blksz; 710 711 /* For now we try to use DMA whenever we won't need partial FIFO 712 * reads or writes, either for the whole transfer (as tested here) 713 * or for any individual scatterlist segment (tested when we call 714 * start_dma_transfer). 715 * 716 * While we *could* change that, unusual block sizes are rarely 717 * used. The occasional fallback to PIO should't hurt. 718 */ 719 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0 720 && mmc_davinci_start_dma_transfer(host, data) == 0) { 721 /* zero this to ensure we take no PIO paths */ 722 host->bytes_left = 0; 723 } else { 724 /* Revert to CPU Copy */ 725 host->sg_len = data->sg_len; 726 host->sg = host->data->sg; 727 mmc_davinci_sg_to_buf(host); 728 } 729} 730 731static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req) 732{ 733 struct mmc_davinci_host *host = mmc_priv(mmc); 734 unsigned long timeout = jiffies + msecs_to_jiffies(900); 735 u32 mmcst1 = 0; 736 737 /* Card may still be sending BUSY after a previous operation, 738 * typically some kind of write. If so, we can't proceed yet. 739 */ 740 while (time_before(jiffies, timeout)) { 741 mmcst1 = readl(host->base + DAVINCI_MMCST1); 742 if (!(mmcst1 & MMCST1_BUSY)) 743 break; 744 cpu_relax(); 745 } 746 if (mmcst1 & MMCST1_BUSY) { 747 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n"); 748 req->cmd->error = -ETIMEDOUT; 749 mmc_request_done(mmc, req); 750 return; 751 } 752 753 host->do_dma = 0; 754 mmc_davinci_prepare_data(host, req); 755 mmc_davinci_start_command(host, req->cmd); 756} 757 758static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host, 759 unsigned int mmc_req_freq) 760{ 761 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0; 762 763 mmc_pclk = host->mmc_input_clk; 764 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) 765 mmc_push_pull_divisor = ((unsigned int)mmc_pclk 766 / (2 * mmc_req_freq)) - 1; 767 else 768 mmc_push_pull_divisor = 0; 769 770 mmc_freq = (unsigned int)mmc_pclk 771 / (2 * (mmc_push_pull_divisor + 1)); 772 773 if (mmc_freq > mmc_req_freq) 774 mmc_push_pull_divisor = mmc_push_pull_divisor + 1; 775 /* Convert ns to clock cycles */ 776 if (mmc_req_freq <= 400000) 777 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 778 / (2 * (mmc_push_pull_divisor + 1)))/1000)); 779 else 780 host->ns_in_one_cycle = (1000000) / (((mmc_pclk 781 / (2 * (mmc_push_pull_divisor + 1)))/1000000)); 782 783 return mmc_push_pull_divisor; 784} 785 786static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios) 787{ 788 unsigned int open_drain_freq = 0, mmc_pclk = 0; 789 unsigned int mmc_push_pull_freq = 0; 790 struct mmc_davinci_host *host = mmc_priv(mmc); 791 792 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 793 u32 temp; 794 795 /* Ignoring the init clock value passed for fixing the inter 796 * operability with different cards. 797 */ 798 open_drain_freq = ((unsigned int)mmc_pclk 799 / (2 * MMCSD_INIT_CLOCK)) - 1; 800 801 if (open_drain_freq > 0xFF) 802 open_drain_freq = 0xFF; 803 804 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 805 temp |= open_drain_freq; 806 writel(temp, host->base + DAVINCI_MMCCLK); 807 808 /* Convert ns to clock cycles */ 809 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000); 810 } else { 811 u32 temp; 812 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); 813 814 if (mmc_push_pull_freq > 0xFF) 815 mmc_push_pull_freq = 0xFF; 816 817 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN; 818 writel(temp, host->base + DAVINCI_MMCCLK); 819 820 udelay(10); 821 822 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK; 823 temp |= mmc_push_pull_freq; 824 writel(temp, host->base + DAVINCI_MMCCLK); 825 826 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 827 828 udelay(10); 829 } 830} 831 832static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 833{ 834 struct mmc_davinci_host *host = mmc_priv(mmc); 835 struct platform_device *pdev = to_platform_device(mmc->parent); 836 struct davinci_mmc_config *config = pdev->dev.platform_data; 837 838 dev_dbg(mmc_dev(host->mmc), 839 "clock %dHz busmode %d powermode %d Vdd %04x\n", 840 ios->clock, ios->bus_mode, ios->power_mode, 841 ios->vdd); 842 843 switch (ios->power_mode) { 844 case MMC_POWER_OFF: 845 if (config && config->set_power) 846 config->set_power(pdev->id, false); 847 break; 848 case MMC_POWER_UP: 849 if (config && config->set_power) 850 config->set_power(pdev->id, true); 851 break; 852 } 853 854 switch (ios->bus_width) { 855 case MMC_BUS_WIDTH_8: 856 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n"); 857 writel((readl(host->base + DAVINCI_MMCCTL) & 858 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT, 859 host->base + DAVINCI_MMCCTL); 860 break; 861 case MMC_BUS_WIDTH_4: 862 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n"); 863 if (host->version == MMC_CTLR_VERSION_2) 864 writel((readl(host->base + DAVINCI_MMCCTL) & 865 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT, 866 host->base + DAVINCI_MMCCTL); 867 else 868 writel(readl(host->base + DAVINCI_MMCCTL) | 869 MMCCTL_WIDTH_4_BIT, 870 host->base + DAVINCI_MMCCTL); 871 break; 872 case MMC_BUS_WIDTH_1: 873 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n"); 874 if (host->version == MMC_CTLR_VERSION_2) 875 writel(readl(host->base + DAVINCI_MMCCTL) & 876 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT), 877 host->base + DAVINCI_MMCCTL); 878 else 879 writel(readl(host->base + DAVINCI_MMCCTL) & 880 ~MMCCTL_WIDTH_4_BIT, 881 host->base + DAVINCI_MMCCTL); 882 break; 883 } 884 885 calculate_clk_divider(mmc, ios); 886 887 host->bus_mode = ios->bus_mode; 888 if (ios->power_mode == MMC_POWER_UP) { 889 unsigned long timeout = jiffies + msecs_to_jiffies(50); 890 bool lose = true; 891 892 /* Send clock cycles, poll completion */ 893 writel(0, host->base + DAVINCI_MMCARGHL); 894 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); 895 while (time_before(jiffies, timeout)) { 896 u32 tmp = readl(host->base + DAVINCI_MMCST0); 897 898 if (tmp & MMCST0_RSPDNE) { 899 lose = false; 900 break; 901 } 902 cpu_relax(); 903 } 904 if (lose) 905 dev_warn(mmc_dev(host->mmc), "powerup timeout\n"); 906 } 907 908 /* FIXME on power OFF, reset things ... */ 909} 910 911static void 912mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data) 913{ 914 host->data = NULL; 915 916 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 917 /* 918 * SDIO Interrupt Detection work-around as suggested by 919 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata 920 * 2.1.6): Signal SDIO interrupt only if it is enabled by core 921 */ 922 if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) & 923 SDIOST0_DAT1_HI)) { 924 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 925 mmc_signal_sdio_irq(host->mmc); 926 } 927 } 928 929 if (host->do_dma) { 930 davinci_abort_dma(host); 931 932 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 933 (data->flags & MMC_DATA_WRITE) 934 ? DMA_TO_DEVICE 935 : DMA_FROM_DEVICE); 936 host->do_dma = false; 937 } 938 host->data_dir = DAVINCI_MMC_DATADIR_NONE; 939 940 if (!data->stop || (host->cmd && host->cmd->error)) { 941 mmc_request_done(host->mmc, data->mrq); 942 writel(0, host->base + DAVINCI_MMCIM); 943 host->active_request = false; 944 } else 945 mmc_davinci_start_command(host, data->stop); 946} 947 948static void mmc_davinci_cmd_done(struct mmc_davinci_host *host, 949 struct mmc_command *cmd) 950{ 951 host->cmd = NULL; 952 953 if (cmd->flags & MMC_RSP_PRESENT) { 954 if (cmd->flags & MMC_RSP_136) { 955 /* response type 2 */ 956 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01); 957 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23); 958 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45); 959 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 960 } else { 961 /* response types 1, 1b, 3, 4, 5, 6 */ 962 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67); 963 } 964 } 965 966 if (host->data == NULL || cmd->error) { 967 if (cmd->error == -ETIMEDOUT) 968 cmd->mrq->cmd->retries = 0; 969 mmc_request_done(host->mmc, cmd->mrq); 970 writel(0, host->base + DAVINCI_MMCIM); 971 host->active_request = false; 972 } 973} 974 975static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host, 976 int val) 977{ 978 u32 temp; 979 980 temp = readl(host->base + DAVINCI_MMCCTL); 981 if (val) /* reset */ 982 temp |= MMCCTL_CMDRST | MMCCTL_DATRST; 983 else /* enable */ 984 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); 985 986 writel(temp, host->base + DAVINCI_MMCCTL); 987 udelay(10); 988} 989 990static void 991davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data) 992{ 993 mmc_davinci_reset_ctrl(host, 1); 994 mmc_davinci_reset_ctrl(host, 0); 995} 996 997static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id) 998{ 999 struct mmc_davinci_host *host = dev_id; 1000 unsigned int status; 1001 1002 status = readl(host->base + DAVINCI_SDIOIST); 1003 if (status & SDIOIST_IOINT) { 1004 dev_dbg(mmc_dev(host->mmc), 1005 "SDIO interrupt status %x\n", status); 1006 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1007 mmc_signal_sdio_irq(host->mmc); 1008 } 1009 return IRQ_HANDLED; 1010} 1011 1012static irqreturn_t mmc_davinci_irq(int irq, void *dev_id) 1013{ 1014 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id; 1015 unsigned int status, qstatus; 1016 int end_command = 0; 1017 int end_transfer = 0; 1018 struct mmc_data *data = host->data; 1019 1020 if (host->cmd == NULL && host->data == NULL) { 1021 status = readl(host->base + DAVINCI_MMCST0); 1022 dev_dbg(mmc_dev(host->mmc), 1023 "Spurious interrupt 0x%04x\n", status); 1024 /* Disable the interrupt from mmcsd */ 1025 writel(0, host->base + DAVINCI_MMCIM); 1026 return IRQ_NONE; 1027 } 1028 1029 status = readl(host->base + DAVINCI_MMCST0); 1030 qstatus = status; 1031 1032 /* handle FIFO first when using PIO for data. 1033 * bytes_left will decrease to zero as I/O progress and status will 1034 * read zero over iteration because this controller status 1035 * register(MMCST0) reports any status only once and it is cleared 1036 * by read. So, it is not unbouned loop even in the case of 1037 * non-dma. 1038 */ 1039 if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) { 1040 unsigned long im_val; 1041 1042 /* 1043 * If interrupts fire during the following loop, they will be 1044 * handled by the handler, but the PIC will still buffer these. 1045 * As a result, the handler will be called again to serve these 1046 * needlessly. In order to avoid these spurious interrupts, 1047 * keep interrupts masked during the loop. 1048 */ 1049 im_val = readl(host->base + DAVINCI_MMCIM); 1050 writel(0, host->base + DAVINCI_MMCIM); 1051 1052 do { 1053 davinci_fifo_data_trans(host, rw_threshold); 1054 status = readl(host->base + DAVINCI_MMCST0); 1055 qstatus |= status; 1056 } while (host->bytes_left && 1057 (status & (MMCST0_DXRDY | MMCST0_DRRDY))); 1058 1059 /* 1060 * If an interrupt is pending, it is assumed it will fire when 1061 * it is unmasked. This assumption is also taken when the MMCIM 1062 * is first set. Otherwise, writing to MMCIM after reading the 1063 * status is race-prone. 1064 */ 1065 writel(im_val, host->base + DAVINCI_MMCIM); 1066 } 1067 1068 if (qstatus & MMCST0_DATDNE) { 1069 /* All blocks sent/received, and CRC checks passed */ 1070 if (data != NULL) { 1071 if ((host->do_dma == 0) && (host->bytes_left > 0)) { 1072 /* if datasize < rw_threshold 1073 * no RX ints are generated 1074 */ 1075 davinci_fifo_data_trans(host, host->bytes_left); 1076 } 1077 end_transfer = 1; 1078 data->bytes_xfered = data->blocks * data->blksz; 1079 } else { 1080 dev_err(mmc_dev(host->mmc), 1081 "DATDNE with no host->data\n"); 1082 } 1083 } 1084 1085 if (qstatus & MMCST0_TOUTRD) { 1086 /* Read data timeout */ 1087 data->error = -ETIMEDOUT; 1088 end_transfer = 1; 1089 1090 dev_dbg(mmc_dev(host->mmc), 1091 "read data timeout, status %x\n", 1092 qstatus); 1093 1094 davinci_abort_data(host, data); 1095 } 1096 1097 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) { 1098 /* Data CRC error */ 1099 data->error = -EILSEQ; 1100 end_transfer = 1; 1101 1102 /* NOTE: this controller uses CRCWR to report both CRC 1103 * errors and timeouts (on writes). MMCDRSP values are 1104 * only weakly documented, but 0x9f was clearly a timeout 1105 * case and the two three-bit patterns in various SD specs 1106 * (101, 010) aren't part of it ... 1107 */ 1108 if (qstatus & MMCST0_CRCWR) { 1109 u32 temp = readb(host->base + DAVINCI_MMCDRSP); 1110 1111 if (temp == 0x9f) 1112 data->error = -ETIMEDOUT; 1113 } 1114 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n", 1115 (qstatus & MMCST0_CRCWR) ? "write" : "read", 1116 (data->error == -ETIMEDOUT) ? "timeout" : "CRC"); 1117 1118 davinci_abort_data(host, data); 1119 } 1120 1121 if (qstatus & MMCST0_TOUTRS) { 1122 /* Command timeout */ 1123 if (host->cmd) { 1124 dev_dbg(mmc_dev(host->mmc), 1125 "CMD%d timeout, status %x\n", 1126 host->cmd->opcode, qstatus); 1127 host->cmd->error = -ETIMEDOUT; 1128 if (data) { 1129 end_transfer = 1; 1130 davinci_abort_data(host, data); 1131 } else 1132 end_command = 1; 1133 } 1134 } 1135 1136 if (qstatus & MMCST0_CRCRS) { 1137 /* Command CRC error */ 1138 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n"); 1139 if (host->cmd) { 1140 host->cmd->error = -EILSEQ; 1141 end_command = 1; 1142 } 1143 } 1144 1145 if (qstatus & MMCST0_RSPDNE) { 1146 /* End of command phase */ 1147 end_command = (int) host->cmd; 1148 } 1149 1150 if (end_command) 1151 mmc_davinci_cmd_done(host, host->cmd); 1152 if (end_transfer) 1153 mmc_davinci_xfer_done(host, data); 1154 return IRQ_HANDLED; 1155} 1156 1157static int mmc_davinci_get_cd(struct mmc_host *mmc) 1158{ 1159 struct platform_device *pdev = to_platform_device(mmc->parent); 1160 struct davinci_mmc_config *config = pdev->dev.platform_data; 1161 1162 if (!config || !config->get_cd) 1163 return -ENOSYS; 1164 return config->get_cd(pdev->id); 1165} 1166 1167static int mmc_davinci_get_ro(struct mmc_host *mmc) 1168{ 1169 struct platform_device *pdev = to_platform_device(mmc->parent); 1170 struct davinci_mmc_config *config = pdev->dev.platform_data; 1171 1172 if (!config || !config->get_ro) 1173 return -ENOSYS; 1174 return config->get_ro(pdev->id); 1175} 1176 1177static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1178{ 1179 struct mmc_davinci_host *host = mmc_priv(mmc); 1180 1181 if (enable) { 1182 if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) { 1183 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); 1184 mmc_signal_sdio_irq(host->mmc); 1185 } else { 1186 host->sdio_int = true; 1187 writel(readl(host->base + DAVINCI_SDIOIEN) | 1188 SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN); 1189 } 1190 } else { 1191 host->sdio_int = false; 1192 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, 1193 host->base + DAVINCI_SDIOIEN); 1194 } 1195} 1196 1197static struct mmc_host_ops mmc_davinci_ops = { 1198 .request = mmc_davinci_request, 1199 .set_ios = mmc_davinci_set_ios, 1200 .get_cd = mmc_davinci_get_cd, 1201 .get_ro = mmc_davinci_get_ro, 1202 .enable_sdio_irq = mmc_davinci_enable_sdio_irq, 1203}; 1204 1205/*----------------------------------------------------------------------*/ 1206 1207#ifdef CONFIG_CPU_FREQ 1208static int mmc_davinci_cpufreq_transition(struct notifier_block *nb, 1209 unsigned long val, void *data) 1210{ 1211 struct mmc_davinci_host *host; 1212 unsigned int mmc_pclk; 1213 struct mmc_host *mmc; 1214 unsigned long flags; 1215 1216 host = container_of(nb, struct mmc_davinci_host, freq_transition); 1217 mmc = host->mmc; 1218 mmc_pclk = clk_get_rate(host->clk); 1219 1220 if (val == CPUFREQ_POSTCHANGE) { 1221 spin_lock_irqsave(&mmc->lock, flags); 1222 host->mmc_input_clk = mmc_pclk; 1223 calculate_clk_divider(mmc, &mmc->ios); 1224 spin_unlock_irqrestore(&mmc->lock, flags); 1225 } 1226 1227 return 0; 1228} 1229 1230static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1231{ 1232 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition; 1233 1234 return cpufreq_register_notifier(&host->freq_transition, 1235 CPUFREQ_TRANSITION_NOTIFIER); 1236} 1237 1238static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1239{ 1240 cpufreq_unregister_notifier(&host->freq_transition, 1241 CPUFREQ_TRANSITION_NOTIFIER); 1242} 1243#else 1244static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host) 1245{ 1246 return 0; 1247} 1248 1249static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host) 1250{ 1251} 1252#endif 1253static void __init init_mmcsd_host(struct mmc_davinci_host *host) 1254{ 1255 1256 mmc_davinci_reset_ctrl(host, 1); 1257 1258 writel(0, host->base + DAVINCI_MMCCLK); 1259 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); 1260 1261 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 1262 writel(0xFFFF, host->base + DAVINCI_MMCTOD); 1263 1264 mmc_davinci_reset_ctrl(host, 0); 1265} 1266 1267static int __init davinci_mmcsd_probe(struct platform_device *pdev) 1268{ 1269 struct davinci_mmc_config *pdata = pdev->dev.platform_data; 1270 struct mmc_davinci_host *host = NULL; 1271 struct mmc_host *mmc = NULL; 1272 struct resource *r, *mem = NULL; 1273 int ret = 0, irq = 0; 1274 size_t mem_size; 1275 1276 /* REVISIT: when we're fully converted, fail if pdata is NULL */ 1277 1278 ret = -ENODEV; 1279 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1280 irq = platform_get_irq(pdev, 0); 1281 if (!r || irq == NO_IRQ) 1282 goto out; 1283 1284 ret = -EBUSY; 1285 mem_size = resource_size(r); 1286 mem = request_mem_region(r->start, mem_size, pdev->name); 1287 if (!mem) 1288 goto out; 1289 1290 ret = -ENOMEM; 1291 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev); 1292 if (!mmc) 1293 goto out; 1294 1295 host = mmc_priv(mmc); 1296 host->mmc = mmc; /* Important */ 1297 1298 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1299 if (!r) 1300 goto out; 1301 host->rxdma = r->start; 1302 1303 r = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1304 if (!r) 1305 goto out; 1306 host->txdma = r->start; 1307 1308 host->mem_res = mem; 1309 host->base = ioremap(mem->start, mem_size); 1310 if (!host->base) 1311 goto out; 1312 1313 ret = -ENXIO; 1314 host->clk = clk_get(&pdev->dev, "MMCSDCLK"); 1315 if (IS_ERR(host->clk)) { 1316 ret = PTR_ERR(host->clk); 1317 goto out; 1318 } 1319 clk_enable(host->clk); 1320 host->mmc_input_clk = clk_get_rate(host->clk); 1321 1322 init_mmcsd_host(host); 1323 1324 if (pdata->nr_sg) 1325 host->nr_sg = pdata->nr_sg - 1; 1326 1327 if (host->nr_sg > MAX_NR_SG || !host->nr_sg) 1328 host->nr_sg = MAX_NR_SG; 1329 1330 host->use_dma = use_dma; 1331 host->mmc_irq = irq; 1332 host->sdio_irq = platform_get_irq(pdev, 1); 1333 1334 if (host->use_dma && davinci_acquire_dma_channels(host) != 0) 1335 host->use_dma = 0; 1336 1337 /* REVISIT: someday, support IRQ-driven card detection. */ 1338 mmc->caps |= MMC_CAP_NEEDS_POLL; 1339 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1340 1341 if (pdata && (pdata->wires == 4 || pdata->wires == 0)) 1342 mmc->caps |= MMC_CAP_4_BIT_DATA; 1343 1344 if (pdata && (pdata->wires == 8)) 1345 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); 1346 1347 host->version = pdata->version; 1348 1349 mmc->ops = &mmc_davinci_ops; 1350 mmc->f_min = 312500; 1351 mmc->f_max = 25000000; 1352 if (pdata && pdata->max_freq) 1353 mmc->f_max = pdata->max_freq; 1354 if (pdata && pdata->caps) 1355 mmc->caps |= pdata->caps; 1356 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1357 1358 /* With no iommu coalescing pages, each phys_seg is a hw_seg. 1359 * Each hw_seg uses one EDMA parameter RAM slot, always one 1360 * channel and then usually some linked slots. 1361 */ 1362 mmc->max_segs = 1 + host->n_link; 1363 1364 /* EDMA limit per hw segment (one or two MBytes) */ 1365 mmc->max_seg_size = MAX_CCNT * rw_threshold; 1366 1367 /* MMC/SD controller limits for multiblock requests */ 1368 mmc->max_blk_size = 4095; /* BLEN is 12 bits */ 1369 mmc->max_blk_count = 65535; /* NBLK is 16 bits */ 1370 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1371 1372 dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs); 1373 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size); 1374 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size); 1375 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size); 1376 1377 platform_set_drvdata(pdev, host); 1378 1379 ret = mmc_davinci_cpufreq_register(host); 1380 if (ret) { 1381 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1382 goto cpu_freq_fail; 1383 } 1384 1385 ret = mmc_add_host(mmc); 1386 if (ret < 0) 1387 goto out; 1388 1389 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host); 1390 if (ret) 1391 goto out; 1392 1393 if (host->sdio_irq >= 0) { 1394 ret = request_irq(host->sdio_irq, mmc_davinci_sdio_irq, 0, 1395 mmc_hostname(mmc), host); 1396 if (!ret) 1397 mmc->caps |= MMC_CAP_SDIO_IRQ; 1398 } 1399 1400 rename_region(mem, mmc_hostname(mmc)); 1401 1402 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n", 1403 host->use_dma ? "DMA" : "PIO", 1404 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1); 1405 1406 return 0; 1407 1408out: 1409 mmc_davinci_cpufreq_deregister(host); 1410cpu_freq_fail: 1411 if (host) { 1412 davinci_release_dma_channels(host); 1413 1414 if (host->clk) { 1415 clk_disable(host->clk); 1416 clk_put(host->clk); 1417 } 1418 1419 if (host->base) 1420 iounmap(host->base); 1421 } 1422 1423 if (mmc) 1424 mmc_free_host(mmc); 1425 1426 if (mem) 1427 release_resource(mem); 1428 1429 dev_dbg(&pdev->dev, "probe err %d\n", ret); 1430 1431 return ret; 1432} 1433 1434static int __exit davinci_mmcsd_remove(struct platform_device *pdev) 1435{ 1436 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1437 1438 platform_set_drvdata(pdev, NULL); 1439 if (host) { 1440 mmc_davinci_cpufreq_deregister(host); 1441 1442 mmc_remove_host(host->mmc); 1443 free_irq(host->mmc_irq, host); 1444 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 1445 free_irq(host->sdio_irq, host); 1446 1447 davinci_release_dma_channels(host); 1448 1449 clk_disable(host->clk); 1450 clk_put(host->clk); 1451 1452 iounmap(host->base); 1453 1454 release_resource(host->mem_res); 1455 1456 mmc_free_host(host->mmc); 1457 } 1458 1459 return 0; 1460} 1461 1462#ifdef CONFIG_PM 1463static int davinci_mmcsd_suspend(struct device *dev) 1464{ 1465 struct platform_device *pdev = to_platform_device(dev); 1466 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1467 int ret; 1468 1469 ret = mmc_suspend_host(host->mmc); 1470 if (!ret) { 1471 writel(0, host->base + DAVINCI_MMCIM); 1472 mmc_davinci_reset_ctrl(host, 1); 1473 clk_disable(host->clk); 1474 host->suspended = 1; 1475 } else { 1476 host->suspended = 0; 1477 } 1478 1479 return ret; 1480} 1481 1482static int davinci_mmcsd_resume(struct device *dev) 1483{ 1484 struct platform_device *pdev = to_platform_device(dev); 1485 struct mmc_davinci_host *host = platform_get_drvdata(pdev); 1486 int ret; 1487 1488 if (!host->suspended) 1489 return 0; 1490 1491 clk_enable(host->clk); 1492 1493 mmc_davinci_reset_ctrl(host, 0); 1494 ret = mmc_resume_host(host->mmc); 1495 if (!ret) 1496 host->suspended = 0; 1497 1498 return ret; 1499} 1500 1501static const struct dev_pm_ops davinci_mmcsd_pm = { 1502 .suspend = davinci_mmcsd_suspend, 1503 .resume = davinci_mmcsd_resume, 1504}; 1505 1506#define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm) 1507#else 1508#define davinci_mmcsd_pm_ops NULL 1509#endif 1510 1511static struct platform_driver davinci_mmcsd_driver = { 1512 .driver = { 1513 .name = "davinci_mmc", 1514 .owner = THIS_MODULE, 1515 .pm = davinci_mmcsd_pm_ops, 1516 }, 1517 .remove = __exit_p(davinci_mmcsd_remove), 1518}; 1519 1520static int __init davinci_mmcsd_init(void) 1521{ 1522 return platform_driver_probe(&davinci_mmcsd_driver, 1523 davinci_mmcsd_probe); 1524} 1525module_init(davinci_mmcsd_init); 1526 1527static void __exit davinci_mmcsd_exit(void) 1528{ 1529 platform_driver_unregister(&davinci_mmcsd_driver); 1530} 1531module_exit(davinci_mmcsd_exit); 1532 1533MODULE_AUTHOR("Texas Instruments India"); 1534MODULE_LICENSE("GPL"); 1535MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller"); 1536MODULE_ALIAS("platform:davinci_mmc"); 1537 1538