mmci.c revision 3a37298ada749897ec2c5c1cdcd5932218eb2928
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/highmem.h> 22#include <linux/log2.h> 23#include <linux/mmc/pm.h> 24#include <linux/mmc/host.h> 25#include <linux/mmc/card.h> 26#include <linux/amba/bus.h> 27#include <linux/clk.h> 28#include <linux/scatterlist.h> 29#include <linux/gpio.h> 30#include <linux/of_gpio.h> 31#include <linux/regulator/consumer.h> 32#include <linux/dmaengine.h> 33#include <linux/dma-mapping.h> 34#include <linux/amba/mmci.h> 35#include <linux/pm_runtime.h> 36#include <linux/types.h> 37#include <linux/pinctrl/consumer.h> 38 39#include <asm/div64.h> 40#include <asm/io.h> 41#include <asm/sizes.h> 42 43#include "mmci.h" 44 45#define DRIVER_NAME "mmci-pl18x" 46 47static unsigned int fmax = 515633; 48 49/** 50 * struct variant_data - MMCI variant-specific quirks 51 * @clkreg: default value for MCICLOCK register 52 * @clkreg_enable: enable value for MMCICLOCK register 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 55 * is asserted (likewise for RX) 56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 57 * is asserted (likewise for RX) 58 * @sdio: variant supports SDIO 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 61 * @pwrreg_powerup: power up value for MMCIPOWER register 62 * @signal_direction: input/out direction of bus signals can be indicated 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 64 */ 65struct variant_data { 66 unsigned int clkreg; 67 unsigned int clkreg_enable; 68 unsigned int datalength_bits; 69 unsigned int fifosize; 70 unsigned int fifohalfsize; 71 bool sdio; 72 bool st_clkdiv; 73 bool blksz_datactrl16; 74 u32 pwrreg_powerup; 75 bool signal_direction; 76 bool pwrreg_clkgate; 77}; 78 79static struct variant_data variant_arm = { 80 .fifosize = 16 * 4, 81 .fifohalfsize = 8 * 4, 82 .datalength_bits = 16, 83 .pwrreg_powerup = MCI_PWR_UP, 84}; 85 86static struct variant_data variant_arm_extended_fifo = { 87 .fifosize = 128 * 4, 88 .fifohalfsize = 64 * 4, 89 .datalength_bits = 16, 90 .pwrreg_powerup = MCI_PWR_UP, 91}; 92 93static struct variant_data variant_arm_extended_fifo_hwfc = { 94 .fifosize = 128 * 4, 95 .fifohalfsize = 64 * 4, 96 .clkreg_enable = MCI_ARM_HWFCEN, 97 .datalength_bits = 16, 98 .pwrreg_powerup = MCI_PWR_UP, 99}; 100 101static struct variant_data variant_u300 = { 102 .fifosize = 16 * 4, 103 .fifohalfsize = 8 * 4, 104 .clkreg_enable = MCI_ST_U300_HWFCEN, 105 .datalength_bits = 16, 106 .sdio = true, 107 .pwrreg_powerup = MCI_PWR_ON, 108 .signal_direction = true, 109 .pwrreg_clkgate = true, 110}; 111 112static struct variant_data variant_nomadik = { 113 .fifosize = 16 * 4, 114 .fifohalfsize = 8 * 4, 115 .clkreg = MCI_CLK_ENABLE, 116 .datalength_bits = 24, 117 .sdio = true, 118 .st_clkdiv = true, 119 .pwrreg_powerup = MCI_PWR_ON, 120 .signal_direction = true, 121 .pwrreg_clkgate = true, 122}; 123 124static struct variant_data variant_ux500 = { 125 .fifosize = 30 * 4, 126 .fifohalfsize = 8 * 4, 127 .clkreg = MCI_CLK_ENABLE, 128 .clkreg_enable = MCI_ST_UX500_HWFCEN, 129 .datalength_bits = 24, 130 .sdio = true, 131 .st_clkdiv = true, 132 .pwrreg_powerup = MCI_PWR_ON, 133 .signal_direction = true, 134 .pwrreg_clkgate = true, 135}; 136 137static struct variant_data variant_ux500v2 = { 138 .fifosize = 30 * 4, 139 .fifohalfsize = 8 * 4, 140 .clkreg = MCI_CLK_ENABLE, 141 .clkreg_enable = MCI_ST_UX500_HWFCEN, 142 .datalength_bits = 24, 143 .sdio = true, 144 .st_clkdiv = true, 145 .blksz_datactrl16 = true, 146 .pwrreg_powerup = MCI_PWR_ON, 147 .signal_direction = true, 148 .pwrreg_clkgate = true, 149}; 150 151/* 152 * This must be called with host->lock held 153 */ 154static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 155{ 156 if (host->clk_reg != clk) { 157 host->clk_reg = clk; 158 writel(clk, host->base + MMCICLOCK); 159 } 160} 161 162/* 163 * This must be called with host->lock held 164 */ 165static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 166{ 167 if (host->pwr_reg != pwr) { 168 host->pwr_reg = pwr; 169 writel(pwr, host->base + MMCIPOWER); 170 } 171} 172 173/* 174 * This must be called with host->lock held 175 */ 176static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 177{ 178 struct variant_data *variant = host->variant; 179 u32 clk = variant->clkreg; 180 181 if (desired) { 182 if (desired >= host->mclk) { 183 clk = MCI_CLK_BYPASS; 184 if (variant->st_clkdiv) 185 clk |= MCI_ST_UX500_NEG_EDGE; 186 host->cclk = host->mclk; 187 } else if (variant->st_clkdiv) { 188 /* 189 * DB8500 TRM says f = mclk / (clkdiv + 2) 190 * => clkdiv = (mclk / f) - 2 191 * Round the divider up so we don't exceed the max 192 * frequency 193 */ 194 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 195 if (clk >= 256) 196 clk = 255; 197 host->cclk = host->mclk / (clk + 2); 198 } else { 199 /* 200 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 201 * => clkdiv = mclk / (2 * f) - 1 202 */ 203 clk = host->mclk / (2 * desired) - 1; 204 if (clk >= 256) 205 clk = 255; 206 host->cclk = host->mclk / (2 * (clk + 1)); 207 } 208 209 clk |= variant->clkreg_enable; 210 clk |= MCI_CLK_ENABLE; 211 /* This hasn't proven to be worthwhile */ 212 /* clk |= MCI_CLK_PWRSAVE; */ 213 } 214 215 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 216 clk |= MCI_4BIT_BUS; 217 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 218 clk |= MCI_ST_8BIT_BUS; 219 220 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 221 clk |= MCI_ST_UX500_NEG_EDGE; 222 223 mmci_write_clkreg(host, clk); 224} 225 226static void 227mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 228{ 229 writel(0, host->base + MMCICOMMAND); 230 231 BUG_ON(host->data); 232 233 host->mrq = NULL; 234 host->cmd = NULL; 235 236 mmc_request_done(host->mmc, mrq); 237 238 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 239 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 240} 241 242static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 243{ 244 void __iomem *base = host->base; 245 246 if (host->singleirq) { 247 unsigned int mask0 = readl(base + MMCIMASK0); 248 249 mask0 &= ~MCI_IRQ1MASK; 250 mask0 |= mask; 251 252 writel(mask0, base + MMCIMASK0); 253 } 254 255 writel(mask, base + MMCIMASK1); 256} 257 258static void mmci_stop_data(struct mmci_host *host) 259{ 260 writel(0, host->base + MMCIDATACTRL); 261 mmci_set_mask1(host, 0); 262 host->data = NULL; 263} 264 265static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 266{ 267 unsigned int flags = SG_MITER_ATOMIC; 268 269 if (data->flags & MMC_DATA_READ) 270 flags |= SG_MITER_TO_SG; 271 else 272 flags |= SG_MITER_FROM_SG; 273 274 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 275} 276 277/* 278 * All the DMA operation mode stuff goes inside this ifdef. 279 * This assumes that you have a generic DMA device interface, 280 * no custom DMA interfaces are supported. 281 */ 282#ifdef CONFIG_DMA_ENGINE 283static void mmci_dma_setup(struct mmci_host *host) 284{ 285 struct mmci_platform_data *plat = host->plat; 286 const char *rxname, *txname; 287 dma_cap_mask_t mask; 288 289 if (!plat || !plat->dma_filter) { 290 dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 291 return; 292 } 293 294 /* initialize pre request cookie */ 295 host->next_data.cookie = 1; 296 297 /* Try to acquire a generic DMA engine slave channel */ 298 dma_cap_zero(mask); 299 dma_cap_set(DMA_SLAVE, mask); 300 301 /* 302 * If only an RX channel is specified, the driver will 303 * attempt to use it bidirectionally, however if it is 304 * is specified but cannot be located, DMA will be disabled. 305 */ 306 if (plat->dma_rx_param) { 307 host->dma_rx_channel = dma_request_channel(mask, 308 plat->dma_filter, 309 plat->dma_rx_param); 310 /* E.g if no DMA hardware is present */ 311 if (!host->dma_rx_channel) 312 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 313 } 314 315 if (plat->dma_tx_param) { 316 host->dma_tx_channel = dma_request_channel(mask, 317 plat->dma_filter, 318 plat->dma_tx_param); 319 if (!host->dma_tx_channel) 320 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 321 } else { 322 host->dma_tx_channel = host->dma_rx_channel; 323 } 324 325 if (host->dma_rx_channel) 326 rxname = dma_chan_name(host->dma_rx_channel); 327 else 328 rxname = "none"; 329 330 if (host->dma_tx_channel) 331 txname = dma_chan_name(host->dma_tx_channel); 332 else 333 txname = "none"; 334 335 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 336 rxname, txname); 337 338 /* 339 * Limit the maximum segment size in any SG entry according to 340 * the parameters of the DMA engine device. 341 */ 342 if (host->dma_tx_channel) { 343 struct device *dev = host->dma_tx_channel->device->dev; 344 unsigned int max_seg_size = dma_get_max_seg_size(dev); 345 346 if (max_seg_size < host->mmc->max_seg_size) 347 host->mmc->max_seg_size = max_seg_size; 348 } 349 if (host->dma_rx_channel) { 350 struct device *dev = host->dma_rx_channel->device->dev; 351 unsigned int max_seg_size = dma_get_max_seg_size(dev); 352 353 if (max_seg_size < host->mmc->max_seg_size) 354 host->mmc->max_seg_size = max_seg_size; 355 } 356} 357 358/* 359 * This is used in or so inline it 360 * so it can be discarded. 361 */ 362static inline void mmci_dma_release(struct mmci_host *host) 363{ 364 struct mmci_platform_data *plat = host->plat; 365 366 if (host->dma_rx_channel) 367 dma_release_channel(host->dma_rx_channel); 368 if (host->dma_tx_channel && plat->dma_tx_param) 369 dma_release_channel(host->dma_tx_channel); 370 host->dma_rx_channel = host->dma_tx_channel = NULL; 371} 372 373static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 374{ 375 struct dma_chan *chan = host->dma_current; 376 enum dma_data_direction dir; 377 u32 status; 378 int i; 379 380 /* Wait up to 1ms for the DMA to complete */ 381 for (i = 0; ; i++) { 382 status = readl(host->base + MMCISTATUS); 383 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 384 break; 385 udelay(10); 386 } 387 388 /* 389 * Check to see whether we still have some data left in the FIFO - 390 * this catches DMA controllers which are unable to monitor the 391 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 392 * contiguous buffers. On TX, we'll get a FIFO underrun error. 393 */ 394 if (status & MCI_RXDATAAVLBLMASK) { 395 dmaengine_terminate_all(chan); 396 if (!data->error) 397 data->error = -EIO; 398 } 399 400 if (data->flags & MMC_DATA_WRITE) { 401 dir = DMA_TO_DEVICE; 402 } else { 403 dir = DMA_FROM_DEVICE; 404 } 405 406 if (!data->host_cookie) 407 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 408 409 /* 410 * Use of DMA with scatter-gather is impossible. 411 * Give up with DMA and switch back to PIO mode. 412 */ 413 if (status & MCI_RXDATAAVLBLMASK) { 414 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 415 mmci_dma_release(host); 416 } 417} 418 419static void mmci_dma_data_error(struct mmci_host *host) 420{ 421 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 422 dmaengine_terminate_all(host->dma_current); 423} 424 425static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 426 struct mmci_host_next *next) 427{ 428 struct variant_data *variant = host->variant; 429 struct dma_slave_config conf = { 430 .src_addr = host->phybase + MMCIFIFO, 431 .dst_addr = host->phybase + MMCIFIFO, 432 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 433 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 434 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 435 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 436 .device_fc = false, 437 }; 438 struct dma_chan *chan; 439 struct dma_device *device; 440 struct dma_async_tx_descriptor *desc; 441 enum dma_data_direction buffer_dirn; 442 int nr_sg; 443 444 /* Check if next job is already prepared */ 445 if (data->host_cookie && !next && 446 host->dma_current && host->dma_desc_current) 447 return 0; 448 449 if (!next) { 450 host->dma_current = NULL; 451 host->dma_desc_current = NULL; 452 } 453 454 if (data->flags & MMC_DATA_READ) { 455 conf.direction = DMA_DEV_TO_MEM; 456 buffer_dirn = DMA_FROM_DEVICE; 457 chan = host->dma_rx_channel; 458 } else { 459 conf.direction = DMA_MEM_TO_DEV; 460 buffer_dirn = DMA_TO_DEVICE; 461 chan = host->dma_tx_channel; 462 } 463 464 /* If there's no DMA channel, fall back to PIO */ 465 if (!chan) 466 return -EINVAL; 467 468 /* If less than or equal to the fifo size, don't bother with DMA */ 469 if (data->blksz * data->blocks <= variant->fifosize) 470 return -EINVAL; 471 472 device = chan->device; 473 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 474 if (nr_sg == 0) 475 return -EINVAL; 476 477 dmaengine_slave_config(chan, &conf); 478 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 479 conf.direction, DMA_CTRL_ACK); 480 if (!desc) 481 goto unmap_exit; 482 483 if (next) { 484 next->dma_chan = chan; 485 next->dma_desc = desc; 486 } else { 487 host->dma_current = chan; 488 host->dma_desc_current = desc; 489 } 490 491 return 0; 492 493 unmap_exit: 494 if (!next) 495 dmaengine_terminate_all(chan); 496 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 497 return -ENOMEM; 498} 499 500static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 501{ 502 int ret; 503 struct mmc_data *data = host->data; 504 505 ret = mmci_dma_prep_data(host, host->data, NULL); 506 if (ret) 507 return ret; 508 509 /* Okay, go for it. */ 510 dev_vdbg(mmc_dev(host->mmc), 511 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 512 data->sg_len, data->blksz, data->blocks, data->flags); 513 dmaengine_submit(host->dma_desc_current); 514 dma_async_issue_pending(host->dma_current); 515 516 datactrl |= MCI_DPSM_DMAENABLE; 517 518 /* Trigger the DMA transfer */ 519 writel(datactrl, host->base + MMCIDATACTRL); 520 521 /* 522 * Let the MMCI say when the data is ended and it's time 523 * to fire next DMA request. When that happens, MMCI will 524 * call mmci_data_end() 525 */ 526 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 527 host->base + MMCIMASK0); 528 return 0; 529} 530 531static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 532{ 533 struct mmci_host_next *next = &host->next_data; 534 535 if (data->host_cookie && data->host_cookie != next->cookie) { 536 pr_warning("[%s] invalid cookie: data->host_cookie %d" 537 " host->next_data.cookie %d\n", 538 __func__, data->host_cookie, host->next_data.cookie); 539 data->host_cookie = 0; 540 } 541 542 if (!data->host_cookie) 543 return; 544 545 host->dma_desc_current = next->dma_desc; 546 host->dma_current = next->dma_chan; 547 548 next->dma_desc = NULL; 549 next->dma_chan = NULL; 550} 551 552static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 553 bool is_first_req) 554{ 555 struct mmci_host *host = mmc_priv(mmc); 556 struct mmc_data *data = mrq->data; 557 struct mmci_host_next *nd = &host->next_data; 558 559 if (!data) 560 return; 561 562 if (data->host_cookie) { 563 data->host_cookie = 0; 564 return; 565 } 566 567 /* if config for dma */ 568 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 569 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 570 if (mmci_dma_prep_data(host, data, nd)) 571 data->host_cookie = 0; 572 else 573 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 574 } 575} 576 577static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 578 int err) 579{ 580 struct mmci_host *host = mmc_priv(mmc); 581 struct mmc_data *data = mrq->data; 582 struct dma_chan *chan; 583 enum dma_data_direction dir; 584 585 if (!data) 586 return; 587 588 if (data->flags & MMC_DATA_READ) { 589 dir = DMA_FROM_DEVICE; 590 chan = host->dma_rx_channel; 591 } else { 592 dir = DMA_TO_DEVICE; 593 chan = host->dma_tx_channel; 594 } 595 596 597 /* if config for dma */ 598 if (chan) { 599 if (err) 600 dmaengine_terminate_all(chan); 601 if (data->host_cookie) 602 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 603 data->sg_len, dir); 604 mrq->data->host_cookie = 0; 605 } 606} 607 608#else 609/* Blank functions if the DMA engine is not available */ 610static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 611{ 612} 613static inline void mmci_dma_setup(struct mmci_host *host) 614{ 615} 616 617static inline void mmci_dma_release(struct mmci_host *host) 618{ 619} 620 621static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 622{ 623} 624 625static inline void mmci_dma_data_error(struct mmci_host *host) 626{ 627} 628 629static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 630{ 631 return -ENOSYS; 632} 633 634#define mmci_pre_request NULL 635#define mmci_post_request NULL 636 637#endif 638 639static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 640{ 641 struct variant_data *variant = host->variant; 642 unsigned int datactrl, timeout, irqmask; 643 unsigned long long clks; 644 void __iomem *base; 645 int blksz_bits; 646 647 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 648 data->blksz, data->blocks, data->flags); 649 650 host->data = data; 651 host->size = data->blksz * data->blocks; 652 data->bytes_xfered = 0; 653 654 clks = (unsigned long long)data->timeout_ns * host->cclk; 655 do_div(clks, 1000000000UL); 656 657 timeout = data->timeout_clks + (unsigned int)clks; 658 659 base = host->base; 660 writel(timeout, base + MMCIDATATIMER); 661 writel(host->size, base + MMCIDATALENGTH); 662 663 blksz_bits = ffs(data->blksz) - 1; 664 BUG_ON(1 << blksz_bits != data->blksz); 665 666 if (variant->blksz_datactrl16) 667 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 668 else 669 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 670 671 if (data->flags & MMC_DATA_READ) 672 datactrl |= MCI_DPSM_DIRECTION; 673 674 /* The ST Micro variants has a special bit to enable SDIO */ 675 if (variant->sdio && host->mmc->card) 676 if (mmc_card_sdio(host->mmc->card)) { 677 /* 678 * The ST Micro variants has a special bit 679 * to enable SDIO. 680 */ 681 u32 clk; 682 683 datactrl |= MCI_ST_DPSM_SDIOEN; 684 685 /* 686 * The ST Micro variant for SDIO small write transfers 687 * needs to have clock H/W flow control disabled, 688 * otherwise the transfer will not start. The threshold 689 * depends on the rate of MCLK. 690 */ 691 if (data->flags & MMC_DATA_WRITE && 692 (host->size < 8 || 693 (host->size <= 8 && host->mclk > 50000000))) 694 clk = host->clk_reg & ~variant->clkreg_enable; 695 else 696 clk = host->clk_reg | variant->clkreg_enable; 697 698 mmci_write_clkreg(host, clk); 699 } 700 701 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 702 datactrl |= MCI_ST_DPSM_DDRMODE; 703 704 /* 705 * Attempt to use DMA operation mode, if this 706 * should fail, fall back to PIO mode 707 */ 708 if (!mmci_dma_start_data(host, datactrl)) 709 return; 710 711 /* IRQ mode, map the SG list for CPU reading/writing */ 712 mmci_init_sg(host, data); 713 714 if (data->flags & MMC_DATA_READ) { 715 irqmask = MCI_RXFIFOHALFFULLMASK; 716 717 /* 718 * If we have less than the fifo 'half-full' threshold to 719 * transfer, trigger a PIO interrupt as soon as any data 720 * is available. 721 */ 722 if (host->size < variant->fifohalfsize) 723 irqmask |= MCI_RXDATAAVLBLMASK; 724 } else { 725 /* 726 * We don't actually need to include "FIFO empty" here 727 * since its implicit in "FIFO half empty". 728 */ 729 irqmask = MCI_TXFIFOHALFEMPTYMASK; 730 } 731 732 writel(datactrl, base + MMCIDATACTRL); 733 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 734 mmci_set_mask1(host, irqmask); 735} 736 737static void 738mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 739{ 740 void __iomem *base = host->base; 741 742 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 743 cmd->opcode, cmd->arg, cmd->flags); 744 745 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 746 writel(0, base + MMCICOMMAND); 747 udelay(1); 748 } 749 750 c |= cmd->opcode | MCI_CPSM_ENABLE; 751 if (cmd->flags & MMC_RSP_PRESENT) { 752 if (cmd->flags & MMC_RSP_136) 753 c |= MCI_CPSM_LONGRSP; 754 c |= MCI_CPSM_RESPONSE; 755 } 756 if (/*interrupt*/0) 757 c |= MCI_CPSM_INTERRUPT; 758 759 host->cmd = cmd; 760 761 writel(cmd->arg, base + MMCIARGUMENT); 762 writel(c, base + MMCICOMMAND); 763} 764 765static void 766mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 767 unsigned int status) 768{ 769 /* First check for errors */ 770 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 771 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 772 u32 remain, success; 773 774 /* Terminate the DMA transfer */ 775 if (dma_inprogress(host)) 776 mmci_dma_data_error(host); 777 778 /* 779 * Calculate how far we are into the transfer. Note that 780 * the data counter gives the number of bytes transferred 781 * on the MMC bus, not on the host side. On reads, this 782 * can be as much as a FIFO-worth of data ahead. This 783 * matters for FIFO overruns only. 784 */ 785 remain = readl(host->base + MMCIDATACNT); 786 success = data->blksz * data->blocks - remain; 787 788 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 789 status, success); 790 if (status & MCI_DATACRCFAIL) { 791 /* Last block was not successful */ 792 success -= 1; 793 data->error = -EILSEQ; 794 } else if (status & MCI_DATATIMEOUT) { 795 data->error = -ETIMEDOUT; 796 } else if (status & MCI_STARTBITERR) { 797 data->error = -ECOMM; 798 } else if (status & MCI_TXUNDERRUN) { 799 data->error = -EIO; 800 } else if (status & MCI_RXOVERRUN) { 801 if (success > host->variant->fifosize) 802 success -= host->variant->fifosize; 803 else 804 success = 0; 805 data->error = -EIO; 806 } 807 data->bytes_xfered = round_down(success, data->blksz); 808 } 809 810 if (status & MCI_DATABLOCKEND) 811 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 812 813 if (status & MCI_DATAEND || data->error) { 814 if (dma_inprogress(host)) 815 mmci_dma_unmap(host, data); 816 mmci_stop_data(host); 817 818 if (!data->error) 819 /* The error clause is handled above, success! */ 820 data->bytes_xfered = data->blksz * data->blocks; 821 822 if (!data->stop) { 823 mmci_request_end(host, data->mrq); 824 } else { 825 mmci_start_command(host, data->stop, 0); 826 } 827 } 828} 829 830static void 831mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 832 unsigned int status) 833{ 834 void __iomem *base = host->base; 835 836 host->cmd = NULL; 837 838 if (status & MCI_CMDTIMEOUT) { 839 cmd->error = -ETIMEDOUT; 840 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 841 cmd->error = -EILSEQ; 842 } else { 843 cmd->resp[0] = readl(base + MMCIRESPONSE0); 844 cmd->resp[1] = readl(base + MMCIRESPONSE1); 845 cmd->resp[2] = readl(base + MMCIRESPONSE2); 846 cmd->resp[3] = readl(base + MMCIRESPONSE3); 847 } 848 849 if (!cmd->data || cmd->error) { 850 if (host->data) { 851 /* Terminate the DMA transfer */ 852 if (dma_inprogress(host)) 853 mmci_dma_data_error(host); 854 mmci_stop_data(host); 855 } 856 mmci_request_end(host, cmd->mrq); 857 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 858 mmci_start_data(host, cmd->data); 859 } 860} 861 862static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 863{ 864 void __iomem *base = host->base; 865 char *ptr = buffer; 866 u32 status; 867 int host_remain = host->size; 868 869 do { 870 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 871 872 if (count > remain) 873 count = remain; 874 875 if (count <= 0) 876 break; 877 878 /* 879 * SDIO especially may want to send something that is 880 * not divisible by 4 (as opposed to card sectors 881 * etc). Therefore make sure to always read the last bytes 882 * while only doing full 32-bit reads towards the FIFO. 883 */ 884 if (unlikely(count & 0x3)) { 885 if (count < 4) { 886 unsigned char buf[4]; 887 ioread32_rep(base + MMCIFIFO, buf, 1); 888 memcpy(ptr, buf, count); 889 } else { 890 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 891 count &= ~0x3; 892 } 893 } else { 894 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 895 } 896 897 ptr += count; 898 remain -= count; 899 host_remain -= count; 900 901 if (remain == 0) 902 break; 903 904 status = readl(base + MMCISTATUS); 905 } while (status & MCI_RXDATAAVLBL); 906 907 return ptr - buffer; 908} 909 910static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 911{ 912 struct variant_data *variant = host->variant; 913 void __iomem *base = host->base; 914 char *ptr = buffer; 915 916 do { 917 unsigned int count, maxcnt; 918 919 maxcnt = status & MCI_TXFIFOEMPTY ? 920 variant->fifosize : variant->fifohalfsize; 921 count = min(remain, maxcnt); 922 923 /* 924 * SDIO especially may want to send something that is 925 * not divisible by 4 (as opposed to card sectors 926 * etc), and the FIFO only accept full 32-bit writes. 927 * So compensate by adding +3 on the count, a single 928 * byte become a 32bit write, 7 bytes will be two 929 * 32bit writes etc. 930 */ 931 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 932 933 ptr += count; 934 remain -= count; 935 936 if (remain == 0) 937 break; 938 939 status = readl(base + MMCISTATUS); 940 } while (status & MCI_TXFIFOHALFEMPTY); 941 942 return ptr - buffer; 943} 944 945/* 946 * PIO data transfer IRQ handler. 947 */ 948static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 949{ 950 struct mmci_host *host = dev_id; 951 struct sg_mapping_iter *sg_miter = &host->sg_miter; 952 struct variant_data *variant = host->variant; 953 void __iomem *base = host->base; 954 unsigned long flags; 955 u32 status; 956 957 status = readl(base + MMCISTATUS); 958 959 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 960 961 local_irq_save(flags); 962 963 do { 964 unsigned int remain, len; 965 char *buffer; 966 967 /* 968 * For write, we only need to test the half-empty flag 969 * here - if the FIFO is completely empty, then by 970 * definition it is more than half empty. 971 * 972 * For read, check for data available. 973 */ 974 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 975 break; 976 977 if (!sg_miter_next(sg_miter)) 978 break; 979 980 buffer = sg_miter->addr; 981 remain = sg_miter->length; 982 983 len = 0; 984 if (status & MCI_RXACTIVE) 985 len = mmci_pio_read(host, buffer, remain); 986 if (status & MCI_TXACTIVE) 987 len = mmci_pio_write(host, buffer, remain, status); 988 989 sg_miter->consumed = len; 990 991 host->size -= len; 992 remain -= len; 993 994 if (remain) 995 break; 996 997 status = readl(base + MMCISTATUS); 998 } while (1); 999 1000 sg_miter_stop(sg_miter); 1001 1002 local_irq_restore(flags); 1003 1004 /* 1005 * If we have less than the fifo 'half-full' threshold to transfer, 1006 * trigger a PIO interrupt as soon as any data is available. 1007 */ 1008 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1009 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1010 1011 /* 1012 * If we run out of data, disable the data IRQs; this 1013 * prevents a race where the FIFO becomes empty before 1014 * the chip itself has disabled the data path, and 1015 * stops us racing with our data end IRQ. 1016 */ 1017 if (host->size == 0) { 1018 mmci_set_mask1(host, 0); 1019 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1020 } 1021 1022 return IRQ_HANDLED; 1023} 1024 1025/* 1026 * Handle completion of command and data transfers. 1027 */ 1028static irqreturn_t mmci_irq(int irq, void *dev_id) 1029{ 1030 struct mmci_host *host = dev_id; 1031 u32 status; 1032 int ret = 0; 1033 1034 spin_lock(&host->lock); 1035 1036 do { 1037 struct mmc_command *cmd; 1038 struct mmc_data *data; 1039 1040 status = readl(host->base + MMCISTATUS); 1041 1042 if (host->singleirq) { 1043 if (status & readl(host->base + MMCIMASK1)) 1044 mmci_pio_irq(irq, dev_id); 1045 1046 status &= ~MCI_IRQ1MASK; 1047 } 1048 1049 status &= readl(host->base + MMCIMASK0); 1050 writel(status, host->base + MMCICLEAR); 1051 1052 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1053 1054 data = host->data; 1055 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1056 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1057 MCI_DATABLOCKEND) && data) 1058 mmci_data_irq(host, data, status); 1059 1060 cmd = host->cmd; 1061 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1062 mmci_cmd_irq(host, cmd, status); 1063 1064 ret = 1; 1065 } while (status); 1066 1067 spin_unlock(&host->lock); 1068 1069 return IRQ_RETVAL(ret); 1070} 1071 1072static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1073{ 1074 struct mmci_host *host = mmc_priv(mmc); 1075 unsigned long flags; 1076 1077 WARN_ON(host->mrq != NULL); 1078 1079 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1080 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 1081 mrq->data->blksz); 1082 mrq->cmd->error = -EINVAL; 1083 mmc_request_done(mmc, mrq); 1084 return; 1085 } 1086 1087 pm_runtime_get_sync(mmc_dev(mmc)); 1088 1089 spin_lock_irqsave(&host->lock, flags); 1090 1091 host->mrq = mrq; 1092 1093 if (mrq->data) 1094 mmci_get_next_data(host, mrq->data); 1095 1096 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1097 mmci_start_data(host, mrq->data); 1098 1099 mmci_start_command(host, mrq->cmd, 0); 1100 1101 spin_unlock_irqrestore(&host->lock, flags); 1102} 1103 1104static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1105{ 1106 struct mmci_host *host = mmc_priv(mmc); 1107 struct variant_data *variant = host->variant; 1108 u32 pwr = 0; 1109 unsigned long flags; 1110 1111 pm_runtime_get_sync(mmc_dev(mmc)); 1112 1113 if (host->plat->ios_handler && 1114 host->plat->ios_handler(mmc_dev(mmc), ios)) 1115 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1116 1117 switch (ios->power_mode) { 1118 case MMC_POWER_OFF: 1119 if (!IS_ERR(mmc->supply.vmmc)) 1120 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1121 break; 1122 case MMC_POWER_UP: 1123 if (!IS_ERR(mmc->supply.vmmc)) 1124 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1125 1126 /* 1127 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1128 * and instead uses MCI_PWR_ON so apply whatever value is 1129 * configured in the variant data. 1130 */ 1131 pwr |= variant->pwrreg_powerup; 1132 1133 break; 1134 case MMC_POWER_ON: 1135 pwr |= MCI_PWR_ON; 1136 break; 1137 } 1138 1139 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1140 /* 1141 * The ST Micro variant has some additional bits 1142 * indicating signal direction for the signals in 1143 * the SD/MMC bus and feedback-clock usage. 1144 */ 1145 pwr |= host->plat->sigdir; 1146 1147 if (ios->bus_width == MMC_BUS_WIDTH_4) 1148 pwr &= ~MCI_ST_DATA74DIREN; 1149 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1150 pwr &= (~MCI_ST_DATA74DIREN & 1151 ~MCI_ST_DATA31DIREN & 1152 ~MCI_ST_DATA2DIREN); 1153 } 1154 1155 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1156 if (host->hw_designer != AMBA_VENDOR_ST) 1157 pwr |= MCI_ROD; 1158 else { 1159 /* 1160 * The ST Micro variant use the ROD bit for something 1161 * else and only has OD (Open Drain). 1162 */ 1163 pwr |= MCI_OD; 1164 } 1165 } 1166 1167 /* 1168 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1169 * gating the clock, the MCI_PWR_ON bit is cleared. 1170 */ 1171 if (!ios->clock && variant->pwrreg_clkgate) 1172 pwr &= ~MCI_PWR_ON; 1173 1174 spin_lock_irqsave(&host->lock, flags); 1175 1176 mmci_set_clkreg(host, ios->clock); 1177 mmci_write_pwrreg(host, pwr); 1178 1179 spin_unlock_irqrestore(&host->lock, flags); 1180 1181 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1182 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1183} 1184 1185static int mmci_get_ro(struct mmc_host *mmc) 1186{ 1187 struct mmci_host *host = mmc_priv(mmc); 1188 1189 if (host->gpio_wp == -ENOSYS) 1190 return -ENOSYS; 1191 1192 return gpio_get_value_cansleep(host->gpio_wp); 1193} 1194 1195static int mmci_get_cd(struct mmc_host *mmc) 1196{ 1197 struct mmci_host *host = mmc_priv(mmc); 1198 struct mmci_platform_data *plat = host->plat; 1199 unsigned int status; 1200 1201 if (host->gpio_cd == -ENOSYS) { 1202 if (!plat->status) 1203 return 1; /* Assume always present */ 1204 1205 status = plat->status(mmc_dev(host->mmc)); 1206 } else 1207 status = !!gpio_get_value_cansleep(host->gpio_cd) 1208 ^ plat->cd_invert; 1209 1210 /* 1211 * Use positive logic throughout - status is zero for no card, 1212 * non-zero for card inserted. 1213 */ 1214 return status; 1215} 1216 1217static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1218{ 1219 struct mmci_host *host = dev_id; 1220 1221 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1222 1223 return IRQ_HANDLED; 1224} 1225 1226static const struct mmc_host_ops mmci_ops = { 1227 .request = mmci_request, 1228 .pre_req = mmci_pre_request, 1229 .post_req = mmci_post_request, 1230 .set_ios = mmci_set_ios, 1231 .get_ro = mmci_get_ro, 1232 .get_cd = mmci_get_cd, 1233}; 1234 1235#ifdef CONFIG_OF 1236static void mmci_dt_populate_generic_pdata(struct device_node *np, 1237 struct mmci_platform_data *pdata) 1238{ 1239 int bus_width = 0; 1240 1241 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1242 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1243 1244 if (of_get_property(np, "cd-inverted", NULL)) 1245 pdata->cd_invert = true; 1246 else 1247 pdata->cd_invert = false; 1248 1249 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1250 if (!pdata->f_max) 1251 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1252 1253 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1254 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1255 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1256 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1257 1258 of_property_read_u32(np, "bus-width", &bus_width); 1259 switch (bus_width) { 1260 case 0 : 1261 /* No bus-width supplied. */ 1262 break; 1263 case 4 : 1264 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1265 break; 1266 case 8 : 1267 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1268 break; 1269 default : 1270 pr_warn("%s: Unsupported bus width\n", np->full_name); 1271 } 1272} 1273#else 1274static void mmci_dt_populate_generic_pdata(struct device_node *np, 1275 struct mmci_platform_data *pdata) 1276{ 1277 return; 1278} 1279#endif 1280 1281static int mmci_probe(struct amba_device *dev, 1282 const struct amba_id *id) 1283{ 1284 struct mmci_platform_data *plat = dev->dev.platform_data; 1285 struct device_node *np = dev->dev.of_node; 1286 struct variant_data *variant = id->data; 1287 struct mmci_host *host; 1288 struct mmc_host *mmc; 1289 int ret; 1290 1291 /* Must have platform data or Device Tree. */ 1292 if (!plat && !np) { 1293 dev_err(&dev->dev, "No plat data or DT found\n"); 1294 return -EINVAL; 1295 } 1296 1297 if (!plat) { 1298 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1299 if (!plat) 1300 return -ENOMEM; 1301 } 1302 1303 if (np) 1304 mmci_dt_populate_generic_pdata(np, plat); 1305 1306 ret = amba_request_regions(dev, DRIVER_NAME); 1307 if (ret) 1308 goto out; 1309 1310 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1311 if (!mmc) { 1312 ret = -ENOMEM; 1313 goto rel_regions; 1314 } 1315 1316 host = mmc_priv(mmc); 1317 host->mmc = mmc; 1318 1319 host->gpio_wp = -ENOSYS; 1320 host->gpio_cd = -ENOSYS; 1321 host->gpio_cd_irq = -1; 1322 1323 host->hw_designer = amba_manf(dev); 1324 host->hw_revision = amba_rev(dev); 1325 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1326 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1327 1328 host->clk = clk_get(&dev->dev, NULL); 1329 if (IS_ERR(host->clk)) { 1330 ret = PTR_ERR(host->clk); 1331 host->clk = NULL; 1332 goto host_free; 1333 } 1334 1335 ret = clk_prepare_enable(host->clk); 1336 if (ret) 1337 goto clk_free; 1338 1339 host->plat = plat; 1340 host->variant = variant; 1341 host->mclk = clk_get_rate(host->clk); 1342 /* 1343 * According to the spec, mclk is max 100 MHz, 1344 * so we try to adjust the clock down to this, 1345 * (if possible). 1346 */ 1347 if (host->mclk > 100000000) { 1348 ret = clk_set_rate(host->clk, 100000000); 1349 if (ret < 0) 1350 goto clk_disable; 1351 host->mclk = clk_get_rate(host->clk); 1352 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1353 host->mclk); 1354 } 1355 host->phybase = dev->res.start; 1356 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1357 if (!host->base) { 1358 ret = -ENOMEM; 1359 goto clk_disable; 1360 } 1361 1362 mmc->ops = &mmci_ops; 1363 /* 1364 * The ARM and ST versions of the block have slightly different 1365 * clock divider equations which means that the minimum divider 1366 * differs too. 1367 */ 1368 if (variant->st_clkdiv) 1369 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1370 else 1371 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1372 /* 1373 * If the platform data supplies a maximum operating 1374 * frequency, this takes precedence. Else, we fall back 1375 * to using the module parameter, which has a (low) 1376 * default value in case it is not specified. Either 1377 * value must not exceed the clock rate into the block, 1378 * of course. 1379 */ 1380 if (plat->f_max) 1381 mmc->f_max = min(host->mclk, plat->f_max); 1382 else 1383 mmc->f_max = min(host->mclk, fmax); 1384 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1385 1386 host->pinctrl = devm_pinctrl_get(&dev->dev); 1387 if (IS_ERR(host->pinctrl)) { 1388 ret = PTR_ERR(host->pinctrl); 1389 goto clk_disable; 1390 } 1391 1392 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1393 PINCTRL_STATE_DEFAULT); 1394 1395 /* enable pins to be muxed in and configured */ 1396 if (!IS_ERR(host->pins_default)) { 1397 ret = pinctrl_select_state(host->pinctrl, host->pins_default); 1398 if (ret) 1399 dev_warn(&dev->dev, "could not set default pins\n"); 1400 } else 1401 dev_warn(&dev->dev, "could not get default pinstate\n"); 1402 1403 /* Get regulators and the supported OCR mask */ 1404 mmc_regulator_get_supply(mmc); 1405 if (!mmc->ocr_avail) 1406 mmc->ocr_avail = plat->ocr_mask; 1407 else if (plat->ocr_mask) 1408 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1409 1410 mmc->caps = plat->capabilities; 1411 mmc->caps2 = plat->capabilities2; 1412 1413 /* We support these PM capabilities. */ 1414 mmc->pm_caps = MMC_PM_KEEP_POWER; 1415 1416 /* 1417 * We can do SGIO 1418 */ 1419 mmc->max_segs = NR_SG; 1420 1421 /* 1422 * Since only a certain number of bits are valid in the data length 1423 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1424 * single request. 1425 */ 1426 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1427 1428 /* 1429 * Set the maximum segment size. Since we aren't doing DMA 1430 * (yet) we are only limited by the data length register. 1431 */ 1432 mmc->max_seg_size = mmc->max_req_size; 1433 1434 /* 1435 * Block size can be up to 2048 bytes, but must be a power of two. 1436 */ 1437 mmc->max_blk_size = 1 << 11; 1438 1439 /* 1440 * Limit the number of blocks transferred so that we don't overflow 1441 * the maximum request size. 1442 */ 1443 mmc->max_blk_count = mmc->max_req_size >> 11; 1444 1445 spin_lock_init(&host->lock); 1446 1447 writel(0, host->base + MMCIMASK0); 1448 writel(0, host->base + MMCIMASK1); 1449 writel(0xfff, host->base + MMCICLEAR); 1450 1451 if (plat->gpio_cd == -EPROBE_DEFER) { 1452 ret = -EPROBE_DEFER; 1453 goto err_gpio_cd; 1454 } 1455 if (gpio_is_valid(plat->gpio_cd)) { 1456 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1457 if (ret == 0) 1458 ret = gpio_direction_input(plat->gpio_cd); 1459 if (ret == 0) 1460 host->gpio_cd = plat->gpio_cd; 1461 else if (ret != -ENOSYS) 1462 goto err_gpio_cd; 1463 1464 /* 1465 * A gpio pin that will detect cards when inserted and removed 1466 * will most likely want to trigger on the edges if it is 1467 * 0 when ejected and 1 when inserted (or mutatis mutandis 1468 * for the inverted case) so we request triggers on both 1469 * edges. 1470 */ 1471 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1472 mmci_cd_irq, 1473 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1474 DRIVER_NAME " (cd)", host); 1475 if (ret >= 0) 1476 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1477 } 1478 if (plat->gpio_wp == -EPROBE_DEFER) { 1479 ret = -EPROBE_DEFER; 1480 goto err_gpio_wp; 1481 } 1482 if (gpio_is_valid(plat->gpio_wp)) { 1483 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1484 if (ret == 0) 1485 ret = gpio_direction_input(plat->gpio_wp); 1486 if (ret == 0) 1487 host->gpio_wp = plat->gpio_wp; 1488 else if (ret != -ENOSYS) 1489 goto err_gpio_wp; 1490 } 1491 1492 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1493 && host->gpio_cd_irq < 0) 1494 mmc->caps |= MMC_CAP_NEEDS_POLL; 1495 1496 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1497 if (ret) 1498 goto unmap; 1499 1500 if (!dev->irq[1]) 1501 host->singleirq = true; 1502 else { 1503 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1504 DRIVER_NAME " (pio)", host); 1505 if (ret) 1506 goto irq0_free; 1507 } 1508 1509 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1510 1511 amba_set_drvdata(dev, mmc); 1512 1513 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1514 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1515 amba_rev(dev), (unsigned long long)dev->res.start, 1516 dev->irq[0], dev->irq[1]); 1517 1518 mmci_dma_setup(host); 1519 1520 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1521 pm_runtime_use_autosuspend(&dev->dev); 1522 pm_runtime_put(&dev->dev); 1523 1524 mmc_add_host(mmc); 1525 1526 return 0; 1527 1528 irq0_free: 1529 free_irq(dev->irq[0], host); 1530 unmap: 1531 if (host->gpio_wp != -ENOSYS) 1532 gpio_free(host->gpio_wp); 1533 err_gpio_wp: 1534 if (host->gpio_cd_irq >= 0) 1535 free_irq(host->gpio_cd_irq, host); 1536 if (host->gpio_cd != -ENOSYS) 1537 gpio_free(host->gpio_cd); 1538 err_gpio_cd: 1539 iounmap(host->base); 1540 clk_disable: 1541 clk_disable_unprepare(host->clk); 1542 clk_free: 1543 clk_put(host->clk); 1544 host_free: 1545 mmc_free_host(mmc); 1546 rel_regions: 1547 amba_release_regions(dev); 1548 out: 1549 return ret; 1550} 1551 1552static int mmci_remove(struct amba_device *dev) 1553{ 1554 struct mmc_host *mmc = amba_get_drvdata(dev); 1555 1556 amba_set_drvdata(dev, NULL); 1557 1558 if (mmc) { 1559 struct mmci_host *host = mmc_priv(mmc); 1560 1561 /* 1562 * Undo pm_runtime_put() in probe. We use the _sync 1563 * version here so that we can access the primecell. 1564 */ 1565 pm_runtime_get_sync(&dev->dev); 1566 1567 mmc_remove_host(mmc); 1568 1569 writel(0, host->base + MMCIMASK0); 1570 writel(0, host->base + MMCIMASK1); 1571 1572 writel(0, host->base + MMCICOMMAND); 1573 writel(0, host->base + MMCIDATACTRL); 1574 1575 mmci_dma_release(host); 1576 free_irq(dev->irq[0], host); 1577 if (!host->singleirq) 1578 free_irq(dev->irq[1], host); 1579 1580 if (host->gpio_wp != -ENOSYS) 1581 gpio_free(host->gpio_wp); 1582 if (host->gpio_cd_irq >= 0) 1583 free_irq(host->gpio_cd_irq, host); 1584 if (host->gpio_cd != -ENOSYS) 1585 gpio_free(host->gpio_cd); 1586 1587 iounmap(host->base); 1588 clk_disable_unprepare(host->clk); 1589 clk_put(host->clk); 1590 1591 mmc_free_host(mmc); 1592 1593 amba_release_regions(dev); 1594 } 1595 1596 return 0; 1597} 1598 1599#ifdef CONFIG_SUSPEND 1600static int mmci_suspend(struct device *dev) 1601{ 1602 struct amba_device *adev = to_amba_device(dev); 1603 struct mmc_host *mmc = amba_get_drvdata(adev); 1604 int ret = 0; 1605 1606 if (mmc) { 1607 struct mmci_host *host = mmc_priv(mmc); 1608 1609 ret = mmc_suspend_host(mmc); 1610 if (ret == 0) { 1611 pm_runtime_get_sync(dev); 1612 writel(0, host->base + MMCIMASK0); 1613 } 1614 } 1615 1616 return ret; 1617} 1618 1619static int mmci_resume(struct device *dev) 1620{ 1621 struct amba_device *adev = to_amba_device(dev); 1622 struct mmc_host *mmc = amba_get_drvdata(adev); 1623 int ret = 0; 1624 1625 if (mmc) { 1626 struct mmci_host *host = mmc_priv(mmc); 1627 1628 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1629 pm_runtime_put(dev); 1630 1631 ret = mmc_resume_host(mmc); 1632 } 1633 1634 return ret; 1635} 1636#endif 1637 1638#ifdef CONFIG_PM_RUNTIME 1639static int mmci_runtime_suspend(struct device *dev) 1640{ 1641 struct amba_device *adev = to_amba_device(dev); 1642 struct mmc_host *mmc = amba_get_drvdata(adev); 1643 1644 if (mmc) { 1645 struct mmci_host *host = mmc_priv(mmc); 1646 clk_disable_unprepare(host->clk); 1647 } 1648 1649 return 0; 1650} 1651 1652static int mmci_runtime_resume(struct device *dev) 1653{ 1654 struct amba_device *adev = to_amba_device(dev); 1655 struct mmc_host *mmc = amba_get_drvdata(adev); 1656 1657 if (mmc) { 1658 struct mmci_host *host = mmc_priv(mmc); 1659 clk_prepare_enable(host->clk); 1660 } 1661 1662 return 0; 1663} 1664#endif 1665 1666static const struct dev_pm_ops mmci_dev_pm_ops = { 1667 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1668 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1669}; 1670 1671static struct amba_id mmci_ids[] = { 1672 { 1673 .id = 0x00041180, 1674 .mask = 0xff0fffff, 1675 .data = &variant_arm, 1676 }, 1677 { 1678 .id = 0x01041180, 1679 .mask = 0xff0fffff, 1680 .data = &variant_arm_extended_fifo, 1681 }, 1682 { 1683 .id = 0x02041180, 1684 .mask = 0xff0fffff, 1685 .data = &variant_arm_extended_fifo_hwfc, 1686 }, 1687 { 1688 .id = 0x00041181, 1689 .mask = 0x000fffff, 1690 .data = &variant_arm, 1691 }, 1692 /* ST Micro variants */ 1693 { 1694 .id = 0x00180180, 1695 .mask = 0x00ffffff, 1696 .data = &variant_u300, 1697 }, 1698 { 1699 .id = 0x10180180, 1700 .mask = 0xf0ffffff, 1701 .data = &variant_nomadik, 1702 }, 1703 { 1704 .id = 0x00280180, 1705 .mask = 0x00ffffff, 1706 .data = &variant_u300, 1707 }, 1708 { 1709 .id = 0x00480180, 1710 .mask = 0xf0ffffff, 1711 .data = &variant_ux500, 1712 }, 1713 { 1714 .id = 0x10480180, 1715 .mask = 0xf0ffffff, 1716 .data = &variant_ux500v2, 1717 }, 1718 { 0, 0 }, 1719}; 1720 1721MODULE_DEVICE_TABLE(amba, mmci_ids); 1722 1723static struct amba_driver mmci_driver = { 1724 .drv = { 1725 .name = DRIVER_NAME, 1726 .pm = &mmci_dev_pm_ops, 1727 }, 1728 .probe = mmci_probe, 1729 .remove = mmci_remove, 1730 .id_table = mmci_ids, 1731}; 1732 1733module_amba_driver(mmci_driver); 1734 1735module_param(fmax, uint, 0444); 1736 1737MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1738MODULE_LICENSE("GPL"); 1739