mmci.c revision 571dce4f105cf2b8e57ec4330da71bd0cb6d38bb
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/highmem.h> 22#include <linux/log2.h> 23#include <linux/mmc/pm.h> 24#include <linux/mmc/host.h> 25#include <linux/mmc/card.h> 26#include <linux/amba/bus.h> 27#include <linux/clk.h> 28#include <linux/scatterlist.h> 29#include <linux/gpio.h> 30#include <linux/of_gpio.h> 31#include <linux/regulator/consumer.h> 32#include <linux/dmaengine.h> 33#include <linux/dma-mapping.h> 34#include <linux/amba/mmci.h> 35#include <linux/pm_runtime.h> 36#include <linux/types.h> 37#include <linux/pinctrl/consumer.h> 38 39#include <asm/div64.h> 40#include <asm/io.h> 41#include <asm/sizes.h> 42 43#include "mmci.h" 44 45#define DRIVER_NAME "mmci-pl18x" 46 47static unsigned int fmax = 515633; 48 49/** 50 * struct variant_data - MMCI variant-specific quirks 51 * @clkreg: default value for MCICLOCK register 52 * @clkreg_enable: enable value for MMCICLOCK register 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 55 * is asserted (likewise for RX) 56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 57 * is asserted (likewise for RX) 58 * @sdio: variant supports SDIO 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 61 * @pwrreg_powerup: power up value for MMCIPOWER register 62 * @signal_direction: input/out direction of bus signals can be indicated 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 64 * @busy_detect: true if busy detection on dat0 is supported 65 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 66 */ 67struct variant_data { 68 unsigned int clkreg; 69 unsigned int clkreg_enable; 70 unsigned int datalength_bits; 71 unsigned int fifosize; 72 unsigned int fifohalfsize; 73 bool sdio; 74 bool st_clkdiv; 75 bool blksz_datactrl16; 76 u32 pwrreg_powerup; 77 bool signal_direction; 78 bool pwrreg_clkgate; 79 bool busy_detect; 80 bool pwrreg_nopower; 81}; 82 83static struct variant_data variant_arm = { 84 .fifosize = 16 * 4, 85 .fifohalfsize = 8 * 4, 86 .datalength_bits = 16, 87 .pwrreg_powerup = MCI_PWR_UP, 88}; 89 90static struct variant_data variant_arm_extended_fifo = { 91 .fifosize = 128 * 4, 92 .fifohalfsize = 64 * 4, 93 .datalength_bits = 16, 94 .pwrreg_powerup = MCI_PWR_UP, 95}; 96 97static struct variant_data variant_arm_extended_fifo_hwfc = { 98 .fifosize = 128 * 4, 99 .fifohalfsize = 64 * 4, 100 .clkreg_enable = MCI_ARM_HWFCEN, 101 .datalength_bits = 16, 102 .pwrreg_powerup = MCI_PWR_UP, 103}; 104 105static struct variant_data variant_u300 = { 106 .fifosize = 16 * 4, 107 .fifohalfsize = 8 * 4, 108 .clkreg_enable = MCI_ST_U300_HWFCEN, 109 .datalength_bits = 16, 110 .sdio = true, 111 .pwrreg_powerup = MCI_PWR_ON, 112 .signal_direction = true, 113 .pwrreg_clkgate = true, 114 .pwrreg_nopower = true, 115}; 116 117static struct variant_data variant_nomadik = { 118 .fifosize = 16 * 4, 119 .fifohalfsize = 8 * 4, 120 .clkreg = MCI_CLK_ENABLE, 121 .datalength_bits = 24, 122 .sdio = true, 123 .st_clkdiv = true, 124 .pwrreg_powerup = MCI_PWR_ON, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128}; 129 130static struct variant_data variant_ux500 = { 131 .fifosize = 30 * 4, 132 .fifohalfsize = 8 * 4, 133 .clkreg = MCI_CLK_ENABLE, 134 .clkreg_enable = MCI_ST_UX500_HWFCEN, 135 .datalength_bits = 24, 136 .sdio = true, 137 .st_clkdiv = true, 138 .pwrreg_powerup = MCI_PWR_ON, 139 .signal_direction = true, 140 .pwrreg_clkgate = true, 141 .busy_detect = true, 142 .pwrreg_nopower = true, 143}; 144 145static struct variant_data variant_ux500v2 = { 146 .fifosize = 30 * 4, 147 .fifohalfsize = 8 * 4, 148 .clkreg = MCI_CLK_ENABLE, 149 .clkreg_enable = MCI_ST_UX500_HWFCEN, 150 .datalength_bits = 24, 151 .sdio = true, 152 .st_clkdiv = true, 153 .blksz_datactrl16 = true, 154 .pwrreg_powerup = MCI_PWR_ON, 155 .signal_direction = true, 156 .pwrreg_clkgate = true, 157 .busy_detect = true, 158 .pwrreg_nopower = true, 159}; 160 161static int mmci_card_busy(struct mmc_host *mmc) 162{ 163 struct mmci_host *host = mmc_priv(mmc); 164 unsigned long flags; 165 int busy = 0; 166 167 pm_runtime_get_sync(mmc_dev(mmc)); 168 169 spin_lock_irqsave(&host->lock, flags); 170 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 171 busy = 1; 172 spin_unlock_irqrestore(&host->lock, flags); 173 174 pm_runtime_mark_last_busy(mmc_dev(mmc)); 175 pm_runtime_put_autosuspend(mmc_dev(mmc)); 176 177 return busy; 178} 179 180/* 181 * Validate mmc prerequisites 182 */ 183static int mmci_validate_data(struct mmci_host *host, 184 struct mmc_data *data) 185{ 186 if (!data) 187 return 0; 188 189 if (!is_power_of_2(data->blksz)) { 190 dev_err(mmc_dev(host->mmc), 191 "unsupported block size (%d bytes)\n", data->blksz); 192 return -EINVAL; 193 } 194 195 return 0; 196} 197 198static void mmci_reg_delay(struct mmci_host *host) 199{ 200 /* 201 * According to the spec, at least three feedback clock cycles 202 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 203 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 204 * Worst delay time during card init is at 100 kHz => 30 us. 205 * Worst delay time when up and running is at 25 MHz => 120 ns. 206 */ 207 if (host->cclk < 25000000) 208 udelay(30); 209 else 210 ndelay(120); 211} 212 213/* 214 * This must be called with host->lock held 215 */ 216static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 217{ 218 if (host->clk_reg != clk) { 219 host->clk_reg = clk; 220 writel(clk, host->base + MMCICLOCK); 221 } 222} 223 224/* 225 * This must be called with host->lock held 226 */ 227static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 228{ 229 if (host->pwr_reg != pwr) { 230 host->pwr_reg = pwr; 231 writel(pwr, host->base + MMCIPOWER); 232 } 233} 234 235/* 236 * This must be called with host->lock held 237 */ 238static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 239{ 240 /* Keep ST Micro busy mode if enabled */ 241 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 242 243 if (host->datactrl_reg != datactrl) { 244 host->datactrl_reg = datactrl; 245 writel(datactrl, host->base + MMCIDATACTRL); 246 } 247} 248 249/* 250 * This must be called with host->lock held 251 */ 252static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 253{ 254 struct variant_data *variant = host->variant; 255 u32 clk = variant->clkreg; 256 257 /* Make sure cclk reflects the current calculated clock */ 258 host->cclk = 0; 259 260 if (desired) { 261 if (desired >= host->mclk) { 262 clk = MCI_CLK_BYPASS; 263 if (variant->st_clkdiv) 264 clk |= MCI_ST_UX500_NEG_EDGE; 265 host->cclk = host->mclk; 266 } else if (variant->st_clkdiv) { 267 /* 268 * DB8500 TRM says f = mclk / (clkdiv + 2) 269 * => clkdiv = (mclk / f) - 2 270 * Round the divider up so we don't exceed the max 271 * frequency 272 */ 273 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 274 if (clk >= 256) 275 clk = 255; 276 host->cclk = host->mclk / (clk + 2); 277 } else { 278 /* 279 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 280 * => clkdiv = mclk / (2 * f) - 1 281 */ 282 clk = host->mclk / (2 * desired) - 1; 283 if (clk >= 256) 284 clk = 255; 285 host->cclk = host->mclk / (2 * (clk + 1)); 286 } 287 288 clk |= variant->clkreg_enable; 289 clk |= MCI_CLK_ENABLE; 290 /* This hasn't proven to be worthwhile */ 291 /* clk |= MCI_CLK_PWRSAVE; */ 292 } 293 294 /* Set actual clock for debug */ 295 host->mmc->actual_clock = host->cclk; 296 297 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 298 clk |= MCI_4BIT_BUS; 299 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 300 clk |= MCI_ST_8BIT_BUS; 301 302 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 303 clk |= MCI_ST_UX500_NEG_EDGE; 304 305 mmci_write_clkreg(host, clk); 306} 307 308static void 309mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 310{ 311 writel(0, host->base + MMCICOMMAND); 312 313 BUG_ON(host->data); 314 315 host->mrq = NULL; 316 host->cmd = NULL; 317 318 mmc_request_done(host->mmc, mrq); 319 320 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 321 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 322} 323 324static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 325{ 326 void __iomem *base = host->base; 327 328 if (host->singleirq) { 329 unsigned int mask0 = readl(base + MMCIMASK0); 330 331 mask0 &= ~MCI_IRQ1MASK; 332 mask0 |= mask; 333 334 writel(mask0, base + MMCIMASK0); 335 } 336 337 writel(mask, base + MMCIMASK1); 338} 339 340static void mmci_stop_data(struct mmci_host *host) 341{ 342 mmci_write_datactrlreg(host, 0); 343 mmci_set_mask1(host, 0); 344 host->data = NULL; 345} 346 347static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 348{ 349 unsigned int flags = SG_MITER_ATOMIC; 350 351 if (data->flags & MMC_DATA_READ) 352 flags |= SG_MITER_TO_SG; 353 else 354 flags |= SG_MITER_FROM_SG; 355 356 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 357} 358 359/* 360 * All the DMA operation mode stuff goes inside this ifdef. 361 * This assumes that you have a generic DMA device interface, 362 * no custom DMA interfaces are supported. 363 */ 364#ifdef CONFIG_DMA_ENGINE 365static void mmci_dma_setup(struct mmci_host *host) 366{ 367 struct mmci_platform_data *plat = host->plat; 368 const char *rxname, *txname; 369 dma_cap_mask_t mask; 370 371 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 372 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 373 374 /* initialize pre request cookie */ 375 host->next_data.cookie = 1; 376 377 /* Try to acquire a generic DMA engine slave channel */ 378 dma_cap_zero(mask); 379 dma_cap_set(DMA_SLAVE, mask); 380 381 if (plat && plat->dma_filter) { 382 if (!host->dma_rx_channel && plat->dma_rx_param) { 383 host->dma_rx_channel = dma_request_channel(mask, 384 plat->dma_filter, 385 plat->dma_rx_param); 386 /* E.g if no DMA hardware is present */ 387 if (!host->dma_rx_channel) 388 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 389 } 390 391 if (!host->dma_tx_channel && plat->dma_tx_param) { 392 host->dma_tx_channel = dma_request_channel(mask, 393 plat->dma_filter, 394 plat->dma_tx_param); 395 if (!host->dma_tx_channel) 396 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 397 } 398 } 399 400 /* 401 * If only an RX channel is specified, the driver will 402 * attempt to use it bidirectionally, however if it is 403 * is specified but cannot be located, DMA will be disabled. 404 */ 405 if (host->dma_rx_channel && !host->dma_tx_channel) 406 host->dma_tx_channel = host->dma_rx_channel; 407 408 if (host->dma_rx_channel) 409 rxname = dma_chan_name(host->dma_rx_channel); 410 else 411 rxname = "none"; 412 413 if (host->dma_tx_channel) 414 txname = dma_chan_name(host->dma_tx_channel); 415 else 416 txname = "none"; 417 418 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 419 rxname, txname); 420 421 /* 422 * Limit the maximum segment size in any SG entry according to 423 * the parameters of the DMA engine device. 424 */ 425 if (host->dma_tx_channel) { 426 struct device *dev = host->dma_tx_channel->device->dev; 427 unsigned int max_seg_size = dma_get_max_seg_size(dev); 428 429 if (max_seg_size < host->mmc->max_seg_size) 430 host->mmc->max_seg_size = max_seg_size; 431 } 432 if (host->dma_rx_channel) { 433 struct device *dev = host->dma_rx_channel->device->dev; 434 unsigned int max_seg_size = dma_get_max_seg_size(dev); 435 436 if (max_seg_size < host->mmc->max_seg_size) 437 host->mmc->max_seg_size = max_seg_size; 438 } 439} 440 441/* 442 * This is used in or so inline it 443 * so it can be discarded. 444 */ 445static inline void mmci_dma_release(struct mmci_host *host) 446{ 447 struct mmci_platform_data *plat = host->plat; 448 449 if (host->dma_rx_channel) 450 dma_release_channel(host->dma_rx_channel); 451 if (host->dma_tx_channel && plat->dma_tx_param) 452 dma_release_channel(host->dma_tx_channel); 453 host->dma_rx_channel = host->dma_tx_channel = NULL; 454} 455 456static void mmci_dma_data_error(struct mmci_host *host) 457{ 458 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 459 dmaengine_terminate_all(host->dma_current); 460 host->dma_current = NULL; 461 host->dma_desc_current = NULL; 462 host->data->host_cookie = 0; 463} 464 465static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 466{ 467 struct dma_chan *chan; 468 enum dma_data_direction dir; 469 470 if (data->flags & MMC_DATA_READ) { 471 dir = DMA_FROM_DEVICE; 472 chan = host->dma_rx_channel; 473 } else { 474 dir = DMA_TO_DEVICE; 475 chan = host->dma_tx_channel; 476 } 477 478 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 479} 480 481static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 482{ 483 u32 status; 484 int i; 485 486 /* Wait up to 1ms for the DMA to complete */ 487 for (i = 0; ; i++) { 488 status = readl(host->base + MMCISTATUS); 489 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 490 break; 491 udelay(10); 492 } 493 494 /* 495 * Check to see whether we still have some data left in the FIFO - 496 * this catches DMA controllers which are unable to monitor the 497 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 498 * contiguous buffers. On TX, we'll get a FIFO underrun error. 499 */ 500 if (status & MCI_RXDATAAVLBLMASK) { 501 mmci_dma_data_error(host); 502 if (!data->error) 503 data->error = -EIO; 504 } 505 506 if (!data->host_cookie) 507 mmci_dma_unmap(host, data); 508 509 /* 510 * Use of DMA with scatter-gather is impossible. 511 * Give up with DMA and switch back to PIO mode. 512 */ 513 if (status & MCI_RXDATAAVLBLMASK) { 514 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 515 mmci_dma_release(host); 516 } 517 518 host->dma_current = NULL; 519 host->dma_desc_current = NULL; 520} 521 522/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 523static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 524 struct dma_chan **dma_chan, 525 struct dma_async_tx_descriptor **dma_desc) 526{ 527 struct variant_data *variant = host->variant; 528 struct dma_slave_config conf = { 529 .src_addr = host->phybase + MMCIFIFO, 530 .dst_addr = host->phybase + MMCIFIFO, 531 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 532 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 533 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 534 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 535 .device_fc = false, 536 }; 537 struct dma_chan *chan; 538 struct dma_device *device; 539 struct dma_async_tx_descriptor *desc; 540 enum dma_data_direction buffer_dirn; 541 int nr_sg; 542 543 if (data->flags & MMC_DATA_READ) { 544 conf.direction = DMA_DEV_TO_MEM; 545 buffer_dirn = DMA_FROM_DEVICE; 546 chan = host->dma_rx_channel; 547 } else { 548 conf.direction = DMA_MEM_TO_DEV; 549 buffer_dirn = DMA_TO_DEVICE; 550 chan = host->dma_tx_channel; 551 } 552 553 /* If there's no DMA channel, fall back to PIO */ 554 if (!chan) 555 return -EINVAL; 556 557 /* If less than or equal to the fifo size, don't bother with DMA */ 558 if (data->blksz * data->blocks <= variant->fifosize) 559 return -EINVAL; 560 561 device = chan->device; 562 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 563 if (nr_sg == 0) 564 return -EINVAL; 565 566 dmaengine_slave_config(chan, &conf); 567 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 568 conf.direction, DMA_CTRL_ACK); 569 if (!desc) 570 goto unmap_exit; 571 572 *dma_chan = chan; 573 *dma_desc = desc; 574 575 return 0; 576 577 unmap_exit: 578 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 579 return -ENOMEM; 580} 581 582static inline int mmci_dma_prep_data(struct mmci_host *host, 583 struct mmc_data *data) 584{ 585 /* Check if next job is already prepared. */ 586 if (host->dma_current && host->dma_desc_current) 587 return 0; 588 589 /* No job were prepared thus do it now. */ 590 return __mmci_dma_prep_data(host, data, &host->dma_current, 591 &host->dma_desc_current); 592} 593 594static inline int mmci_dma_prep_next(struct mmci_host *host, 595 struct mmc_data *data) 596{ 597 struct mmci_host_next *nd = &host->next_data; 598 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 599} 600 601static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 602{ 603 int ret; 604 struct mmc_data *data = host->data; 605 606 ret = mmci_dma_prep_data(host, host->data); 607 if (ret) 608 return ret; 609 610 /* Okay, go for it. */ 611 dev_vdbg(mmc_dev(host->mmc), 612 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 613 data->sg_len, data->blksz, data->blocks, data->flags); 614 dmaengine_submit(host->dma_desc_current); 615 dma_async_issue_pending(host->dma_current); 616 617 datactrl |= MCI_DPSM_DMAENABLE; 618 619 /* Trigger the DMA transfer */ 620 mmci_write_datactrlreg(host, datactrl); 621 622 /* 623 * Let the MMCI say when the data is ended and it's time 624 * to fire next DMA request. When that happens, MMCI will 625 * call mmci_data_end() 626 */ 627 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 628 host->base + MMCIMASK0); 629 return 0; 630} 631 632static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 633{ 634 struct mmci_host_next *next = &host->next_data; 635 636 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 637 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 638 639 host->dma_desc_current = next->dma_desc; 640 host->dma_current = next->dma_chan; 641 next->dma_desc = NULL; 642 next->dma_chan = NULL; 643} 644 645static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 646 bool is_first_req) 647{ 648 struct mmci_host *host = mmc_priv(mmc); 649 struct mmc_data *data = mrq->data; 650 struct mmci_host_next *nd = &host->next_data; 651 652 if (!data) 653 return; 654 655 BUG_ON(data->host_cookie); 656 657 if (mmci_validate_data(host, data)) 658 return; 659 660 if (!mmci_dma_prep_next(host, data)) 661 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 662} 663 664static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 665 int err) 666{ 667 struct mmci_host *host = mmc_priv(mmc); 668 struct mmc_data *data = mrq->data; 669 670 if (!data || !data->host_cookie) 671 return; 672 673 mmci_dma_unmap(host, data); 674 675 if (err) { 676 struct mmci_host_next *next = &host->next_data; 677 struct dma_chan *chan; 678 if (data->flags & MMC_DATA_READ) 679 chan = host->dma_rx_channel; 680 else 681 chan = host->dma_tx_channel; 682 dmaengine_terminate_all(chan); 683 684 next->dma_desc = NULL; 685 next->dma_chan = NULL; 686 } 687} 688 689#else 690/* Blank functions if the DMA engine is not available */ 691static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 692{ 693} 694static inline void mmci_dma_setup(struct mmci_host *host) 695{ 696} 697 698static inline void mmci_dma_release(struct mmci_host *host) 699{ 700} 701 702static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 703{ 704} 705 706static inline void mmci_dma_finalize(struct mmci_host *host, 707 struct mmc_data *data) 708{ 709} 710 711static inline void mmci_dma_data_error(struct mmci_host *host) 712{ 713} 714 715static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 716{ 717 return -ENOSYS; 718} 719 720#define mmci_pre_request NULL 721#define mmci_post_request NULL 722 723#endif 724 725static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 726{ 727 struct variant_data *variant = host->variant; 728 unsigned int datactrl, timeout, irqmask; 729 unsigned long long clks; 730 void __iomem *base; 731 int blksz_bits; 732 733 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 734 data->blksz, data->blocks, data->flags); 735 736 host->data = data; 737 host->size = data->blksz * data->blocks; 738 data->bytes_xfered = 0; 739 740 clks = (unsigned long long)data->timeout_ns * host->cclk; 741 do_div(clks, 1000000000UL); 742 743 timeout = data->timeout_clks + (unsigned int)clks; 744 745 base = host->base; 746 writel(timeout, base + MMCIDATATIMER); 747 writel(host->size, base + MMCIDATALENGTH); 748 749 blksz_bits = ffs(data->blksz) - 1; 750 BUG_ON(1 << blksz_bits != data->blksz); 751 752 if (variant->blksz_datactrl16) 753 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 754 else 755 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 756 757 if (data->flags & MMC_DATA_READ) 758 datactrl |= MCI_DPSM_DIRECTION; 759 760 /* The ST Micro variants has a special bit to enable SDIO */ 761 if (variant->sdio && host->mmc->card) 762 if (mmc_card_sdio(host->mmc->card)) { 763 /* 764 * The ST Micro variants has a special bit 765 * to enable SDIO. 766 */ 767 u32 clk; 768 769 datactrl |= MCI_ST_DPSM_SDIOEN; 770 771 /* 772 * The ST Micro variant for SDIO small write transfers 773 * needs to have clock H/W flow control disabled, 774 * otherwise the transfer will not start. The threshold 775 * depends on the rate of MCLK. 776 */ 777 if (data->flags & MMC_DATA_WRITE && 778 (host->size < 8 || 779 (host->size <= 8 && host->mclk > 50000000))) 780 clk = host->clk_reg & ~variant->clkreg_enable; 781 else 782 clk = host->clk_reg | variant->clkreg_enable; 783 784 mmci_write_clkreg(host, clk); 785 } 786 787 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 788 datactrl |= MCI_ST_DPSM_DDRMODE; 789 790 /* 791 * Attempt to use DMA operation mode, if this 792 * should fail, fall back to PIO mode 793 */ 794 if (!mmci_dma_start_data(host, datactrl)) 795 return; 796 797 /* IRQ mode, map the SG list for CPU reading/writing */ 798 mmci_init_sg(host, data); 799 800 if (data->flags & MMC_DATA_READ) { 801 irqmask = MCI_RXFIFOHALFFULLMASK; 802 803 /* 804 * If we have less than the fifo 'half-full' threshold to 805 * transfer, trigger a PIO interrupt as soon as any data 806 * is available. 807 */ 808 if (host->size < variant->fifohalfsize) 809 irqmask |= MCI_RXDATAAVLBLMASK; 810 } else { 811 /* 812 * We don't actually need to include "FIFO empty" here 813 * since its implicit in "FIFO half empty". 814 */ 815 irqmask = MCI_TXFIFOHALFEMPTYMASK; 816 } 817 818 mmci_write_datactrlreg(host, datactrl); 819 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 820 mmci_set_mask1(host, irqmask); 821} 822 823static void 824mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 825{ 826 void __iomem *base = host->base; 827 828 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 829 cmd->opcode, cmd->arg, cmd->flags); 830 831 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 832 writel(0, base + MMCICOMMAND); 833 udelay(1); 834 } 835 836 c |= cmd->opcode | MCI_CPSM_ENABLE; 837 if (cmd->flags & MMC_RSP_PRESENT) { 838 if (cmd->flags & MMC_RSP_136) 839 c |= MCI_CPSM_LONGRSP; 840 c |= MCI_CPSM_RESPONSE; 841 } 842 if (/*interrupt*/0) 843 c |= MCI_CPSM_INTERRUPT; 844 845 host->cmd = cmd; 846 847 writel(cmd->arg, base + MMCIARGUMENT); 848 writel(c, base + MMCICOMMAND); 849} 850 851static void 852mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 853 unsigned int status) 854{ 855 /* First check for errors */ 856 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 857 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 858 u32 remain, success; 859 860 /* Terminate the DMA transfer */ 861 if (dma_inprogress(host)) { 862 mmci_dma_data_error(host); 863 mmci_dma_unmap(host, data); 864 } 865 866 /* 867 * Calculate how far we are into the transfer. Note that 868 * the data counter gives the number of bytes transferred 869 * on the MMC bus, not on the host side. On reads, this 870 * can be as much as a FIFO-worth of data ahead. This 871 * matters for FIFO overruns only. 872 */ 873 remain = readl(host->base + MMCIDATACNT); 874 success = data->blksz * data->blocks - remain; 875 876 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 877 status, success); 878 if (status & MCI_DATACRCFAIL) { 879 /* Last block was not successful */ 880 success -= 1; 881 data->error = -EILSEQ; 882 } else if (status & MCI_DATATIMEOUT) { 883 data->error = -ETIMEDOUT; 884 } else if (status & MCI_STARTBITERR) { 885 data->error = -ECOMM; 886 } else if (status & MCI_TXUNDERRUN) { 887 data->error = -EIO; 888 } else if (status & MCI_RXOVERRUN) { 889 if (success > host->variant->fifosize) 890 success -= host->variant->fifosize; 891 else 892 success = 0; 893 data->error = -EIO; 894 } 895 data->bytes_xfered = round_down(success, data->blksz); 896 } 897 898 if (status & MCI_DATABLOCKEND) 899 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 900 901 if (status & MCI_DATAEND || data->error) { 902 if (dma_inprogress(host)) 903 mmci_dma_finalize(host, data); 904 mmci_stop_data(host); 905 906 if (!data->error) 907 /* The error clause is handled above, success! */ 908 data->bytes_xfered = data->blksz * data->blocks; 909 910 if (!data->stop || host->mrq->sbc) { 911 mmci_request_end(host, data->mrq); 912 } else { 913 mmci_start_command(host, data->stop, 0); 914 } 915 } 916} 917 918static void 919mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 920 unsigned int status) 921{ 922 void __iomem *base = host->base; 923 bool sbc = (cmd == host->mrq->sbc); 924 bool busy_resp = host->variant->busy_detect && 925 (cmd->flags & MMC_RSP_BUSY); 926 927 /* Check if we need to wait for busy completion. */ 928 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 929 return; 930 931 /* Enable busy completion if needed and supported. */ 932 if (!host->busy_status && busy_resp && 933 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 934 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 935 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 936 base + MMCIMASK0); 937 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 938 return; 939 } 940 941 /* At busy completion, mask the IRQ and complete the request. */ 942 if (host->busy_status) { 943 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 944 base + MMCIMASK0); 945 host->busy_status = 0; 946 } 947 948 host->cmd = NULL; 949 950 if (status & MCI_CMDTIMEOUT) { 951 cmd->error = -ETIMEDOUT; 952 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 953 cmd->error = -EILSEQ; 954 } else { 955 cmd->resp[0] = readl(base + MMCIRESPONSE0); 956 cmd->resp[1] = readl(base + MMCIRESPONSE1); 957 cmd->resp[2] = readl(base + MMCIRESPONSE2); 958 cmd->resp[3] = readl(base + MMCIRESPONSE3); 959 } 960 961 if ((!sbc && !cmd->data) || cmd->error) { 962 if (host->data) { 963 /* Terminate the DMA transfer */ 964 if (dma_inprogress(host)) { 965 mmci_dma_data_error(host); 966 mmci_dma_unmap(host, host->data); 967 } 968 mmci_stop_data(host); 969 } 970 mmci_request_end(host, host->mrq); 971 } else if (sbc) { 972 mmci_start_command(host, host->mrq->cmd, 0); 973 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 974 mmci_start_data(host, cmd->data); 975 } 976} 977 978static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 979{ 980 void __iomem *base = host->base; 981 char *ptr = buffer; 982 u32 status; 983 int host_remain = host->size; 984 985 do { 986 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 987 988 if (count > remain) 989 count = remain; 990 991 if (count <= 0) 992 break; 993 994 /* 995 * SDIO especially may want to send something that is 996 * not divisible by 4 (as opposed to card sectors 997 * etc). Therefore make sure to always read the last bytes 998 * while only doing full 32-bit reads towards the FIFO. 999 */ 1000 if (unlikely(count & 0x3)) { 1001 if (count < 4) { 1002 unsigned char buf[4]; 1003 ioread32_rep(base + MMCIFIFO, buf, 1); 1004 memcpy(ptr, buf, count); 1005 } else { 1006 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1007 count &= ~0x3; 1008 } 1009 } else { 1010 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1011 } 1012 1013 ptr += count; 1014 remain -= count; 1015 host_remain -= count; 1016 1017 if (remain == 0) 1018 break; 1019 1020 status = readl(base + MMCISTATUS); 1021 } while (status & MCI_RXDATAAVLBL); 1022 1023 return ptr - buffer; 1024} 1025 1026static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1027{ 1028 struct variant_data *variant = host->variant; 1029 void __iomem *base = host->base; 1030 char *ptr = buffer; 1031 1032 do { 1033 unsigned int count, maxcnt; 1034 1035 maxcnt = status & MCI_TXFIFOEMPTY ? 1036 variant->fifosize : variant->fifohalfsize; 1037 count = min(remain, maxcnt); 1038 1039 /* 1040 * SDIO especially may want to send something that is 1041 * not divisible by 4 (as opposed to card sectors 1042 * etc), and the FIFO only accept full 32-bit writes. 1043 * So compensate by adding +3 on the count, a single 1044 * byte become a 32bit write, 7 bytes will be two 1045 * 32bit writes etc. 1046 */ 1047 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1048 1049 ptr += count; 1050 remain -= count; 1051 1052 if (remain == 0) 1053 break; 1054 1055 status = readl(base + MMCISTATUS); 1056 } while (status & MCI_TXFIFOHALFEMPTY); 1057 1058 return ptr - buffer; 1059} 1060 1061/* 1062 * PIO data transfer IRQ handler. 1063 */ 1064static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1065{ 1066 struct mmci_host *host = dev_id; 1067 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1068 struct variant_data *variant = host->variant; 1069 void __iomem *base = host->base; 1070 unsigned long flags; 1071 u32 status; 1072 1073 status = readl(base + MMCISTATUS); 1074 1075 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1076 1077 local_irq_save(flags); 1078 1079 do { 1080 unsigned int remain, len; 1081 char *buffer; 1082 1083 /* 1084 * For write, we only need to test the half-empty flag 1085 * here - if the FIFO is completely empty, then by 1086 * definition it is more than half empty. 1087 * 1088 * For read, check for data available. 1089 */ 1090 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1091 break; 1092 1093 if (!sg_miter_next(sg_miter)) 1094 break; 1095 1096 buffer = sg_miter->addr; 1097 remain = sg_miter->length; 1098 1099 len = 0; 1100 if (status & MCI_RXACTIVE) 1101 len = mmci_pio_read(host, buffer, remain); 1102 if (status & MCI_TXACTIVE) 1103 len = mmci_pio_write(host, buffer, remain, status); 1104 1105 sg_miter->consumed = len; 1106 1107 host->size -= len; 1108 remain -= len; 1109 1110 if (remain) 1111 break; 1112 1113 status = readl(base + MMCISTATUS); 1114 } while (1); 1115 1116 sg_miter_stop(sg_miter); 1117 1118 local_irq_restore(flags); 1119 1120 /* 1121 * If we have less than the fifo 'half-full' threshold to transfer, 1122 * trigger a PIO interrupt as soon as any data is available. 1123 */ 1124 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1125 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1126 1127 /* 1128 * If we run out of data, disable the data IRQs; this 1129 * prevents a race where the FIFO becomes empty before 1130 * the chip itself has disabled the data path, and 1131 * stops us racing with our data end IRQ. 1132 */ 1133 if (host->size == 0) { 1134 mmci_set_mask1(host, 0); 1135 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1136 } 1137 1138 return IRQ_HANDLED; 1139} 1140 1141/* 1142 * Handle completion of command and data transfers. 1143 */ 1144static irqreturn_t mmci_irq(int irq, void *dev_id) 1145{ 1146 struct mmci_host *host = dev_id; 1147 u32 status; 1148 int ret = 0; 1149 1150 spin_lock(&host->lock); 1151 1152 do { 1153 struct mmc_command *cmd; 1154 struct mmc_data *data; 1155 1156 status = readl(host->base + MMCISTATUS); 1157 1158 if (host->singleirq) { 1159 if (status & readl(host->base + MMCIMASK1)) 1160 mmci_pio_irq(irq, dev_id); 1161 1162 status &= ~MCI_IRQ1MASK; 1163 } 1164 1165 /* 1166 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1167 * enabled) since the HW seems to be triggering the IRQ on both 1168 * edges while monitoring DAT0 for busy completion. 1169 */ 1170 status &= readl(host->base + MMCIMASK0); 1171 writel(status, host->base + MMCICLEAR); 1172 1173 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1174 1175 cmd = host->cmd; 1176 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 1177 MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1178 mmci_cmd_irq(host, cmd, status); 1179 1180 data = host->data; 1181 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1182 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1183 MCI_DATABLOCKEND) && data) 1184 mmci_data_irq(host, data, status); 1185 1186 /* Don't poll for busy completion in irq context. */ 1187 if (host->busy_status) 1188 status &= ~MCI_ST_CARDBUSY; 1189 1190 ret = 1; 1191 } while (status); 1192 1193 spin_unlock(&host->lock); 1194 1195 return IRQ_RETVAL(ret); 1196} 1197 1198static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1199{ 1200 struct mmci_host *host = mmc_priv(mmc); 1201 unsigned long flags; 1202 1203 WARN_ON(host->mrq != NULL); 1204 1205 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1206 if (mrq->cmd->error) { 1207 mmc_request_done(mmc, mrq); 1208 return; 1209 } 1210 1211 pm_runtime_get_sync(mmc_dev(mmc)); 1212 1213 spin_lock_irqsave(&host->lock, flags); 1214 1215 host->mrq = mrq; 1216 1217 if (mrq->data) 1218 mmci_get_next_data(host, mrq->data); 1219 1220 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1221 mmci_start_data(host, mrq->data); 1222 1223 if (mrq->sbc) 1224 mmci_start_command(host, mrq->sbc, 0); 1225 else 1226 mmci_start_command(host, mrq->cmd, 0); 1227 1228 spin_unlock_irqrestore(&host->lock, flags); 1229} 1230 1231static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1232{ 1233 struct mmci_host *host = mmc_priv(mmc); 1234 struct variant_data *variant = host->variant; 1235 u32 pwr = 0; 1236 unsigned long flags; 1237 int ret; 1238 1239 pm_runtime_get_sync(mmc_dev(mmc)); 1240 1241 if (host->plat->ios_handler && 1242 host->plat->ios_handler(mmc_dev(mmc), ios)) 1243 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1244 1245 switch (ios->power_mode) { 1246 case MMC_POWER_OFF: 1247 if (!IS_ERR(mmc->supply.vmmc)) 1248 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1249 1250 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1251 regulator_disable(mmc->supply.vqmmc); 1252 host->vqmmc_enabled = false; 1253 } 1254 1255 break; 1256 case MMC_POWER_UP: 1257 if (!IS_ERR(mmc->supply.vmmc)) 1258 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1259 1260 /* 1261 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1262 * and instead uses MCI_PWR_ON so apply whatever value is 1263 * configured in the variant data. 1264 */ 1265 pwr |= variant->pwrreg_powerup; 1266 1267 break; 1268 case MMC_POWER_ON: 1269 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1270 ret = regulator_enable(mmc->supply.vqmmc); 1271 if (ret < 0) 1272 dev_err(mmc_dev(mmc), 1273 "failed to enable vqmmc regulator\n"); 1274 else 1275 host->vqmmc_enabled = true; 1276 } 1277 1278 pwr |= MCI_PWR_ON; 1279 break; 1280 } 1281 1282 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1283 /* 1284 * The ST Micro variant has some additional bits 1285 * indicating signal direction for the signals in 1286 * the SD/MMC bus and feedback-clock usage. 1287 */ 1288 pwr |= host->plat->sigdir; 1289 1290 if (ios->bus_width == MMC_BUS_WIDTH_4) 1291 pwr &= ~MCI_ST_DATA74DIREN; 1292 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1293 pwr &= (~MCI_ST_DATA74DIREN & 1294 ~MCI_ST_DATA31DIREN & 1295 ~MCI_ST_DATA2DIREN); 1296 } 1297 1298 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1299 if (host->hw_designer != AMBA_VENDOR_ST) 1300 pwr |= MCI_ROD; 1301 else { 1302 /* 1303 * The ST Micro variant use the ROD bit for something 1304 * else and only has OD (Open Drain). 1305 */ 1306 pwr |= MCI_OD; 1307 } 1308 } 1309 1310 /* 1311 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1312 * gating the clock, the MCI_PWR_ON bit is cleared. 1313 */ 1314 if (!ios->clock && variant->pwrreg_clkgate) 1315 pwr &= ~MCI_PWR_ON; 1316 1317 spin_lock_irqsave(&host->lock, flags); 1318 1319 mmci_set_clkreg(host, ios->clock); 1320 mmci_write_pwrreg(host, pwr); 1321 mmci_reg_delay(host); 1322 1323 spin_unlock_irqrestore(&host->lock, flags); 1324 1325 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1326 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1327} 1328 1329static int mmci_get_ro(struct mmc_host *mmc) 1330{ 1331 struct mmci_host *host = mmc_priv(mmc); 1332 1333 if (host->gpio_wp == -ENOSYS) 1334 return -ENOSYS; 1335 1336 return gpio_get_value_cansleep(host->gpio_wp); 1337} 1338 1339static int mmci_get_cd(struct mmc_host *mmc) 1340{ 1341 struct mmci_host *host = mmc_priv(mmc); 1342 struct mmci_platform_data *plat = host->plat; 1343 unsigned int status; 1344 1345 if (host->gpio_cd == -ENOSYS) { 1346 if (!plat->status) 1347 return 1; /* Assume always present */ 1348 1349 status = plat->status(mmc_dev(host->mmc)); 1350 } else 1351 status = !!gpio_get_value_cansleep(host->gpio_cd) 1352 ^ plat->cd_invert; 1353 1354 /* 1355 * Use positive logic throughout - status is zero for no card, 1356 * non-zero for card inserted. 1357 */ 1358 return status; 1359} 1360 1361static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1362{ 1363 int ret = 0; 1364 1365 if (!IS_ERR(mmc->supply.vqmmc)) { 1366 1367 pm_runtime_get_sync(mmc_dev(mmc)); 1368 1369 switch (ios->signal_voltage) { 1370 case MMC_SIGNAL_VOLTAGE_330: 1371 ret = regulator_set_voltage(mmc->supply.vqmmc, 1372 2700000, 3600000); 1373 break; 1374 case MMC_SIGNAL_VOLTAGE_180: 1375 ret = regulator_set_voltage(mmc->supply.vqmmc, 1376 1700000, 1950000); 1377 break; 1378 case MMC_SIGNAL_VOLTAGE_120: 1379 ret = regulator_set_voltage(mmc->supply.vqmmc, 1380 1100000, 1300000); 1381 break; 1382 } 1383 1384 if (ret) 1385 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1386 1387 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1388 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1389 } 1390 1391 return ret; 1392} 1393 1394static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1395{ 1396 struct mmci_host *host = dev_id; 1397 1398 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1399 1400 return IRQ_HANDLED; 1401} 1402 1403static struct mmc_host_ops mmci_ops = { 1404 .request = mmci_request, 1405 .pre_req = mmci_pre_request, 1406 .post_req = mmci_post_request, 1407 .set_ios = mmci_set_ios, 1408 .get_ro = mmci_get_ro, 1409 .get_cd = mmci_get_cd, 1410 .start_signal_voltage_switch = mmci_sig_volt_switch, 1411}; 1412 1413#ifdef CONFIG_OF 1414static void mmci_dt_populate_generic_pdata(struct device_node *np, 1415 struct mmci_platform_data *pdata) 1416{ 1417 int bus_width = 0; 1418 1419 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1420 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1421 1422 if (of_get_property(np, "cd-inverted", NULL)) 1423 pdata->cd_invert = true; 1424 else 1425 pdata->cd_invert = false; 1426 1427 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1428 if (!pdata->f_max) 1429 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1430 1431 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1432 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1433 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1434 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1435 1436 of_property_read_u32(np, "bus-width", &bus_width); 1437 switch (bus_width) { 1438 case 0 : 1439 /* No bus-width supplied. */ 1440 break; 1441 case 4 : 1442 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1443 break; 1444 case 8 : 1445 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1446 break; 1447 default : 1448 pr_warn("%s: Unsupported bus width\n", np->full_name); 1449 } 1450} 1451#else 1452static void mmci_dt_populate_generic_pdata(struct device_node *np, 1453 struct mmci_platform_data *pdata) 1454{ 1455 return; 1456} 1457#endif 1458 1459static int mmci_probe(struct amba_device *dev, 1460 const struct amba_id *id) 1461{ 1462 struct mmci_platform_data *plat = dev->dev.platform_data; 1463 struct device_node *np = dev->dev.of_node; 1464 struct variant_data *variant = id->data; 1465 struct mmci_host *host; 1466 struct mmc_host *mmc; 1467 int ret; 1468 1469 /* Must have platform data or Device Tree. */ 1470 if (!plat && !np) { 1471 dev_err(&dev->dev, "No plat data or DT found\n"); 1472 return -EINVAL; 1473 } 1474 1475 if (!plat) { 1476 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1477 if (!plat) 1478 return -ENOMEM; 1479 } 1480 1481 if (np) 1482 mmci_dt_populate_generic_pdata(np, plat); 1483 1484 ret = amba_request_regions(dev, DRIVER_NAME); 1485 if (ret) 1486 goto out; 1487 1488 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1489 if (!mmc) { 1490 ret = -ENOMEM; 1491 goto rel_regions; 1492 } 1493 1494 host = mmc_priv(mmc); 1495 host->mmc = mmc; 1496 1497 host->gpio_wp = -ENOSYS; 1498 host->gpio_cd = -ENOSYS; 1499 host->gpio_cd_irq = -1; 1500 1501 host->hw_designer = amba_manf(dev); 1502 host->hw_revision = amba_rev(dev); 1503 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1504 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1505 1506 host->clk = devm_clk_get(&dev->dev, NULL); 1507 if (IS_ERR(host->clk)) { 1508 ret = PTR_ERR(host->clk); 1509 goto host_free; 1510 } 1511 1512 ret = clk_prepare_enable(host->clk); 1513 if (ret) 1514 goto host_free; 1515 1516 host->plat = plat; 1517 host->variant = variant; 1518 host->mclk = clk_get_rate(host->clk); 1519 /* 1520 * According to the spec, mclk is max 100 MHz, 1521 * so we try to adjust the clock down to this, 1522 * (if possible). 1523 */ 1524 if (host->mclk > 100000000) { 1525 ret = clk_set_rate(host->clk, 100000000); 1526 if (ret < 0) 1527 goto clk_disable; 1528 host->mclk = clk_get_rate(host->clk); 1529 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1530 host->mclk); 1531 } 1532 host->phybase = dev->res.start; 1533 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1534 if (!host->base) { 1535 ret = -ENOMEM; 1536 goto clk_disable; 1537 } 1538 1539 /* 1540 * The ARM and ST versions of the block have slightly different 1541 * clock divider equations which means that the minimum divider 1542 * differs too. 1543 */ 1544 if (variant->st_clkdiv) 1545 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1546 else 1547 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1548 /* 1549 * If the platform data supplies a maximum operating 1550 * frequency, this takes precedence. Else, we fall back 1551 * to using the module parameter, which has a (low) 1552 * default value in case it is not specified. Either 1553 * value must not exceed the clock rate into the block, 1554 * of course. 1555 */ 1556 if (plat->f_max) 1557 mmc->f_max = min(host->mclk, plat->f_max); 1558 else 1559 mmc->f_max = min(host->mclk, fmax); 1560 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1561 1562 /* Get regulators and the supported OCR mask */ 1563 mmc_regulator_get_supply(mmc); 1564 if (!mmc->ocr_avail) 1565 mmc->ocr_avail = plat->ocr_mask; 1566 else if (plat->ocr_mask) 1567 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1568 1569 mmc->caps = plat->capabilities; 1570 mmc->caps2 = plat->capabilities2; 1571 1572 if (variant->busy_detect) { 1573 mmci_ops.card_busy = mmci_card_busy; 1574 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1575 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1576 mmc->max_busy_timeout = 0; 1577 } 1578 1579 mmc->ops = &mmci_ops; 1580 1581 /* We support these PM capabilities. */ 1582 mmc->pm_caps = MMC_PM_KEEP_POWER; 1583 1584 /* 1585 * We can do SGIO 1586 */ 1587 mmc->max_segs = NR_SG; 1588 1589 /* 1590 * Since only a certain number of bits are valid in the data length 1591 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1592 * single request. 1593 */ 1594 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1595 1596 /* 1597 * Set the maximum segment size. Since we aren't doing DMA 1598 * (yet) we are only limited by the data length register. 1599 */ 1600 mmc->max_seg_size = mmc->max_req_size; 1601 1602 /* 1603 * Block size can be up to 2048 bytes, but must be a power of two. 1604 */ 1605 mmc->max_blk_size = 1 << 11; 1606 1607 /* 1608 * Limit the number of blocks transferred so that we don't overflow 1609 * the maximum request size. 1610 */ 1611 mmc->max_blk_count = mmc->max_req_size >> 11; 1612 1613 spin_lock_init(&host->lock); 1614 1615 writel(0, host->base + MMCIMASK0); 1616 writel(0, host->base + MMCIMASK1); 1617 writel(0xfff, host->base + MMCICLEAR); 1618 1619 if (plat->gpio_cd == -EPROBE_DEFER) { 1620 ret = -EPROBE_DEFER; 1621 goto err_gpio_cd; 1622 } 1623 if (gpio_is_valid(plat->gpio_cd)) { 1624 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1625 if (ret == 0) 1626 ret = gpio_direction_input(plat->gpio_cd); 1627 if (ret == 0) 1628 host->gpio_cd = plat->gpio_cd; 1629 else if (ret != -ENOSYS) 1630 goto err_gpio_cd; 1631 1632 /* 1633 * A gpio pin that will detect cards when inserted and removed 1634 * will most likely want to trigger on the edges if it is 1635 * 0 when ejected and 1 when inserted (or mutatis mutandis 1636 * for the inverted case) so we request triggers on both 1637 * edges. 1638 */ 1639 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1640 mmci_cd_irq, 1641 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1642 DRIVER_NAME " (cd)", host); 1643 if (ret >= 0) 1644 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1645 } 1646 if (plat->gpio_wp == -EPROBE_DEFER) { 1647 ret = -EPROBE_DEFER; 1648 goto err_gpio_wp; 1649 } 1650 if (gpio_is_valid(plat->gpio_wp)) { 1651 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1652 if (ret == 0) 1653 ret = gpio_direction_input(plat->gpio_wp); 1654 if (ret == 0) 1655 host->gpio_wp = plat->gpio_wp; 1656 else if (ret != -ENOSYS) 1657 goto err_gpio_wp; 1658 } 1659 1660 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1661 && host->gpio_cd_irq < 0) 1662 mmc->caps |= MMC_CAP_NEEDS_POLL; 1663 1664 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1665 if (ret) 1666 goto unmap; 1667 1668 if (!dev->irq[1]) 1669 host->singleirq = true; 1670 else { 1671 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1672 DRIVER_NAME " (pio)", host); 1673 if (ret) 1674 goto irq0_free; 1675 } 1676 1677 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1678 1679 amba_set_drvdata(dev, mmc); 1680 1681 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1682 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1683 amba_rev(dev), (unsigned long long)dev->res.start, 1684 dev->irq[0], dev->irq[1]); 1685 1686 mmci_dma_setup(host); 1687 1688 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1689 pm_runtime_use_autosuspend(&dev->dev); 1690 pm_runtime_put(&dev->dev); 1691 1692 mmc_add_host(mmc); 1693 1694 return 0; 1695 1696 irq0_free: 1697 free_irq(dev->irq[0], host); 1698 unmap: 1699 if (host->gpio_wp != -ENOSYS) 1700 gpio_free(host->gpio_wp); 1701 err_gpio_wp: 1702 if (host->gpio_cd_irq >= 0) 1703 free_irq(host->gpio_cd_irq, host); 1704 if (host->gpio_cd != -ENOSYS) 1705 gpio_free(host->gpio_cd); 1706 err_gpio_cd: 1707 iounmap(host->base); 1708 clk_disable: 1709 clk_disable_unprepare(host->clk); 1710 host_free: 1711 mmc_free_host(mmc); 1712 rel_regions: 1713 amba_release_regions(dev); 1714 out: 1715 return ret; 1716} 1717 1718static int mmci_remove(struct amba_device *dev) 1719{ 1720 struct mmc_host *mmc = amba_get_drvdata(dev); 1721 1722 if (mmc) { 1723 struct mmci_host *host = mmc_priv(mmc); 1724 1725 /* 1726 * Undo pm_runtime_put() in probe. We use the _sync 1727 * version here so that we can access the primecell. 1728 */ 1729 pm_runtime_get_sync(&dev->dev); 1730 1731 mmc_remove_host(mmc); 1732 1733 writel(0, host->base + MMCIMASK0); 1734 writel(0, host->base + MMCIMASK1); 1735 1736 writel(0, host->base + MMCICOMMAND); 1737 writel(0, host->base + MMCIDATACTRL); 1738 1739 mmci_dma_release(host); 1740 free_irq(dev->irq[0], host); 1741 if (!host->singleirq) 1742 free_irq(dev->irq[1], host); 1743 1744 if (host->gpio_wp != -ENOSYS) 1745 gpio_free(host->gpio_wp); 1746 if (host->gpio_cd_irq >= 0) 1747 free_irq(host->gpio_cd_irq, host); 1748 if (host->gpio_cd != -ENOSYS) 1749 gpio_free(host->gpio_cd); 1750 1751 iounmap(host->base); 1752 clk_disable_unprepare(host->clk); 1753 1754 mmc_free_host(mmc); 1755 1756 amba_release_regions(dev); 1757 } 1758 1759 return 0; 1760} 1761 1762#ifdef CONFIG_SUSPEND 1763static int mmci_suspend(struct device *dev) 1764{ 1765 struct amba_device *adev = to_amba_device(dev); 1766 struct mmc_host *mmc = amba_get_drvdata(adev); 1767 1768 if (mmc) { 1769 struct mmci_host *host = mmc_priv(mmc); 1770 pm_runtime_get_sync(dev); 1771 writel(0, host->base + MMCIMASK0); 1772 } 1773 1774 return 0; 1775} 1776 1777static int mmci_resume(struct device *dev) 1778{ 1779 struct amba_device *adev = to_amba_device(dev); 1780 struct mmc_host *mmc = amba_get_drvdata(adev); 1781 1782 if (mmc) { 1783 struct mmci_host *host = mmc_priv(mmc); 1784 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1785 pm_runtime_put(dev); 1786 } 1787 1788 return 0; 1789} 1790#endif 1791 1792#ifdef CONFIG_PM 1793static void mmci_save(struct mmci_host *host) 1794{ 1795 unsigned long flags; 1796 1797 spin_lock_irqsave(&host->lock, flags); 1798 1799 writel(0, host->base + MMCIMASK0); 1800 if (host->variant->pwrreg_nopower) { 1801 writel(0, host->base + MMCIDATACTRL); 1802 writel(0, host->base + MMCIPOWER); 1803 writel(0, host->base + MMCICLOCK); 1804 } 1805 mmci_reg_delay(host); 1806 1807 spin_unlock_irqrestore(&host->lock, flags); 1808} 1809 1810static void mmci_restore(struct mmci_host *host) 1811{ 1812 unsigned long flags; 1813 1814 spin_lock_irqsave(&host->lock, flags); 1815 1816 if (host->variant->pwrreg_nopower) { 1817 writel(host->clk_reg, host->base + MMCICLOCK); 1818 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1819 writel(host->pwr_reg, host->base + MMCIPOWER); 1820 } 1821 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1822 mmci_reg_delay(host); 1823 1824 spin_unlock_irqrestore(&host->lock, flags); 1825} 1826 1827static int mmci_runtime_suspend(struct device *dev) 1828{ 1829 struct amba_device *adev = to_amba_device(dev); 1830 struct mmc_host *mmc = amba_get_drvdata(adev); 1831 1832 if (mmc) { 1833 struct mmci_host *host = mmc_priv(mmc); 1834 pinctrl_pm_select_sleep_state(dev); 1835 mmci_save(host); 1836 clk_disable_unprepare(host->clk); 1837 } 1838 1839 return 0; 1840} 1841 1842static int mmci_runtime_resume(struct device *dev) 1843{ 1844 struct amba_device *adev = to_amba_device(dev); 1845 struct mmc_host *mmc = amba_get_drvdata(adev); 1846 1847 if (mmc) { 1848 struct mmci_host *host = mmc_priv(mmc); 1849 clk_prepare_enable(host->clk); 1850 mmci_restore(host); 1851 pinctrl_pm_select_default_state(dev); 1852 } 1853 1854 return 0; 1855} 1856#endif 1857 1858static const struct dev_pm_ops mmci_dev_pm_ops = { 1859 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1860 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1861}; 1862 1863static struct amba_id mmci_ids[] = { 1864 { 1865 .id = 0x00041180, 1866 .mask = 0xff0fffff, 1867 .data = &variant_arm, 1868 }, 1869 { 1870 .id = 0x01041180, 1871 .mask = 0xff0fffff, 1872 .data = &variant_arm_extended_fifo, 1873 }, 1874 { 1875 .id = 0x02041180, 1876 .mask = 0xff0fffff, 1877 .data = &variant_arm_extended_fifo_hwfc, 1878 }, 1879 { 1880 .id = 0x00041181, 1881 .mask = 0x000fffff, 1882 .data = &variant_arm, 1883 }, 1884 /* ST Micro variants */ 1885 { 1886 .id = 0x00180180, 1887 .mask = 0x00ffffff, 1888 .data = &variant_u300, 1889 }, 1890 { 1891 .id = 0x10180180, 1892 .mask = 0xf0ffffff, 1893 .data = &variant_nomadik, 1894 }, 1895 { 1896 .id = 0x00280180, 1897 .mask = 0x00ffffff, 1898 .data = &variant_u300, 1899 }, 1900 { 1901 .id = 0x00480180, 1902 .mask = 0xf0ffffff, 1903 .data = &variant_ux500, 1904 }, 1905 { 1906 .id = 0x10480180, 1907 .mask = 0xf0ffffff, 1908 .data = &variant_ux500v2, 1909 }, 1910 { 0, 0 }, 1911}; 1912 1913MODULE_DEVICE_TABLE(amba, mmci_ids); 1914 1915static struct amba_driver mmci_driver = { 1916 .drv = { 1917 .name = DRIVER_NAME, 1918 .pm = &mmci_dev_pm_ops, 1919 }, 1920 .probe = mmci_probe, 1921 .remove = mmci_remove, 1922 .id_table = mmci_ids, 1923}; 1924 1925module_amba_driver(mmci_driver); 1926 1927module_param(fmax, uint, 0444); 1928 1929MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1930MODULE_LICENSE("GPL"); 1931