mmci.c revision 808d97ccbe8e8251b1435e86c762965fd7e8a75e
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson AB. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/delay.h> 18#include <linux/err.h> 19#include <linux/highmem.h> 20#include <linux/log2.h> 21#include <linux/mmc/host.h> 22#include <linux/amba/bus.h> 23#include <linux/clk.h> 24#include <linux/scatterlist.h> 25#include <linux/gpio.h> 26#include <linux/amba/mmci.h> 27#include <linux/regulator/consumer.h> 28 29#include <asm/cacheflush.h> 30#include <asm/div64.h> 31#include <asm/io.h> 32#include <asm/sizes.h> 33 34#include "mmci.h" 35 36#define DRIVER_NAME "mmci-pl18x" 37 38static unsigned int fmax = 515633; 39 40/* 41 * This must be called with host->lock held 42 */ 43static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 44{ 45 u32 clk = 0; 46 47 if (desired) { 48 if (desired >= host->mclk) { 49 clk = MCI_CLK_BYPASS; 50 host->cclk = host->mclk; 51 } else { 52 clk = host->mclk / (2 * desired) - 1; 53 if (clk >= 256) 54 clk = 255; 55 host->cclk = host->mclk / (2 * (clk + 1)); 56 } 57 if (host->hw_designer == AMBA_VENDOR_ST) 58 clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ 59 clk |= MCI_CLK_ENABLE; 60 /* This hasn't proven to be worthwhile */ 61 /* clk |= MCI_CLK_PWRSAVE; */ 62 } 63 64 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 65 clk |= MCI_4BIT_BUS; 66 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 67 clk |= MCI_ST_8BIT_BUS; 68 69 writel(clk, host->base + MMCICLOCK); 70} 71 72static void 73mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 74{ 75 writel(0, host->base + MMCICOMMAND); 76 77 BUG_ON(host->data); 78 79 host->mrq = NULL; 80 host->cmd = NULL; 81 82 if (mrq->data) 83 mrq->data->bytes_xfered = host->data_xfered; 84 85 /* 86 * Need to drop the host lock here; mmc_request_done may call 87 * back into the driver... 88 */ 89 spin_unlock(&host->lock); 90 mmc_request_done(host->mmc, mrq); 91 spin_lock(&host->lock); 92} 93 94static void mmci_stop_data(struct mmci_host *host) 95{ 96 writel(0, host->base + MMCIDATACTRL); 97 writel(0, host->base + MMCIMASK1); 98 host->data = NULL; 99} 100 101static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 102{ 103 unsigned int datactrl, timeout, irqmask; 104 unsigned long long clks; 105 void __iomem *base; 106 int blksz_bits; 107 108 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 109 data->blksz, data->blocks, data->flags); 110 111 host->data = data; 112 host->size = data->blksz; 113 host->data_xfered = 0; 114 115 mmci_init_sg(host, data); 116 117 clks = (unsigned long long)data->timeout_ns * host->cclk; 118 do_div(clks, 1000000000UL); 119 120 timeout = data->timeout_clks + (unsigned int)clks; 121 122 base = host->base; 123 writel(timeout, base + MMCIDATATIMER); 124 writel(host->size, base + MMCIDATALENGTH); 125 126 blksz_bits = ffs(data->blksz) - 1; 127 BUG_ON(1 << blksz_bits != data->blksz); 128 129 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 130 if (data->flags & MMC_DATA_READ) { 131 datactrl |= MCI_DPSM_DIRECTION; 132 irqmask = MCI_RXFIFOHALFFULLMASK; 133 134 /* 135 * If we have less than a FIFOSIZE of bytes to transfer, 136 * trigger a PIO interrupt as soon as any data is available. 137 */ 138 if (host->size < MCI_FIFOSIZE) 139 irqmask |= MCI_RXDATAAVLBLMASK; 140 } else { 141 /* 142 * We don't actually need to include "FIFO empty" here 143 * since its implicit in "FIFO half empty". 144 */ 145 irqmask = MCI_TXFIFOHALFEMPTYMASK; 146 } 147 148 writel(datactrl, base + MMCIDATACTRL); 149 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 150 writel(irqmask, base + MMCIMASK1); 151} 152 153static void 154mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 155{ 156 void __iomem *base = host->base; 157 158 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 159 cmd->opcode, cmd->arg, cmd->flags); 160 161 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 162 writel(0, base + MMCICOMMAND); 163 udelay(1); 164 } 165 166 c |= cmd->opcode | MCI_CPSM_ENABLE; 167 if (cmd->flags & MMC_RSP_PRESENT) { 168 if (cmd->flags & MMC_RSP_136) 169 c |= MCI_CPSM_LONGRSP; 170 c |= MCI_CPSM_RESPONSE; 171 } 172 if (/*interrupt*/0) 173 c |= MCI_CPSM_INTERRUPT; 174 175 host->cmd = cmd; 176 177 writel(cmd->arg, base + MMCIARGUMENT); 178 writel(c, base + MMCICOMMAND); 179} 180 181static void 182mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 183 unsigned int status) 184{ 185 if (status & MCI_DATABLOCKEND) { 186 host->data_xfered += data->blksz; 187#ifdef CONFIG_ARCH_U300 188 /* 189 * On the U300 some signal or other is 190 * badly routed so that a data write does 191 * not properly terminate with a MCI_DATAEND 192 * status flag. This quirk will make writes 193 * work again. 194 */ 195 if (data->flags & MMC_DATA_WRITE) 196 status |= MCI_DATAEND; 197#endif 198 } 199 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 200 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); 201 if (status & MCI_DATACRCFAIL) 202 data->error = -EILSEQ; 203 else if (status & MCI_DATATIMEOUT) 204 data->error = -ETIMEDOUT; 205 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) 206 data->error = -EIO; 207 status |= MCI_DATAEND; 208 209 /* 210 * We hit an error condition. Ensure that any data 211 * partially written to a page is properly coherent. 212 */ 213 if (host->sg_len && data->flags & MMC_DATA_READ) 214 flush_dcache_page(sg_page(host->sg_ptr)); 215 } 216 if (status & MCI_DATAEND) { 217 mmci_stop_data(host); 218 219 if (!data->stop) { 220 mmci_request_end(host, data->mrq); 221 } else { 222 mmci_start_command(host, data->stop, 0); 223 } 224 } 225} 226 227static void 228mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 229 unsigned int status) 230{ 231 void __iomem *base = host->base; 232 233 host->cmd = NULL; 234 235 cmd->resp[0] = readl(base + MMCIRESPONSE0); 236 cmd->resp[1] = readl(base + MMCIRESPONSE1); 237 cmd->resp[2] = readl(base + MMCIRESPONSE2); 238 cmd->resp[3] = readl(base + MMCIRESPONSE3); 239 240 if (status & MCI_CMDTIMEOUT) { 241 cmd->error = -ETIMEDOUT; 242 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 243 cmd->error = -EILSEQ; 244 } 245 246 if (!cmd->data || cmd->error) { 247 if (host->data) 248 mmci_stop_data(host); 249 mmci_request_end(host, cmd->mrq); 250 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 251 mmci_start_data(host, cmd->data); 252 } 253} 254 255static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 256{ 257 void __iomem *base = host->base; 258 char *ptr = buffer; 259 u32 status; 260 int host_remain = host->size; 261 262 do { 263 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 264 265 if (count > remain) 266 count = remain; 267 268 if (count <= 0) 269 break; 270 271 readsl(base + MMCIFIFO, ptr, count >> 2); 272 273 ptr += count; 274 remain -= count; 275 host_remain -= count; 276 277 if (remain == 0) 278 break; 279 280 status = readl(base + MMCISTATUS); 281 } while (status & MCI_RXDATAAVLBL); 282 283 return ptr - buffer; 284} 285 286static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 287{ 288 void __iomem *base = host->base; 289 char *ptr = buffer; 290 291 do { 292 unsigned int count, maxcnt; 293 294 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; 295 count = min(remain, maxcnt); 296 297 writesl(base + MMCIFIFO, ptr, count >> 2); 298 299 ptr += count; 300 remain -= count; 301 302 if (remain == 0) 303 break; 304 305 status = readl(base + MMCISTATUS); 306 } while (status & MCI_TXFIFOHALFEMPTY); 307 308 return ptr - buffer; 309} 310 311/* 312 * PIO data transfer IRQ handler. 313 */ 314static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 315{ 316 struct mmci_host *host = dev_id; 317 void __iomem *base = host->base; 318 u32 status; 319 320 status = readl(base + MMCISTATUS); 321 322 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 323 324 do { 325 unsigned long flags; 326 unsigned int remain, len; 327 char *buffer; 328 329 /* 330 * For write, we only need to test the half-empty flag 331 * here - if the FIFO is completely empty, then by 332 * definition it is more than half empty. 333 * 334 * For read, check for data available. 335 */ 336 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 337 break; 338 339 /* 340 * Map the current scatter buffer. 341 */ 342 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off; 343 remain = host->sg_ptr->length - host->sg_off; 344 345 len = 0; 346 if (status & MCI_RXACTIVE) 347 len = mmci_pio_read(host, buffer, remain); 348 if (status & MCI_TXACTIVE) 349 len = mmci_pio_write(host, buffer, remain, status); 350 351 /* 352 * Unmap the buffer. 353 */ 354 mmci_kunmap_atomic(host, buffer, &flags); 355 356 host->sg_off += len; 357 host->size -= len; 358 remain -= len; 359 360 if (remain) 361 break; 362 363 /* 364 * If we were reading, and we have completed this 365 * page, ensure that the data cache is coherent. 366 */ 367 if (status & MCI_RXACTIVE) 368 flush_dcache_page(sg_page(host->sg_ptr)); 369 370 if (!mmci_next_sg(host)) 371 break; 372 373 status = readl(base + MMCISTATUS); 374 } while (1); 375 376 /* 377 * If we're nearing the end of the read, switch to 378 * "any data available" mode. 379 */ 380 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) 381 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); 382 383 /* 384 * If we run out of data, disable the data IRQs; this 385 * prevents a race where the FIFO becomes empty before 386 * the chip itself has disabled the data path, and 387 * stops us racing with our data end IRQ. 388 */ 389 if (host->size == 0) { 390 writel(0, base + MMCIMASK1); 391 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 392 } 393 394 return IRQ_HANDLED; 395} 396 397/* 398 * Handle completion of command and data transfers. 399 */ 400static irqreturn_t mmci_irq(int irq, void *dev_id) 401{ 402 struct mmci_host *host = dev_id; 403 u32 status; 404 int ret = 0; 405 406 spin_lock(&host->lock); 407 408 do { 409 struct mmc_command *cmd; 410 struct mmc_data *data; 411 412 status = readl(host->base + MMCISTATUS); 413 status &= readl(host->base + MMCIMASK0); 414 writel(status, host->base + MMCICLEAR); 415 416 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 417 418 data = host->data; 419 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 420 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 421 mmci_data_irq(host, data, status); 422 423 cmd = host->cmd; 424 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 425 mmci_cmd_irq(host, cmd, status); 426 427 ret = 1; 428 } while (status); 429 430 spin_unlock(&host->lock); 431 432 return IRQ_RETVAL(ret); 433} 434 435static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 436{ 437 struct mmci_host *host = mmc_priv(mmc); 438 unsigned long flags; 439 440 WARN_ON(host->mrq != NULL); 441 442 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 443 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 444 mrq->data->blksz); 445 mrq->cmd->error = -EINVAL; 446 mmc_request_done(mmc, mrq); 447 return; 448 } 449 450 spin_lock_irqsave(&host->lock, flags); 451 452 host->mrq = mrq; 453 454 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 455 mmci_start_data(host, mrq->data); 456 457 mmci_start_command(host, mrq->cmd, 0); 458 459 spin_unlock_irqrestore(&host->lock, flags); 460} 461 462static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 463{ 464 struct mmci_host *host = mmc_priv(mmc); 465 u32 pwr = 0; 466 unsigned long flags; 467 468 switch (ios->power_mode) { 469 case MMC_POWER_OFF: 470 if(host->vcc && 471 regulator_is_enabled(host->vcc)) 472 regulator_disable(host->vcc); 473 break; 474 case MMC_POWER_UP: 475#ifdef CONFIG_REGULATOR 476 if (host->vcc) 477 /* This implicitly enables the regulator */ 478 mmc_regulator_set_ocr(host->vcc, ios->vdd); 479#endif 480 /* 481 * The translate_vdd function is not used if you have 482 * an external regulator, or your design is really weird. 483 * Using it would mean sending in power control BOTH using 484 * a regulator AND the 4 MMCIPWR bits. If we don't have 485 * a regulator, we might have some other platform specific 486 * power control behind this translate function. 487 */ 488 if (!host->vcc && host->plat->translate_vdd) 489 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); 490 /* The ST version does not have this, fall through to POWER_ON */ 491 if (host->hw_designer != AMBA_VENDOR_ST) { 492 pwr |= MCI_PWR_UP; 493 break; 494 } 495 case MMC_POWER_ON: 496 pwr |= MCI_PWR_ON; 497 break; 498 } 499 500 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 501 if (host->hw_designer != AMBA_VENDOR_ST) 502 pwr |= MCI_ROD; 503 else { 504 /* 505 * The ST Micro variant use the ROD bit for something 506 * else and only has OD (Open Drain). 507 */ 508 pwr |= MCI_OD; 509 } 510 } 511 512 spin_lock_irqsave(&host->lock, flags); 513 514 mmci_set_clkreg(host, ios->clock); 515 516 if (host->pwr != pwr) { 517 host->pwr = pwr; 518 writel(pwr, host->base + MMCIPOWER); 519 } 520 521 spin_unlock_irqrestore(&host->lock, flags); 522} 523 524static int mmci_get_ro(struct mmc_host *mmc) 525{ 526 struct mmci_host *host = mmc_priv(mmc); 527 528 if (host->gpio_wp == -ENOSYS) 529 return -ENOSYS; 530 531 return gpio_get_value(host->gpio_wp); 532} 533 534static int mmci_get_cd(struct mmc_host *mmc) 535{ 536 struct mmci_host *host = mmc_priv(mmc); 537 unsigned int status; 538 539 if (host->gpio_cd == -ENOSYS) 540 status = host->plat->status(mmc_dev(host->mmc)); 541 else 542 status = gpio_get_value(host->gpio_cd); 543 544 return !status; 545} 546 547static const struct mmc_host_ops mmci_ops = { 548 .request = mmci_request, 549 .set_ios = mmci_set_ios, 550 .get_ro = mmci_get_ro, 551 .get_cd = mmci_get_cd, 552}; 553 554static void mmci_check_status(unsigned long data) 555{ 556 struct mmci_host *host = (struct mmci_host *)data; 557 unsigned int status = mmci_get_cd(host->mmc); 558 559 if (status ^ host->oldstat) 560 mmc_detect_change(host->mmc, 0); 561 562 host->oldstat = status; 563 mod_timer(&host->timer, jiffies + HZ); 564} 565 566static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 567{ 568 struct mmci_platform_data *plat = dev->dev.platform_data; 569 struct mmci_host *host; 570 struct mmc_host *mmc; 571 int ret; 572 573 /* must have platform data */ 574 if (!plat) { 575 ret = -EINVAL; 576 goto out; 577 } 578 579 ret = amba_request_regions(dev, DRIVER_NAME); 580 if (ret) 581 goto out; 582 583 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 584 if (!mmc) { 585 ret = -ENOMEM; 586 goto rel_regions; 587 } 588 589 host = mmc_priv(mmc); 590 host->mmc = mmc; 591 592 host->gpio_wp = -ENOSYS; 593 host->gpio_cd = -ENOSYS; 594 595 host->hw_designer = amba_manf(dev); 596 host->hw_revision = amba_rev(dev); 597 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 598 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 599 600 host->clk = clk_get(&dev->dev, NULL); 601 if (IS_ERR(host->clk)) { 602 ret = PTR_ERR(host->clk); 603 host->clk = NULL; 604 goto host_free; 605 } 606 607 ret = clk_enable(host->clk); 608 if (ret) 609 goto clk_free; 610 611 host->plat = plat; 612 host->mclk = clk_get_rate(host->clk); 613 /* 614 * According to the spec, mclk is max 100 MHz, 615 * so we try to adjust the clock down to this, 616 * (if possible). 617 */ 618 if (host->mclk > 100000000) { 619 ret = clk_set_rate(host->clk, 100000000); 620 if (ret < 0) 621 goto clk_disable; 622 host->mclk = clk_get_rate(host->clk); 623 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 624 host->mclk); 625 } 626 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 627 if (!host->base) { 628 ret = -ENOMEM; 629 goto clk_disable; 630 } 631 632 mmc->ops = &mmci_ops; 633 mmc->f_min = (host->mclk + 511) / 512; 634 /* 635 * If the platform data supplies a maximum operating 636 * frequency, this takes precedence. Else, we fall back 637 * to using the module parameter, which has a (low) 638 * default value in case it is not specified. Either 639 * value must not exceed the clock rate into the block, 640 * of course. 641 */ 642 if (plat->f_max) 643 mmc->f_max = min(host->mclk, plat->f_max); 644 else 645 mmc->f_max = min(host->mclk, fmax); 646 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 647 648#ifdef CONFIG_REGULATOR 649 /* If we're using the regulator framework, try to fetch a regulator */ 650 host->vcc = regulator_get(&dev->dev, "vmmc"); 651 if (IS_ERR(host->vcc)) 652 host->vcc = NULL; 653 else { 654 int mask = mmc_regulator_get_ocrmask(host->vcc); 655 656 if (mask < 0) 657 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 658 mask); 659 else { 660 host->mmc->ocr_avail = (u32) mask; 661 if (plat->ocr_mask) 662 dev_warn(&dev->dev, 663 "Provided ocr_mask/setpower will not be used " 664 "(using regulator instead)\n"); 665 } 666 } 667#endif 668 /* Fall back to platform data if no regulator is found */ 669 if (host->vcc == NULL) 670 mmc->ocr_avail = plat->ocr_mask; 671 mmc->caps = plat->capabilities; 672 673 /* 674 * We can do SGIO 675 */ 676 mmc->max_hw_segs = 16; 677 mmc->max_phys_segs = NR_SG; 678 679 /* 680 * Since we only have a 16-bit data length register, we must 681 * ensure that we don't exceed 2^16-1 bytes in a single request. 682 */ 683 mmc->max_req_size = 65535; 684 685 /* 686 * Set the maximum segment size. Since we aren't doing DMA 687 * (yet) we are only limited by the data length register. 688 */ 689 mmc->max_seg_size = mmc->max_req_size; 690 691 /* 692 * Block size can be up to 2048 bytes, but must be a power of two. 693 */ 694 mmc->max_blk_size = 2048; 695 696 /* 697 * No limit on the number of blocks transferred. 698 */ 699 mmc->max_blk_count = mmc->max_req_size; 700 701 spin_lock_init(&host->lock); 702 703 writel(0, host->base + MMCIMASK0); 704 writel(0, host->base + MMCIMASK1); 705 writel(0xfff, host->base + MMCICLEAR); 706 707 if (gpio_is_valid(plat->gpio_cd)) { 708 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 709 if (ret == 0) 710 ret = gpio_direction_input(plat->gpio_cd); 711 if (ret == 0) 712 host->gpio_cd = plat->gpio_cd; 713 else if (ret != -ENOSYS) 714 goto err_gpio_cd; 715 } 716 if (gpio_is_valid(plat->gpio_wp)) { 717 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 718 if (ret == 0) 719 ret = gpio_direction_input(plat->gpio_wp); 720 if (ret == 0) 721 host->gpio_wp = plat->gpio_wp; 722 else if (ret != -ENOSYS) 723 goto err_gpio_wp; 724 } 725 726 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 727 if (ret) 728 goto unmap; 729 730 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); 731 if (ret) 732 goto irq0_free; 733 734 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 735 736 amba_set_drvdata(dev, mmc); 737 host->oldstat = mmci_get_cd(host->mmc); 738 739 mmc_add_host(mmc); 740 741 dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", 742 mmc_hostname(mmc), amba_rev(dev), amba_config(dev), 743 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 744 745 init_timer(&host->timer); 746 host->timer.data = (unsigned long)host; 747 host->timer.function = mmci_check_status; 748 host->timer.expires = jiffies + HZ; 749 add_timer(&host->timer); 750 751 return 0; 752 753 irq0_free: 754 free_irq(dev->irq[0], host); 755 unmap: 756 if (host->gpio_wp != -ENOSYS) 757 gpio_free(host->gpio_wp); 758 err_gpio_wp: 759 if (host->gpio_cd != -ENOSYS) 760 gpio_free(host->gpio_cd); 761 err_gpio_cd: 762 iounmap(host->base); 763 clk_disable: 764 clk_disable(host->clk); 765 clk_free: 766 clk_put(host->clk); 767 host_free: 768 mmc_free_host(mmc); 769 rel_regions: 770 amba_release_regions(dev); 771 out: 772 return ret; 773} 774 775static int __devexit mmci_remove(struct amba_device *dev) 776{ 777 struct mmc_host *mmc = amba_get_drvdata(dev); 778 779 amba_set_drvdata(dev, NULL); 780 781 if (mmc) { 782 struct mmci_host *host = mmc_priv(mmc); 783 784 del_timer_sync(&host->timer); 785 786 mmc_remove_host(mmc); 787 788 writel(0, host->base + MMCIMASK0); 789 writel(0, host->base + MMCIMASK1); 790 791 writel(0, host->base + MMCICOMMAND); 792 writel(0, host->base + MMCIDATACTRL); 793 794 free_irq(dev->irq[0], host); 795 free_irq(dev->irq[1], host); 796 797 if (host->gpio_wp != -ENOSYS) 798 gpio_free(host->gpio_wp); 799 if (host->gpio_cd != -ENOSYS) 800 gpio_free(host->gpio_cd); 801 802 iounmap(host->base); 803 clk_disable(host->clk); 804 clk_put(host->clk); 805 806 if (regulator_is_enabled(host->vcc)) 807 regulator_disable(host->vcc); 808 regulator_put(host->vcc); 809 810 mmc_free_host(mmc); 811 812 amba_release_regions(dev); 813 } 814 815 return 0; 816} 817 818#ifdef CONFIG_PM 819static int mmci_suspend(struct amba_device *dev, pm_message_t state) 820{ 821 struct mmc_host *mmc = amba_get_drvdata(dev); 822 int ret = 0; 823 824 if (mmc) { 825 struct mmci_host *host = mmc_priv(mmc); 826 827 ret = mmc_suspend_host(mmc, state); 828 if (ret == 0) 829 writel(0, host->base + MMCIMASK0); 830 } 831 832 return ret; 833} 834 835static int mmci_resume(struct amba_device *dev) 836{ 837 struct mmc_host *mmc = amba_get_drvdata(dev); 838 int ret = 0; 839 840 if (mmc) { 841 struct mmci_host *host = mmc_priv(mmc); 842 843 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 844 845 ret = mmc_resume_host(mmc); 846 } 847 848 return ret; 849} 850#else 851#define mmci_suspend NULL 852#define mmci_resume NULL 853#endif 854 855static struct amba_id mmci_ids[] = { 856 { 857 .id = 0x00041180, 858 .mask = 0x000fffff, 859 }, 860 { 861 .id = 0x00041181, 862 .mask = 0x000fffff, 863 }, 864 /* ST Micro variants */ 865 { 866 .id = 0x00180180, 867 .mask = 0x00ffffff, 868 }, 869 { 870 .id = 0x00280180, 871 .mask = 0x00ffffff, 872 }, 873 { 0, 0 }, 874}; 875 876static struct amba_driver mmci_driver = { 877 .drv = { 878 .name = DRIVER_NAME, 879 }, 880 .probe = mmci_probe, 881 .remove = __devexit_p(mmci_remove), 882 .suspend = mmci_suspend, 883 .resume = mmci_resume, 884 .id_table = mmci_ids, 885}; 886 887static int __init mmci_init(void) 888{ 889 return amba_driver_register(&mmci_driver); 890} 891 892static void __exit mmci_exit(void) 893{ 894 amba_driver_unregister(&mmci_driver); 895} 896 897module_init(mmci_init); 898module_exit(mmci_exit); 899module_param(fmax, uint, 0444); 900 901MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 902MODULE_LICENSE("GPL"); 903