mmci.c revision 9c34b73deec147a042c4bd871a373f76af70e38c
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/io.h> 17#include <linux/interrupt.h> 18#include <linux/kernel.h> 19#include <linux/slab.h> 20#include <linux/delay.h> 21#include <linux/err.h> 22#include <linux/highmem.h> 23#include <linux/log2.h> 24#include <linux/mmc/pm.h> 25#include <linux/mmc/host.h> 26#include <linux/mmc/card.h> 27#include <linux/mmc/slot-gpio.h> 28#include <linux/amba/bus.h> 29#include <linux/clk.h> 30#include <linux/scatterlist.h> 31#include <linux/gpio.h> 32#include <linux/of_gpio.h> 33#include <linux/regulator/consumer.h> 34#include <linux/dmaengine.h> 35#include <linux/dma-mapping.h> 36#include <linux/amba/mmci.h> 37#include <linux/pm_runtime.h> 38#include <linux/types.h> 39#include <linux/pinctrl/consumer.h> 40 41#include <asm/div64.h> 42#include <asm/io.h> 43#include <asm/sizes.h> 44 45#include "mmci.h" 46 47#define DRIVER_NAME "mmci-pl18x" 48 49static unsigned int fmax = 515633; 50 51/** 52 * struct variant_data - MMCI variant-specific quirks 53 * @clkreg: default value for MCICLOCK register 54 * @clkreg_enable: enable value for MMCICLOCK register 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 59 * is asserted (likewise for RX) 60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 61 * is asserted (likewise for RX) 62 * @data_cmd_enable: enable value for data commands. 63 * @sdio: variant supports SDIO 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 68 * register 69 * @pwrreg_powerup: power up value for MMCIPOWER register 70 * @f_max: maximum clk frequency supported by the controller. 71 * @signal_direction: input/out direction of bus signals can be indicated 72 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 73 * @busy_detect: true if busy detection on dat0 is supported 74 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 75 * @explicit_mclk_control: enable explicit mclk control in driver. 76 * @qcom_fifo: enables qcom specific fifo pio read logic. 77 */ 78struct variant_data { 79 unsigned int clkreg; 80 unsigned int clkreg_enable; 81 unsigned int clkreg_8bit_bus_enable; 82 unsigned int clkreg_neg_edge_enable; 83 unsigned int datalength_bits; 84 unsigned int fifosize; 85 unsigned int fifohalfsize; 86 unsigned int data_cmd_enable; 87 unsigned int datactrl_mask_ddrmode; 88 bool sdio; 89 bool st_clkdiv; 90 bool blksz_datactrl16; 91 bool blksz_datactrl4; 92 u32 pwrreg_powerup; 93 u32 f_max; 94 bool signal_direction; 95 bool pwrreg_clkgate; 96 bool busy_detect; 97 bool pwrreg_nopower; 98 bool explicit_mclk_control; 99 bool qcom_fifo; 100}; 101 102static struct variant_data variant_arm = { 103 .fifosize = 16 * 4, 104 .fifohalfsize = 8 * 4, 105 .datalength_bits = 16, 106 .pwrreg_powerup = MCI_PWR_UP, 107 .f_max = 100000000, 108}; 109 110static struct variant_data variant_arm_extended_fifo = { 111 .fifosize = 128 * 4, 112 .fifohalfsize = 64 * 4, 113 .datalength_bits = 16, 114 .pwrreg_powerup = MCI_PWR_UP, 115 .f_max = 100000000, 116}; 117 118static struct variant_data variant_arm_extended_fifo_hwfc = { 119 .fifosize = 128 * 4, 120 .fifohalfsize = 64 * 4, 121 .clkreg_enable = MCI_ARM_HWFCEN, 122 .datalength_bits = 16, 123 .pwrreg_powerup = MCI_PWR_UP, 124 .f_max = 100000000, 125}; 126 127static struct variant_data variant_u300 = { 128 .fifosize = 16 * 4, 129 .fifohalfsize = 8 * 4, 130 .clkreg_enable = MCI_ST_U300_HWFCEN, 131 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 132 .datalength_bits = 16, 133 .sdio = true, 134 .pwrreg_powerup = MCI_PWR_ON, 135 .f_max = 100000000, 136 .signal_direction = true, 137 .pwrreg_clkgate = true, 138 .pwrreg_nopower = true, 139}; 140 141static struct variant_data variant_nomadik = { 142 .fifosize = 16 * 4, 143 .fifohalfsize = 8 * 4, 144 .clkreg = MCI_CLK_ENABLE, 145 .datalength_bits = 24, 146 .sdio = true, 147 .st_clkdiv = true, 148 .pwrreg_powerup = MCI_PWR_ON, 149 .f_max = 100000000, 150 .signal_direction = true, 151 .pwrreg_clkgate = true, 152 .pwrreg_nopower = true, 153}; 154 155static struct variant_data variant_ux500 = { 156 .fifosize = 30 * 4, 157 .fifohalfsize = 8 * 4, 158 .clkreg = MCI_CLK_ENABLE, 159 .clkreg_enable = MCI_ST_UX500_HWFCEN, 160 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 161 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 162 .datalength_bits = 24, 163 .sdio = true, 164 .st_clkdiv = true, 165 .pwrreg_powerup = MCI_PWR_ON, 166 .f_max = 100000000, 167 .signal_direction = true, 168 .pwrreg_clkgate = true, 169 .busy_detect = true, 170 .pwrreg_nopower = true, 171}; 172 173static struct variant_data variant_ux500v2 = { 174 .fifosize = 30 * 4, 175 .fifohalfsize = 8 * 4, 176 .clkreg = MCI_CLK_ENABLE, 177 .clkreg_enable = MCI_ST_UX500_HWFCEN, 178 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 179 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 180 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 181 .datalength_bits = 24, 182 .sdio = true, 183 .st_clkdiv = true, 184 .blksz_datactrl16 = true, 185 .pwrreg_powerup = MCI_PWR_ON, 186 .f_max = 100000000, 187 .signal_direction = true, 188 .pwrreg_clkgate = true, 189 .busy_detect = true, 190 .pwrreg_nopower = true, 191}; 192 193static int mmci_card_busy(struct mmc_host *mmc) 194{ 195 struct mmci_host *host = mmc_priv(mmc); 196 unsigned long flags; 197 int busy = 0; 198 199 pm_runtime_get_sync(mmc_dev(mmc)); 200 201 spin_lock_irqsave(&host->lock, flags); 202 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 203 busy = 1; 204 spin_unlock_irqrestore(&host->lock, flags); 205 206 pm_runtime_mark_last_busy(mmc_dev(mmc)); 207 pm_runtime_put_autosuspend(mmc_dev(mmc)); 208 209 return busy; 210} 211 212/* 213 * Validate mmc prerequisites 214 */ 215static int mmci_validate_data(struct mmci_host *host, 216 struct mmc_data *data) 217{ 218 if (!data) 219 return 0; 220 221 if (!is_power_of_2(data->blksz)) { 222 dev_err(mmc_dev(host->mmc), 223 "unsupported block size (%d bytes)\n", data->blksz); 224 return -EINVAL; 225 } 226 227 return 0; 228} 229 230static void mmci_reg_delay(struct mmci_host *host) 231{ 232 /* 233 * According to the spec, at least three feedback clock cycles 234 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 235 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 236 * Worst delay time during card init is at 100 kHz => 30 us. 237 * Worst delay time when up and running is at 25 MHz => 120 ns. 238 */ 239 if (host->cclk < 25000000) 240 udelay(30); 241 else 242 ndelay(120); 243} 244 245/* 246 * This must be called with host->lock held 247 */ 248static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 249{ 250 if (host->clk_reg != clk) { 251 host->clk_reg = clk; 252 writel(clk, host->base + MMCICLOCK); 253 } 254} 255 256/* 257 * This must be called with host->lock held 258 */ 259static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 260{ 261 if (host->pwr_reg != pwr) { 262 host->pwr_reg = pwr; 263 writel(pwr, host->base + MMCIPOWER); 264 } 265} 266 267/* 268 * This must be called with host->lock held 269 */ 270static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 271{ 272 /* Keep ST Micro busy mode if enabled */ 273 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 274 275 if (host->datactrl_reg != datactrl) { 276 host->datactrl_reg = datactrl; 277 writel(datactrl, host->base + MMCIDATACTRL); 278 } 279} 280 281/* 282 * This must be called with host->lock held 283 */ 284static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 285{ 286 struct variant_data *variant = host->variant; 287 u32 clk = variant->clkreg; 288 289 /* Make sure cclk reflects the current calculated clock */ 290 host->cclk = 0; 291 292 if (desired) { 293 if (variant->explicit_mclk_control) { 294 host->cclk = host->mclk; 295 } else if (desired >= host->mclk) { 296 clk = MCI_CLK_BYPASS; 297 if (variant->st_clkdiv) 298 clk |= MCI_ST_UX500_NEG_EDGE; 299 host->cclk = host->mclk; 300 } else if (variant->st_clkdiv) { 301 /* 302 * DB8500 TRM says f = mclk / (clkdiv + 2) 303 * => clkdiv = (mclk / f) - 2 304 * Round the divider up so we don't exceed the max 305 * frequency 306 */ 307 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 308 if (clk >= 256) 309 clk = 255; 310 host->cclk = host->mclk / (clk + 2); 311 } else { 312 /* 313 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 314 * => clkdiv = mclk / (2 * f) - 1 315 */ 316 clk = host->mclk / (2 * desired) - 1; 317 if (clk >= 256) 318 clk = 255; 319 host->cclk = host->mclk / (2 * (clk + 1)); 320 } 321 322 clk |= variant->clkreg_enable; 323 clk |= MCI_CLK_ENABLE; 324 /* This hasn't proven to be worthwhile */ 325 /* clk |= MCI_CLK_PWRSAVE; */ 326 } 327 328 /* Set actual clock for debug */ 329 host->mmc->actual_clock = host->cclk; 330 331 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 332 clk |= MCI_4BIT_BUS; 333 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 334 clk |= variant->clkreg_8bit_bus_enable; 335 336 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 337 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 338 clk |= variant->clkreg_neg_edge_enable; 339 340 mmci_write_clkreg(host, clk); 341} 342 343static void 344mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 345{ 346 writel(0, host->base + MMCICOMMAND); 347 348 BUG_ON(host->data); 349 350 host->mrq = NULL; 351 host->cmd = NULL; 352 353 mmc_request_done(host->mmc, mrq); 354 355 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 356 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 357} 358 359static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 360{ 361 void __iomem *base = host->base; 362 363 if (host->singleirq) { 364 unsigned int mask0 = readl(base + MMCIMASK0); 365 366 mask0 &= ~MCI_IRQ1MASK; 367 mask0 |= mask; 368 369 writel(mask0, base + MMCIMASK0); 370 } 371 372 writel(mask, base + MMCIMASK1); 373} 374 375static void mmci_stop_data(struct mmci_host *host) 376{ 377 mmci_write_datactrlreg(host, 0); 378 mmci_set_mask1(host, 0); 379 host->data = NULL; 380} 381 382static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 383{ 384 unsigned int flags = SG_MITER_ATOMIC; 385 386 if (data->flags & MMC_DATA_READ) 387 flags |= SG_MITER_TO_SG; 388 else 389 flags |= SG_MITER_FROM_SG; 390 391 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 392} 393 394/* 395 * All the DMA operation mode stuff goes inside this ifdef. 396 * This assumes that you have a generic DMA device interface, 397 * no custom DMA interfaces are supported. 398 */ 399#ifdef CONFIG_DMA_ENGINE 400static void mmci_dma_setup(struct mmci_host *host) 401{ 402 const char *rxname, *txname; 403 dma_cap_mask_t mask; 404 405 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 406 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 407 408 /* initialize pre request cookie */ 409 host->next_data.cookie = 1; 410 411 /* Try to acquire a generic DMA engine slave channel */ 412 dma_cap_zero(mask); 413 dma_cap_set(DMA_SLAVE, mask); 414 415 /* 416 * If only an RX channel is specified, the driver will 417 * attempt to use it bidirectionally, however if it is 418 * is specified but cannot be located, DMA will be disabled. 419 */ 420 if (host->dma_rx_channel && !host->dma_tx_channel) 421 host->dma_tx_channel = host->dma_rx_channel; 422 423 if (host->dma_rx_channel) 424 rxname = dma_chan_name(host->dma_rx_channel); 425 else 426 rxname = "none"; 427 428 if (host->dma_tx_channel) 429 txname = dma_chan_name(host->dma_tx_channel); 430 else 431 txname = "none"; 432 433 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 434 rxname, txname); 435 436 /* 437 * Limit the maximum segment size in any SG entry according to 438 * the parameters of the DMA engine device. 439 */ 440 if (host->dma_tx_channel) { 441 struct device *dev = host->dma_tx_channel->device->dev; 442 unsigned int max_seg_size = dma_get_max_seg_size(dev); 443 444 if (max_seg_size < host->mmc->max_seg_size) 445 host->mmc->max_seg_size = max_seg_size; 446 } 447 if (host->dma_rx_channel) { 448 struct device *dev = host->dma_rx_channel->device->dev; 449 unsigned int max_seg_size = dma_get_max_seg_size(dev); 450 451 if (max_seg_size < host->mmc->max_seg_size) 452 host->mmc->max_seg_size = max_seg_size; 453 } 454} 455 456/* 457 * This is used in or so inline it 458 * so it can be discarded. 459 */ 460static inline void mmci_dma_release(struct mmci_host *host) 461{ 462 if (host->dma_rx_channel) 463 dma_release_channel(host->dma_rx_channel); 464 if (host->dma_tx_channel) 465 dma_release_channel(host->dma_tx_channel); 466 host->dma_rx_channel = host->dma_tx_channel = NULL; 467} 468 469static void mmci_dma_data_error(struct mmci_host *host) 470{ 471 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 472 dmaengine_terminate_all(host->dma_current); 473 host->dma_current = NULL; 474 host->dma_desc_current = NULL; 475 host->data->host_cookie = 0; 476} 477 478static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 479{ 480 struct dma_chan *chan; 481 enum dma_data_direction dir; 482 483 if (data->flags & MMC_DATA_READ) { 484 dir = DMA_FROM_DEVICE; 485 chan = host->dma_rx_channel; 486 } else { 487 dir = DMA_TO_DEVICE; 488 chan = host->dma_tx_channel; 489 } 490 491 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 492} 493 494static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 495{ 496 u32 status; 497 int i; 498 499 /* Wait up to 1ms for the DMA to complete */ 500 for (i = 0; ; i++) { 501 status = readl(host->base + MMCISTATUS); 502 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 503 break; 504 udelay(10); 505 } 506 507 /* 508 * Check to see whether we still have some data left in the FIFO - 509 * this catches DMA controllers which are unable to monitor the 510 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 511 * contiguous buffers. On TX, we'll get a FIFO underrun error. 512 */ 513 if (status & MCI_RXDATAAVLBLMASK) { 514 mmci_dma_data_error(host); 515 if (!data->error) 516 data->error = -EIO; 517 } 518 519 if (!data->host_cookie) 520 mmci_dma_unmap(host, data); 521 522 /* 523 * Use of DMA with scatter-gather is impossible. 524 * Give up with DMA and switch back to PIO mode. 525 */ 526 if (status & MCI_RXDATAAVLBLMASK) { 527 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 528 mmci_dma_release(host); 529 } 530 531 host->dma_current = NULL; 532 host->dma_desc_current = NULL; 533} 534 535/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 536static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 537 struct dma_chan **dma_chan, 538 struct dma_async_tx_descriptor **dma_desc) 539{ 540 struct variant_data *variant = host->variant; 541 struct dma_slave_config conf = { 542 .src_addr = host->phybase + MMCIFIFO, 543 .dst_addr = host->phybase + MMCIFIFO, 544 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 545 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 546 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 547 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 548 .device_fc = false, 549 }; 550 struct dma_chan *chan; 551 struct dma_device *device; 552 struct dma_async_tx_descriptor *desc; 553 enum dma_data_direction buffer_dirn; 554 int nr_sg; 555 556 if (data->flags & MMC_DATA_READ) { 557 conf.direction = DMA_DEV_TO_MEM; 558 buffer_dirn = DMA_FROM_DEVICE; 559 chan = host->dma_rx_channel; 560 } else { 561 conf.direction = DMA_MEM_TO_DEV; 562 buffer_dirn = DMA_TO_DEVICE; 563 chan = host->dma_tx_channel; 564 } 565 566 /* If there's no DMA channel, fall back to PIO */ 567 if (!chan) 568 return -EINVAL; 569 570 /* If less than or equal to the fifo size, don't bother with DMA */ 571 if (data->blksz * data->blocks <= variant->fifosize) 572 return -EINVAL; 573 574 device = chan->device; 575 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 576 if (nr_sg == 0) 577 return -EINVAL; 578 579 dmaengine_slave_config(chan, &conf); 580 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 581 conf.direction, DMA_CTRL_ACK); 582 if (!desc) 583 goto unmap_exit; 584 585 *dma_chan = chan; 586 *dma_desc = desc; 587 588 return 0; 589 590 unmap_exit: 591 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 592 return -ENOMEM; 593} 594 595static inline int mmci_dma_prep_data(struct mmci_host *host, 596 struct mmc_data *data) 597{ 598 /* Check if next job is already prepared. */ 599 if (host->dma_current && host->dma_desc_current) 600 return 0; 601 602 /* No job were prepared thus do it now. */ 603 return __mmci_dma_prep_data(host, data, &host->dma_current, 604 &host->dma_desc_current); 605} 606 607static inline int mmci_dma_prep_next(struct mmci_host *host, 608 struct mmc_data *data) 609{ 610 struct mmci_host_next *nd = &host->next_data; 611 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 612} 613 614static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 615{ 616 int ret; 617 struct mmc_data *data = host->data; 618 619 ret = mmci_dma_prep_data(host, host->data); 620 if (ret) 621 return ret; 622 623 /* Okay, go for it. */ 624 dev_vdbg(mmc_dev(host->mmc), 625 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 626 data->sg_len, data->blksz, data->blocks, data->flags); 627 dmaengine_submit(host->dma_desc_current); 628 dma_async_issue_pending(host->dma_current); 629 630 datactrl |= MCI_DPSM_DMAENABLE; 631 632 /* Trigger the DMA transfer */ 633 mmci_write_datactrlreg(host, datactrl); 634 635 /* 636 * Let the MMCI say when the data is ended and it's time 637 * to fire next DMA request. When that happens, MMCI will 638 * call mmci_data_end() 639 */ 640 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 641 host->base + MMCIMASK0); 642 return 0; 643} 644 645static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 646{ 647 struct mmci_host_next *next = &host->next_data; 648 649 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 650 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 651 652 host->dma_desc_current = next->dma_desc; 653 host->dma_current = next->dma_chan; 654 next->dma_desc = NULL; 655 next->dma_chan = NULL; 656} 657 658static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 659 bool is_first_req) 660{ 661 struct mmci_host *host = mmc_priv(mmc); 662 struct mmc_data *data = mrq->data; 663 struct mmci_host_next *nd = &host->next_data; 664 665 if (!data) 666 return; 667 668 BUG_ON(data->host_cookie); 669 670 if (mmci_validate_data(host, data)) 671 return; 672 673 if (!mmci_dma_prep_next(host, data)) 674 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 675} 676 677static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 678 int err) 679{ 680 struct mmci_host *host = mmc_priv(mmc); 681 struct mmc_data *data = mrq->data; 682 683 if (!data || !data->host_cookie) 684 return; 685 686 mmci_dma_unmap(host, data); 687 688 if (err) { 689 struct mmci_host_next *next = &host->next_data; 690 struct dma_chan *chan; 691 if (data->flags & MMC_DATA_READ) 692 chan = host->dma_rx_channel; 693 else 694 chan = host->dma_tx_channel; 695 dmaengine_terminate_all(chan); 696 697 next->dma_desc = NULL; 698 next->dma_chan = NULL; 699 } 700} 701 702#else 703/* Blank functions if the DMA engine is not available */ 704static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 705{ 706} 707static inline void mmci_dma_setup(struct mmci_host *host) 708{ 709} 710 711static inline void mmci_dma_release(struct mmci_host *host) 712{ 713} 714 715static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 716{ 717} 718 719static inline void mmci_dma_finalize(struct mmci_host *host, 720 struct mmc_data *data) 721{ 722} 723 724static inline void mmci_dma_data_error(struct mmci_host *host) 725{ 726} 727 728static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 729{ 730 return -ENOSYS; 731} 732 733#define mmci_pre_request NULL 734#define mmci_post_request NULL 735 736#endif 737 738static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 739{ 740 struct variant_data *variant = host->variant; 741 unsigned int datactrl, timeout, irqmask; 742 unsigned long long clks; 743 void __iomem *base; 744 int blksz_bits; 745 746 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 747 data->blksz, data->blocks, data->flags); 748 749 host->data = data; 750 host->size = data->blksz * data->blocks; 751 data->bytes_xfered = 0; 752 753 clks = (unsigned long long)data->timeout_ns * host->cclk; 754 do_div(clks, NSEC_PER_SEC); 755 756 timeout = data->timeout_clks + (unsigned int)clks; 757 758 base = host->base; 759 writel(timeout, base + MMCIDATATIMER); 760 writel(host->size, base + MMCIDATALENGTH); 761 762 blksz_bits = ffs(data->blksz) - 1; 763 BUG_ON(1 << blksz_bits != data->blksz); 764 765 if (variant->blksz_datactrl16) 766 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 767 else if (variant->blksz_datactrl4) 768 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 769 else 770 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 771 772 if (data->flags & MMC_DATA_READ) 773 datactrl |= MCI_DPSM_DIRECTION; 774 775 /* The ST Micro variants has a special bit to enable SDIO */ 776 if (variant->sdio && host->mmc->card) 777 if (mmc_card_sdio(host->mmc->card)) { 778 /* 779 * The ST Micro variants has a special bit 780 * to enable SDIO. 781 */ 782 u32 clk; 783 784 datactrl |= MCI_ST_DPSM_SDIOEN; 785 786 /* 787 * The ST Micro variant for SDIO small write transfers 788 * needs to have clock H/W flow control disabled, 789 * otherwise the transfer will not start. The threshold 790 * depends on the rate of MCLK. 791 */ 792 if (data->flags & MMC_DATA_WRITE && 793 (host->size < 8 || 794 (host->size <= 8 && host->mclk > 50000000))) 795 clk = host->clk_reg & ~variant->clkreg_enable; 796 else 797 clk = host->clk_reg | variant->clkreg_enable; 798 799 mmci_write_clkreg(host, clk); 800 } 801 802 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 803 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 804 datactrl |= variant->datactrl_mask_ddrmode; 805 806 /* 807 * Attempt to use DMA operation mode, if this 808 * should fail, fall back to PIO mode 809 */ 810 if (!mmci_dma_start_data(host, datactrl)) 811 return; 812 813 /* IRQ mode, map the SG list for CPU reading/writing */ 814 mmci_init_sg(host, data); 815 816 if (data->flags & MMC_DATA_READ) { 817 irqmask = MCI_RXFIFOHALFFULLMASK; 818 819 /* 820 * If we have less than the fifo 'half-full' threshold to 821 * transfer, trigger a PIO interrupt as soon as any data 822 * is available. 823 */ 824 if (host->size < variant->fifohalfsize) 825 irqmask |= MCI_RXDATAAVLBLMASK; 826 } else { 827 /* 828 * We don't actually need to include "FIFO empty" here 829 * since its implicit in "FIFO half empty". 830 */ 831 irqmask = MCI_TXFIFOHALFEMPTYMASK; 832 } 833 834 mmci_write_datactrlreg(host, datactrl); 835 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 836 mmci_set_mask1(host, irqmask); 837} 838 839static void 840mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 841{ 842 void __iomem *base = host->base; 843 844 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 845 cmd->opcode, cmd->arg, cmd->flags); 846 847 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 848 writel(0, base + MMCICOMMAND); 849 mmci_reg_delay(host); 850 } 851 852 c |= cmd->opcode | MCI_CPSM_ENABLE; 853 if (cmd->flags & MMC_RSP_PRESENT) { 854 if (cmd->flags & MMC_RSP_136) 855 c |= MCI_CPSM_LONGRSP; 856 c |= MCI_CPSM_RESPONSE; 857 } 858 if (/*interrupt*/0) 859 c |= MCI_CPSM_INTERRUPT; 860 861 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 862 c |= host->variant->data_cmd_enable; 863 864 host->cmd = cmd; 865 866 writel(cmd->arg, base + MMCIARGUMENT); 867 writel(c, base + MMCICOMMAND); 868} 869 870static void 871mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 872 unsigned int status) 873{ 874 /* First check for errors */ 875 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 876 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 877 u32 remain, success; 878 879 /* Terminate the DMA transfer */ 880 if (dma_inprogress(host)) { 881 mmci_dma_data_error(host); 882 mmci_dma_unmap(host, data); 883 } 884 885 /* 886 * Calculate how far we are into the transfer. Note that 887 * the data counter gives the number of bytes transferred 888 * on the MMC bus, not on the host side. On reads, this 889 * can be as much as a FIFO-worth of data ahead. This 890 * matters for FIFO overruns only. 891 */ 892 remain = readl(host->base + MMCIDATACNT); 893 success = data->blksz * data->blocks - remain; 894 895 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 896 status, success); 897 if (status & MCI_DATACRCFAIL) { 898 /* Last block was not successful */ 899 success -= 1; 900 data->error = -EILSEQ; 901 } else if (status & MCI_DATATIMEOUT) { 902 data->error = -ETIMEDOUT; 903 } else if (status & MCI_STARTBITERR) { 904 data->error = -ECOMM; 905 } else if (status & MCI_TXUNDERRUN) { 906 data->error = -EIO; 907 } else if (status & MCI_RXOVERRUN) { 908 if (success > host->variant->fifosize) 909 success -= host->variant->fifosize; 910 else 911 success = 0; 912 data->error = -EIO; 913 } 914 data->bytes_xfered = round_down(success, data->blksz); 915 } 916 917 if (status & MCI_DATABLOCKEND) 918 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 919 920 if (status & MCI_DATAEND || data->error) { 921 if (dma_inprogress(host)) 922 mmci_dma_finalize(host, data); 923 mmci_stop_data(host); 924 925 if (!data->error) 926 /* The error clause is handled above, success! */ 927 data->bytes_xfered = data->blksz * data->blocks; 928 929 if (!data->stop || host->mrq->sbc) { 930 mmci_request_end(host, data->mrq); 931 } else { 932 mmci_start_command(host, data->stop, 0); 933 } 934 } 935} 936 937static void 938mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 939 unsigned int status) 940{ 941 void __iomem *base = host->base; 942 bool sbc = (cmd == host->mrq->sbc); 943 bool busy_resp = host->variant->busy_detect && 944 (cmd->flags & MMC_RSP_BUSY); 945 946 /* Check if we need to wait for busy completion. */ 947 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 948 return; 949 950 /* Enable busy completion if needed and supported. */ 951 if (!host->busy_status && busy_resp && 952 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 953 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 954 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 955 base + MMCIMASK0); 956 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 957 return; 958 } 959 960 /* At busy completion, mask the IRQ and complete the request. */ 961 if (host->busy_status) { 962 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 963 base + MMCIMASK0); 964 host->busy_status = 0; 965 } 966 967 host->cmd = NULL; 968 969 if (status & MCI_CMDTIMEOUT) { 970 cmd->error = -ETIMEDOUT; 971 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 972 cmd->error = -EILSEQ; 973 } else { 974 cmd->resp[0] = readl(base + MMCIRESPONSE0); 975 cmd->resp[1] = readl(base + MMCIRESPONSE1); 976 cmd->resp[2] = readl(base + MMCIRESPONSE2); 977 cmd->resp[3] = readl(base + MMCIRESPONSE3); 978 } 979 980 if ((!sbc && !cmd->data) || cmd->error) { 981 if (host->data) { 982 /* Terminate the DMA transfer */ 983 if (dma_inprogress(host)) { 984 mmci_dma_data_error(host); 985 mmci_dma_unmap(host, host->data); 986 } 987 mmci_stop_data(host); 988 } 989 mmci_request_end(host, host->mrq); 990 } else if (sbc) { 991 mmci_start_command(host, host->mrq->cmd, 0); 992 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 993 mmci_start_data(host, cmd->data); 994 } 995} 996 997static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) 998{ 999 return remain - (readl(host->base + MMCIFIFOCNT) << 2); 1000} 1001 1002static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) 1003{ 1004 /* 1005 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses 1006 * from the fifo range should be used 1007 */ 1008 if (status & MCI_RXFIFOHALFFULL) 1009 return host->variant->fifohalfsize; 1010 else if (status & MCI_RXDATAAVLBL) 1011 return 4; 1012 1013 return 0; 1014} 1015 1016static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 1017{ 1018 void __iomem *base = host->base; 1019 char *ptr = buffer; 1020 u32 status = readl(host->base + MMCISTATUS); 1021 int host_remain = host->size; 1022 1023 do { 1024 int count = host->get_rx_fifocnt(host, status, host_remain); 1025 1026 if (count > remain) 1027 count = remain; 1028 1029 if (count <= 0) 1030 break; 1031 1032 /* 1033 * SDIO especially may want to send something that is 1034 * not divisible by 4 (as opposed to card sectors 1035 * etc). Therefore make sure to always read the last bytes 1036 * while only doing full 32-bit reads towards the FIFO. 1037 */ 1038 if (unlikely(count & 0x3)) { 1039 if (count < 4) { 1040 unsigned char buf[4]; 1041 ioread32_rep(base + MMCIFIFO, buf, 1); 1042 memcpy(ptr, buf, count); 1043 } else { 1044 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1045 count &= ~0x3; 1046 } 1047 } else { 1048 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1049 } 1050 1051 ptr += count; 1052 remain -= count; 1053 host_remain -= count; 1054 1055 if (remain == 0) 1056 break; 1057 1058 status = readl(base + MMCISTATUS); 1059 } while (status & MCI_RXDATAAVLBL); 1060 1061 return ptr - buffer; 1062} 1063 1064static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1065{ 1066 struct variant_data *variant = host->variant; 1067 void __iomem *base = host->base; 1068 char *ptr = buffer; 1069 1070 do { 1071 unsigned int count, maxcnt; 1072 1073 maxcnt = status & MCI_TXFIFOEMPTY ? 1074 variant->fifosize : variant->fifohalfsize; 1075 count = min(remain, maxcnt); 1076 1077 /* 1078 * SDIO especially may want to send something that is 1079 * not divisible by 4 (as opposed to card sectors 1080 * etc), and the FIFO only accept full 32-bit writes. 1081 * So compensate by adding +3 on the count, a single 1082 * byte become a 32bit write, 7 bytes will be two 1083 * 32bit writes etc. 1084 */ 1085 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1086 1087 ptr += count; 1088 remain -= count; 1089 1090 if (remain == 0) 1091 break; 1092 1093 status = readl(base + MMCISTATUS); 1094 } while (status & MCI_TXFIFOHALFEMPTY); 1095 1096 return ptr - buffer; 1097} 1098 1099/* 1100 * PIO data transfer IRQ handler. 1101 */ 1102static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1103{ 1104 struct mmci_host *host = dev_id; 1105 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1106 struct variant_data *variant = host->variant; 1107 void __iomem *base = host->base; 1108 unsigned long flags; 1109 u32 status; 1110 1111 status = readl(base + MMCISTATUS); 1112 1113 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1114 1115 local_irq_save(flags); 1116 1117 do { 1118 unsigned int remain, len; 1119 char *buffer; 1120 1121 /* 1122 * For write, we only need to test the half-empty flag 1123 * here - if the FIFO is completely empty, then by 1124 * definition it is more than half empty. 1125 * 1126 * For read, check for data available. 1127 */ 1128 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1129 break; 1130 1131 if (!sg_miter_next(sg_miter)) 1132 break; 1133 1134 buffer = sg_miter->addr; 1135 remain = sg_miter->length; 1136 1137 len = 0; 1138 if (status & MCI_RXACTIVE) 1139 len = mmci_pio_read(host, buffer, remain); 1140 if (status & MCI_TXACTIVE) 1141 len = mmci_pio_write(host, buffer, remain, status); 1142 1143 sg_miter->consumed = len; 1144 1145 host->size -= len; 1146 remain -= len; 1147 1148 if (remain) 1149 break; 1150 1151 status = readl(base + MMCISTATUS); 1152 } while (1); 1153 1154 sg_miter_stop(sg_miter); 1155 1156 local_irq_restore(flags); 1157 1158 /* 1159 * If we have less than the fifo 'half-full' threshold to transfer, 1160 * trigger a PIO interrupt as soon as any data is available. 1161 */ 1162 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1163 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1164 1165 /* 1166 * If we run out of data, disable the data IRQs; this 1167 * prevents a race where the FIFO becomes empty before 1168 * the chip itself has disabled the data path, and 1169 * stops us racing with our data end IRQ. 1170 */ 1171 if (host->size == 0) { 1172 mmci_set_mask1(host, 0); 1173 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1174 } 1175 1176 return IRQ_HANDLED; 1177} 1178 1179/* 1180 * Handle completion of command and data transfers. 1181 */ 1182static irqreturn_t mmci_irq(int irq, void *dev_id) 1183{ 1184 struct mmci_host *host = dev_id; 1185 u32 status; 1186 int ret = 0; 1187 1188 spin_lock(&host->lock); 1189 1190 do { 1191 struct mmc_command *cmd; 1192 struct mmc_data *data; 1193 1194 status = readl(host->base + MMCISTATUS); 1195 1196 if (host->singleirq) { 1197 if (status & readl(host->base + MMCIMASK1)) 1198 mmci_pio_irq(irq, dev_id); 1199 1200 status &= ~MCI_IRQ1MASK; 1201 } 1202 1203 /* 1204 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1205 * enabled) since the HW seems to be triggering the IRQ on both 1206 * edges while monitoring DAT0 for busy completion. 1207 */ 1208 status &= readl(host->base + MMCIMASK0); 1209 writel(status, host->base + MMCICLEAR); 1210 1211 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1212 1213 cmd = host->cmd; 1214 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 1215 MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1216 mmci_cmd_irq(host, cmd, status); 1217 1218 data = host->data; 1219 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1220 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1221 MCI_DATABLOCKEND) && data) 1222 mmci_data_irq(host, data, status); 1223 1224 /* Don't poll for busy completion in irq context. */ 1225 if (host->busy_status) 1226 status &= ~MCI_ST_CARDBUSY; 1227 1228 ret = 1; 1229 } while (status); 1230 1231 spin_unlock(&host->lock); 1232 1233 return IRQ_RETVAL(ret); 1234} 1235 1236static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1237{ 1238 struct mmci_host *host = mmc_priv(mmc); 1239 unsigned long flags; 1240 1241 WARN_ON(host->mrq != NULL); 1242 1243 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1244 if (mrq->cmd->error) { 1245 mmc_request_done(mmc, mrq); 1246 return; 1247 } 1248 1249 pm_runtime_get_sync(mmc_dev(mmc)); 1250 1251 spin_lock_irqsave(&host->lock, flags); 1252 1253 host->mrq = mrq; 1254 1255 if (mrq->data) 1256 mmci_get_next_data(host, mrq->data); 1257 1258 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1259 mmci_start_data(host, mrq->data); 1260 1261 if (mrq->sbc) 1262 mmci_start_command(host, mrq->sbc, 0); 1263 else 1264 mmci_start_command(host, mrq->cmd, 0); 1265 1266 spin_unlock_irqrestore(&host->lock, flags); 1267} 1268 1269static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1270{ 1271 struct mmci_host *host = mmc_priv(mmc); 1272 struct variant_data *variant = host->variant; 1273 u32 pwr = 0; 1274 unsigned long flags; 1275 int ret; 1276 1277 pm_runtime_get_sync(mmc_dev(mmc)); 1278 1279 if (host->plat->ios_handler && 1280 host->plat->ios_handler(mmc_dev(mmc), ios)) 1281 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1282 1283 switch (ios->power_mode) { 1284 case MMC_POWER_OFF: 1285 if (!IS_ERR(mmc->supply.vmmc)) 1286 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1287 1288 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1289 regulator_disable(mmc->supply.vqmmc); 1290 host->vqmmc_enabled = false; 1291 } 1292 1293 break; 1294 case MMC_POWER_UP: 1295 if (!IS_ERR(mmc->supply.vmmc)) 1296 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1297 1298 /* 1299 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1300 * and instead uses MCI_PWR_ON so apply whatever value is 1301 * configured in the variant data. 1302 */ 1303 pwr |= variant->pwrreg_powerup; 1304 1305 break; 1306 case MMC_POWER_ON: 1307 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1308 ret = regulator_enable(mmc->supply.vqmmc); 1309 if (ret < 0) 1310 dev_err(mmc_dev(mmc), 1311 "failed to enable vqmmc regulator\n"); 1312 else 1313 host->vqmmc_enabled = true; 1314 } 1315 1316 pwr |= MCI_PWR_ON; 1317 break; 1318 } 1319 1320 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1321 /* 1322 * The ST Micro variant has some additional bits 1323 * indicating signal direction for the signals in 1324 * the SD/MMC bus and feedback-clock usage. 1325 */ 1326 pwr |= host->pwr_reg_add; 1327 1328 if (ios->bus_width == MMC_BUS_WIDTH_4) 1329 pwr &= ~MCI_ST_DATA74DIREN; 1330 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1331 pwr &= (~MCI_ST_DATA74DIREN & 1332 ~MCI_ST_DATA31DIREN & 1333 ~MCI_ST_DATA2DIREN); 1334 } 1335 1336 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1337 if (host->hw_designer != AMBA_VENDOR_ST) 1338 pwr |= MCI_ROD; 1339 else { 1340 /* 1341 * The ST Micro variant use the ROD bit for something 1342 * else and only has OD (Open Drain). 1343 */ 1344 pwr |= MCI_OD; 1345 } 1346 } 1347 1348 /* 1349 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1350 * gating the clock, the MCI_PWR_ON bit is cleared. 1351 */ 1352 if (!ios->clock && variant->pwrreg_clkgate) 1353 pwr &= ~MCI_PWR_ON; 1354 1355 if (host->variant->explicit_mclk_control && 1356 ios->clock != host->clock_cache) { 1357 ret = clk_set_rate(host->clk, ios->clock); 1358 if (ret < 0) 1359 dev_err(mmc_dev(host->mmc), 1360 "Error setting clock rate (%d)\n", ret); 1361 else 1362 host->mclk = clk_get_rate(host->clk); 1363 } 1364 host->clock_cache = ios->clock; 1365 1366 spin_lock_irqsave(&host->lock, flags); 1367 1368 mmci_set_clkreg(host, ios->clock); 1369 mmci_write_pwrreg(host, pwr); 1370 mmci_reg_delay(host); 1371 1372 spin_unlock_irqrestore(&host->lock, flags); 1373 1374 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1375 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1376} 1377 1378static int mmci_get_cd(struct mmc_host *mmc) 1379{ 1380 struct mmci_host *host = mmc_priv(mmc); 1381 struct mmci_platform_data *plat = host->plat; 1382 unsigned int status = mmc_gpio_get_cd(mmc); 1383 1384 if (status == -ENOSYS) { 1385 if (!plat->status) 1386 return 1; /* Assume always present */ 1387 1388 status = plat->status(mmc_dev(host->mmc)); 1389 } 1390 return status; 1391} 1392 1393static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1394{ 1395 int ret = 0; 1396 1397 if (!IS_ERR(mmc->supply.vqmmc)) { 1398 1399 pm_runtime_get_sync(mmc_dev(mmc)); 1400 1401 switch (ios->signal_voltage) { 1402 case MMC_SIGNAL_VOLTAGE_330: 1403 ret = regulator_set_voltage(mmc->supply.vqmmc, 1404 2700000, 3600000); 1405 break; 1406 case MMC_SIGNAL_VOLTAGE_180: 1407 ret = regulator_set_voltage(mmc->supply.vqmmc, 1408 1700000, 1950000); 1409 break; 1410 case MMC_SIGNAL_VOLTAGE_120: 1411 ret = regulator_set_voltage(mmc->supply.vqmmc, 1412 1100000, 1300000); 1413 break; 1414 } 1415 1416 if (ret) 1417 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1418 1419 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1420 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1421 } 1422 1423 return ret; 1424} 1425 1426static struct mmc_host_ops mmci_ops = { 1427 .request = mmci_request, 1428 .pre_req = mmci_pre_request, 1429 .post_req = mmci_post_request, 1430 .set_ios = mmci_set_ios, 1431 .get_ro = mmc_gpio_get_ro, 1432 .get_cd = mmci_get_cd, 1433 .start_signal_voltage_switch = mmci_sig_volt_switch, 1434}; 1435 1436static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1437{ 1438 struct mmci_host *host = mmc_priv(mmc); 1439 int ret = mmc_of_parse(mmc); 1440 1441 if (ret) 1442 return ret; 1443 1444 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1445 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1446 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1447 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1448 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1449 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1450 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1451 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1452 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1453 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1454 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1455 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1456 1457 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1458 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1459 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1460 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1461 1462 return 0; 1463} 1464 1465static int mmci_probe(struct amba_device *dev, 1466 const struct amba_id *id) 1467{ 1468 struct mmci_platform_data *plat = dev->dev.platform_data; 1469 struct device_node *np = dev->dev.of_node; 1470 struct variant_data *variant = id->data; 1471 struct mmci_host *host; 1472 struct mmc_host *mmc; 1473 int ret; 1474 1475 /* Must have platform data or Device Tree. */ 1476 if (!plat && !np) { 1477 dev_err(&dev->dev, "No plat data or DT found\n"); 1478 return -EINVAL; 1479 } 1480 1481 if (!plat) { 1482 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1483 if (!plat) 1484 return -ENOMEM; 1485 } 1486 1487 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1488 if (!mmc) 1489 return -ENOMEM; 1490 1491 ret = mmci_of_parse(np, mmc); 1492 if (ret) 1493 goto host_free; 1494 1495 host = mmc_priv(mmc); 1496 host->mmc = mmc; 1497 1498 host->hw_designer = amba_manf(dev); 1499 host->hw_revision = amba_rev(dev); 1500 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1501 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1502 1503 host->clk = devm_clk_get(&dev->dev, NULL); 1504 if (IS_ERR(host->clk)) { 1505 ret = PTR_ERR(host->clk); 1506 goto host_free; 1507 } 1508 1509 ret = clk_prepare_enable(host->clk); 1510 if (ret) 1511 goto host_free; 1512 1513 if (variant->qcom_fifo) 1514 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; 1515 else 1516 host->get_rx_fifocnt = mmci_get_rx_fifocnt; 1517 1518 host->plat = plat; 1519 host->variant = variant; 1520 host->mclk = clk_get_rate(host->clk); 1521 /* 1522 * According to the spec, mclk is max 100 MHz, 1523 * so we try to adjust the clock down to this, 1524 * (if possible). 1525 */ 1526 if (host->mclk > variant->f_max) { 1527 ret = clk_set_rate(host->clk, variant->f_max); 1528 if (ret < 0) 1529 goto clk_disable; 1530 host->mclk = clk_get_rate(host->clk); 1531 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1532 host->mclk); 1533 } 1534 1535 host->phybase = dev->res.start; 1536 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1537 if (IS_ERR(host->base)) { 1538 ret = PTR_ERR(host->base); 1539 goto clk_disable; 1540 } 1541 1542 /* 1543 * The ARM and ST versions of the block have slightly different 1544 * clock divider equations which means that the minimum divider 1545 * differs too. 1546 * on Qualcomm like controllers get the nearest minimum clock to 100Khz 1547 */ 1548 if (variant->st_clkdiv) 1549 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1550 else if (variant->explicit_mclk_control) 1551 mmc->f_min = clk_round_rate(host->clk, 100000); 1552 else 1553 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1554 /* 1555 * If no maximum operating frequency is supplied, fall back to use 1556 * the module parameter, which has a (low) default value in case it 1557 * is not specified. Either value must not exceed the clock rate into 1558 * the block, of course. 1559 */ 1560 if (mmc->f_max) 1561 mmc->f_max = variant->explicit_mclk_control ? 1562 min(variant->f_max, mmc->f_max) : 1563 min(host->mclk, mmc->f_max); 1564 else 1565 mmc->f_max = variant->explicit_mclk_control ? 1566 fmax : min(host->mclk, fmax); 1567 1568 1569 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1570 1571 /* Get regulators and the supported OCR mask */ 1572 mmc_regulator_get_supply(mmc); 1573 if (!mmc->ocr_avail) 1574 mmc->ocr_avail = plat->ocr_mask; 1575 else if (plat->ocr_mask) 1576 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1577 1578 /* DT takes precedence over platform data. */ 1579 if (!np) { 1580 if (!plat->cd_invert) 1581 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1582 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1583 } 1584 1585 /* We support these capabilities. */ 1586 mmc->caps |= MMC_CAP_CMD23; 1587 1588 if (variant->busy_detect) { 1589 mmci_ops.card_busy = mmci_card_busy; 1590 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1591 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1592 mmc->max_busy_timeout = 0; 1593 } 1594 1595 mmc->ops = &mmci_ops; 1596 1597 /* We support these PM capabilities. */ 1598 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1599 1600 /* 1601 * We can do SGIO 1602 */ 1603 mmc->max_segs = NR_SG; 1604 1605 /* 1606 * Since only a certain number of bits are valid in the data length 1607 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1608 * single request. 1609 */ 1610 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1611 1612 /* 1613 * Set the maximum segment size. Since we aren't doing DMA 1614 * (yet) we are only limited by the data length register. 1615 */ 1616 mmc->max_seg_size = mmc->max_req_size; 1617 1618 /* 1619 * Block size can be up to 2048 bytes, but must be a power of two. 1620 */ 1621 mmc->max_blk_size = 1 << 11; 1622 1623 /* 1624 * Limit the number of blocks transferred so that we don't overflow 1625 * the maximum request size. 1626 */ 1627 mmc->max_blk_count = mmc->max_req_size >> 11; 1628 1629 spin_lock_init(&host->lock); 1630 1631 writel(0, host->base + MMCIMASK0); 1632 writel(0, host->base + MMCIMASK1); 1633 writel(0xfff, host->base + MMCICLEAR); 1634 1635 /* If DT, cd/wp gpios must be supplied through it. */ 1636 if (!np && gpio_is_valid(plat->gpio_cd)) { 1637 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1638 if (ret) 1639 goto clk_disable; 1640 } 1641 if (!np && gpio_is_valid(plat->gpio_wp)) { 1642 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1643 if (ret) 1644 goto clk_disable; 1645 } 1646 1647 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1648 DRIVER_NAME " (cmd)", host); 1649 if (ret) 1650 goto clk_disable; 1651 1652 if (!dev->irq[1]) 1653 host->singleirq = true; 1654 else { 1655 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1656 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1657 if (ret) 1658 goto clk_disable; 1659 } 1660 1661 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1662 1663 amba_set_drvdata(dev, mmc); 1664 1665 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1666 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1667 amba_rev(dev), (unsigned long long)dev->res.start, 1668 dev->irq[0], dev->irq[1]); 1669 1670 mmci_dma_setup(host); 1671 1672 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1673 pm_runtime_use_autosuspend(&dev->dev); 1674 pm_runtime_put(&dev->dev); 1675 1676 mmc_add_host(mmc); 1677 1678 return 0; 1679 1680 clk_disable: 1681 clk_disable_unprepare(host->clk); 1682 host_free: 1683 mmc_free_host(mmc); 1684 return ret; 1685} 1686 1687static int mmci_remove(struct amba_device *dev) 1688{ 1689 struct mmc_host *mmc = amba_get_drvdata(dev); 1690 1691 if (mmc) { 1692 struct mmci_host *host = mmc_priv(mmc); 1693 1694 /* 1695 * Undo pm_runtime_put() in probe. We use the _sync 1696 * version here so that we can access the primecell. 1697 */ 1698 pm_runtime_get_sync(&dev->dev); 1699 1700 mmc_remove_host(mmc); 1701 1702 writel(0, host->base + MMCIMASK0); 1703 writel(0, host->base + MMCIMASK1); 1704 1705 writel(0, host->base + MMCICOMMAND); 1706 writel(0, host->base + MMCIDATACTRL); 1707 1708 mmci_dma_release(host); 1709 clk_disable_unprepare(host->clk); 1710 mmc_free_host(mmc); 1711 } 1712 1713 return 0; 1714} 1715 1716#ifdef CONFIG_PM 1717static void mmci_save(struct mmci_host *host) 1718{ 1719 unsigned long flags; 1720 1721 spin_lock_irqsave(&host->lock, flags); 1722 1723 writel(0, host->base + MMCIMASK0); 1724 if (host->variant->pwrreg_nopower) { 1725 writel(0, host->base + MMCIDATACTRL); 1726 writel(0, host->base + MMCIPOWER); 1727 writel(0, host->base + MMCICLOCK); 1728 } 1729 mmci_reg_delay(host); 1730 1731 spin_unlock_irqrestore(&host->lock, flags); 1732} 1733 1734static void mmci_restore(struct mmci_host *host) 1735{ 1736 unsigned long flags; 1737 1738 spin_lock_irqsave(&host->lock, flags); 1739 1740 if (host->variant->pwrreg_nopower) { 1741 writel(host->clk_reg, host->base + MMCICLOCK); 1742 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1743 writel(host->pwr_reg, host->base + MMCIPOWER); 1744 } 1745 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1746 mmci_reg_delay(host); 1747 1748 spin_unlock_irqrestore(&host->lock, flags); 1749} 1750 1751static int mmci_runtime_suspend(struct device *dev) 1752{ 1753 struct amba_device *adev = to_amba_device(dev); 1754 struct mmc_host *mmc = amba_get_drvdata(adev); 1755 1756 if (mmc) { 1757 struct mmci_host *host = mmc_priv(mmc); 1758 pinctrl_pm_select_sleep_state(dev); 1759 mmci_save(host); 1760 clk_disable_unprepare(host->clk); 1761 } 1762 1763 return 0; 1764} 1765 1766static int mmci_runtime_resume(struct device *dev) 1767{ 1768 struct amba_device *adev = to_amba_device(dev); 1769 struct mmc_host *mmc = amba_get_drvdata(adev); 1770 1771 if (mmc) { 1772 struct mmci_host *host = mmc_priv(mmc); 1773 clk_prepare_enable(host->clk); 1774 mmci_restore(host); 1775 pinctrl_pm_select_default_state(dev); 1776 } 1777 1778 return 0; 1779} 1780#endif 1781 1782static const struct dev_pm_ops mmci_dev_pm_ops = { 1783 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1784 pm_runtime_force_resume) 1785 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1786}; 1787 1788static struct amba_id mmci_ids[] = { 1789 { 1790 .id = 0x00041180, 1791 .mask = 0xff0fffff, 1792 .data = &variant_arm, 1793 }, 1794 { 1795 .id = 0x01041180, 1796 .mask = 0xff0fffff, 1797 .data = &variant_arm_extended_fifo, 1798 }, 1799 { 1800 .id = 0x02041180, 1801 .mask = 0xff0fffff, 1802 .data = &variant_arm_extended_fifo_hwfc, 1803 }, 1804 { 1805 .id = 0x00041181, 1806 .mask = 0x000fffff, 1807 .data = &variant_arm, 1808 }, 1809 /* ST Micro variants */ 1810 { 1811 .id = 0x00180180, 1812 .mask = 0x00ffffff, 1813 .data = &variant_u300, 1814 }, 1815 { 1816 .id = 0x10180180, 1817 .mask = 0xf0ffffff, 1818 .data = &variant_nomadik, 1819 }, 1820 { 1821 .id = 0x00280180, 1822 .mask = 0x00ffffff, 1823 .data = &variant_u300, 1824 }, 1825 { 1826 .id = 0x00480180, 1827 .mask = 0xf0ffffff, 1828 .data = &variant_ux500, 1829 }, 1830 { 1831 .id = 0x10480180, 1832 .mask = 0xf0ffffff, 1833 .data = &variant_ux500v2, 1834 }, 1835 { 0, 0 }, 1836}; 1837 1838MODULE_DEVICE_TABLE(amba, mmci_ids); 1839 1840static struct amba_driver mmci_driver = { 1841 .drv = { 1842 .name = DRIVER_NAME, 1843 .pm = &mmci_dev_pm_ops, 1844 }, 1845 .probe = mmci_probe, 1846 .remove = mmci_remove, 1847 .id_table = mmci_ids, 1848}; 1849 1850module_amba_driver(mmci_driver); 1851 1852module_param(fmax, uint, 0444); 1853 1854MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1855MODULE_LICENSE("GPL"); 1856