mmci.c revision 9cc639a20fdc0b935e55d4992f93963f95233ca4
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/highmem.h> 22#include <linux/log2.h> 23#include <linux/mmc/pm.h> 24#include <linux/mmc/host.h> 25#include <linux/mmc/card.h> 26#include <linux/amba/bus.h> 27#include <linux/clk.h> 28#include <linux/scatterlist.h> 29#include <linux/gpio.h> 30#include <linux/of_gpio.h> 31#include <linux/regulator/consumer.h> 32#include <linux/dmaengine.h> 33#include <linux/dma-mapping.h> 34#include <linux/amba/mmci.h> 35#include <linux/pm_runtime.h> 36#include <linux/types.h> 37#include <linux/pinctrl/consumer.h> 38 39#include <asm/div64.h> 40#include <asm/io.h> 41#include <asm/sizes.h> 42 43#include "mmci.h" 44 45#define DRIVER_NAME "mmci-pl18x" 46 47static unsigned int fmax = 515633; 48 49/** 50 * struct variant_data - MMCI variant-specific quirks 51 * @clkreg: default value for MCICLOCK register 52 * @clkreg_enable: enable value for MMCICLOCK register 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 55 * is asserted (likewise for RX) 56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 57 * is asserted (likewise for RX) 58 * @sdio: variant supports SDIO 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 61 * @pwrreg_powerup: power up value for MMCIPOWER register 62 * @signal_direction: input/out direction of bus signals can be indicated 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 64 */ 65struct variant_data { 66 unsigned int clkreg; 67 unsigned int clkreg_enable; 68 unsigned int datalength_bits; 69 unsigned int fifosize; 70 unsigned int fifohalfsize; 71 bool sdio; 72 bool st_clkdiv; 73 bool blksz_datactrl16; 74 u32 pwrreg_powerup; 75 bool signal_direction; 76 bool pwrreg_clkgate; 77}; 78 79static struct variant_data variant_arm = { 80 .fifosize = 16 * 4, 81 .fifohalfsize = 8 * 4, 82 .datalength_bits = 16, 83 .pwrreg_powerup = MCI_PWR_UP, 84}; 85 86static struct variant_data variant_arm_extended_fifo = { 87 .fifosize = 128 * 4, 88 .fifohalfsize = 64 * 4, 89 .datalength_bits = 16, 90 .pwrreg_powerup = MCI_PWR_UP, 91}; 92 93static struct variant_data variant_arm_extended_fifo_hwfc = { 94 .fifosize = 128 * 4, 95 .fifohalfsize = 64 * 4, 96 .clkreg_enable = MCI_ARM_HWFCEN, 97 .datalength_bits = 16, 98 .pwrreg_powerup = MCI_PWR_UP, 99}; 100 101static struct variant_data variant_u300 = { 102 .fifosize = 16 * 4, 103 .fifohalfsize = 8 * 4, 104 .clkreg_enable = MCI_ST_U300_HWFCEN, 105 .datalength_bits = 16, 106 .sdio = true, 107 .pwrreg_powerup = MCI_PWR_ON, 108 .signal_direction = true, 109 .pwrreg_clkgate = true, 110}; 111 112static struct variant_data variant_nomadik = { 113 .fifosize = 16 * 4, 114 .fifohalfsize = 8 * 4, 115 .clkreg = MCI_CLK_ENABLE, 116 .datalength_bits = 24, 117 .sdio = true, 118 .st_clkdiv = true, 119 .pwrreg_powerup = MCI_PWR_ON, 120 .signal_direction = true, 121 .pwrreg_clkgate = true, 122}; 123 124static struct variant_data variant_ux500 = { 125 .fifosize = 30 * 4, 126 .fifohalfsize = 8 * 4, 127 .clkreg = MCI_CLK_ENABLE, 128 .clkreg_enable = MCI_ST_UX500_HWFCEN, 129 .datalength_bits = 24, 130 .sdio = true, 131 .st_clkdiv = true, 132 .pwrreg_powerup = MCI_PWR_ON, 133 .signal_direction = true, 134 .pwrreg_clkgate = true, 135}; 136 137static struct variant_data variant_ux500v2 = { 138 .fifosize = 30 * 4, 139 .fifohalfsize = 8 * 4, 140 .clkreg = MCI_CLK_ENABLE, 141 .clkreg_enable = MCI_ST_UX500_HWFCEN, 142 .datalength_bits = 24, 143 .sdio = true, 144 .st_clkdiv = true, 145 .blksz_datactrl16 = true, 146 .pwrreg_powerup = MCI_PWR_ON, 147 .signal_direction = true, 148 .pwrreg_clkgate = true, 149}; 150 151/* 152 * Validate mmc prerequisites 153 */ 154static int mmci_validate_data(struct mmci_host *host, 155 struct mmc_data *data) 156{ 157 if (!data) 158 return 0; 159 160 if (!is_power_of_2(data->blksz)) { 161 dev_err(mmc_dev(host->mmc), 162 "unsupported block size (%d bytes)\n", data->blksz); 163 return -EINVAL; 164 } 165 166 return 0; 167} 168 169/* 170 * This must be called with host->lock held 171 */ 172static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 173{ 174 if (host->clk_reg != clk) { 175 host->clk_reg = clk; 176 writel(clk, host->base + MMCICLOCK); 177 } 178} 179 180/* 181 * This must be called with host->lock held 182 */ 183static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 184{ 185 if (host->pwr_reg != pwr) { 186 host->pwr_reg = pwr; 187 writel(pwr, host->base + MMCIPOWER); 188 } 189} 190 191/* 192 * This must be called with host->lock held 193 */ 194static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 195{ 196 if (host->datactrl_reg != datactrl) { 197 host->datactrl_reg = datactrl; 198 writel(datactrl, host->base + MMCIDATACTRL); 199 } 200} 201 202/* 203 * This must be called with host->lock held 204 */ 205static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 206{ 207 struct variant_data *variant = host->variant; 208 u32 clk = variant->clkreg; 209 210 /* Make sure cclk reflects the current calculated clock */ 211 host->cclk = 0; 212 213 if (desired) { 214 if (desired >= host->mclk) { 215 clk = MCI_CLK_BYPASS; 216 if (variant->st_clkdiv) 217 clk |= MCI_ST_UX500_NEG_EDGE; 218 host->cclk = host->mclk; 219 } else if (variant->st_clkdiv) { 220 /* 221 * DB8500 TRM says f = mclk / (clkdiv + 2) 222 * => clkdiv = (mclk / f) - 2 223 * Round the divider up so we don't exceed the max 224 * frequency 225 */ 226 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 227 if (clk >= 256) 228 clk = 255; 229 host->cclk = host->mclk / (clk + 2); 230 } else { 231 /* 232 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 233 * => clkdiv = mclk / (2 * f) - 1 234 */ 235 clk = host->mclk / (2 * desired) - 1; 236 if (clk >= 256) 237 clk = 255; 238 host->cclk = host->mclk / (2 * (clk + 1)); 239 } 240 241 clk |= variant->clkreg_enable; 242 clk |= MCI_CLK_ENABLE; 243 /* This hasn't proven to be worthwhile */ 244 /* clk |= MCI_CLK_PWRSAVE; */ 245 } 246 247 /* Set actual clock for debug */ 248 host->mmc->actual_clock = host->cclk; 249 250 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 251 clk |= MCI_4BIT_BUS; 252 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 253 clk |= MCI_ST_8BIT_BUS; 254 255 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 256 clk |= MCI_ST_UX500_NEG_EDGE; 257 258 mmci_write_clkreg(host, clk); 259} 260 261static void 262mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 263{ 264 writel(0, host->base + MMCICOMMAND); 265 266 BUG_ON(host->data); 267 268 host->mrq = NULL; 269 host->cmd = NULL; 270 271 mmc_request_done(host->mmc, mrq); 272 273 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 274 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 275} 276 277static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 278{ 279 void __iomem *base = host->base; 280 281 if (host->singleirq) { 282 unsigned int mask0 = readl(base + MMCIMASK0); 283 284 mask0 &= ~MCI_IRQ1MASK; 285 mask0 |= mask; 286 287 writel(mask0, base + MMCIMASK0); 288 } 289 290 writel(mask, base + MMCIMASK1); 291} 292 293static void mmci_stop_data(struct mmci_host *host) 294{ 295 mmci_write_datactrlreg(host, 0); 296 mmci_set_mask1(host, 0); 297 host->data = NULL; 298} 299 300static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 301{ 302 unsigned int flags = SG_MITER_ATOMIC; 303 304 if (data->flags & MMC_DATA_READ) 305 flags |= SG_MITER_TO_SG; 306 else 307 flags |= SG_MITER_FROM_SG; 308 309 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 310} 311 312/* 313 * All the DMA operation mode stuff goes inside this ifdef. 314 * This assumes that you have a generic DMA device interface, 315 * no custom DMA interfaces are supported. 316 */ 317#ifdef CONFIG_DMA_ENGINE 318static void mmci_dma_setup(struct mmci_host *host) 319{ 320 struct mmci_platform_data *plat = host->plat; 321 const char *rxname, *txname; 322 dma_cap_mask_t mask; 323 324 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 325 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 326 327 /* initialize pre request cookie */ 328 host->next_data.cookie = 1; 329 330 /* Try to acquire a generic DMA engine slave channel */ 331 dma_cap_zero(mask); 332 dma_cap_set(DMA_SLAVE, mask); 333 334 if (plat && plat->dma_filter) { 335 if (!host->dma_rx_channel && plat->dma_rx_param) { 336 host->dma_rx_channel = dma_request_channel(mask, 337 plat->dma_filter, 338 plat->dma_rx_param); 339 /* E.g if no DMA hardware is present */ 340 if (!host->dma_rx_channel) 341 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 342 } 343 344 if (!host->dma_tx_channel && plat->dma_tx_param) { 345 host->dma_tx_channel = dma_request_channel(mask, 346 plat->dma_filter, 347 plat->dma_tx_param); 348 if (!host->dma_tx_channel) 349 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 350 } 351 } 352 353 /* 354 * If only an RX channel is specified, the driver will 355 * attempt to use it bidirectionally, however if it is 356 * is specified but cannot be located, DMA will be disabled. 357 */ 358 if (host->dma_rx_channel && !host->dma_tx_channel) 359 host->dma_tx_channel = host->dma_rx_channel; 360 361 if (host->dma_rx_channel) 362 rxname = dma_chan_name(host->dma_rx_channel); 363 else 364 rxname = "none"; 365 366 if (host->dma_tx_channel) 367 txname = dma_chan_name(host->dma_tx_channel); 368 else 369 txname = "none"; 370 371 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 372 rxname, txname); 373 374 /* 375 * Limit the maximum segment size in any SG entry according to 376 * the parameters of the DMA engine device. 377 */ 378 if (host->dma_tx_channel) { 379 struct device *dev = host->dma_tx_channel->device->dev; 380 unsigned int max_seg_size = dma_get_max_seg_size(dev); 381 382 if (max_seg_size < host->mmc->max_seg_size) 383 host->mmc->max_seg_size = max_seg_size; 384 } 385 if (host->dma_rx_channel) { 386 struct device *dev = host->dma_rx_channel->device->dev; 387 unsigned int max_seg_size = dma_get_max_seg_size(dev); 388 389 if (max_seg_size < host->mmc->max_seg_size) 390 host->mmc->max_seg_size = max_seg_size; 391 } 392} 393 394/* 395 * This is used in or so inline it 396 * so it can be discarded. 397 */ 398static inline void mmci_dma_release(struct mmci_host *host) 399{ 400 struct mmci_platform_data *plat = host->plat; 401 402 if (host->dma_rx_channel) 403 dma_release_channel(host->dma_rx_channel); 404 if (host->dma_tx_channel && plat->dma_tx_param) 405 dma_release_channel(host->dma_tx_channel); 406 host->dma_rx_channel = host->dma_tx_channel = NULL; 407} 408 409static void mmci_dma_data_error(struct mmci_host *host) 410{ 411 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 412 dmaengine_terminate_all(host->dma_current); 413 host->dma_current = NULL; 414 host->dma_desc_current = NULL; 415 host->data->host_cookie = 0; 416} 417 418static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 419{ 420 struct dma_chan *chan; 421 enum dma_data_direction dir; 422 423 if (data->flags & MMC_DATA_READ) { 424 dir = DMA_FROM_DEVICE; 425 chan = host->dma_rx_channel; 426 } else { 427 dir = DMA_TO_DEVICE; 428 chan = host->dma_tx_channel; 429 } 430 431 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 432} 433 434static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 435{ 436 u32 status; 437 int i; 438 439 /* Wait up to 1ms for the DMA to complete */ 440 for (i = 0; ; i++) { 441 status = readl(host->base + MMCISTATUS); 442 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 443 break; 444 udelay(10); 445 } 446 447 /* 448 * Check to see whether we still have some data left in the FIFO - 449 * this catches DMA controllers which are unable to monitor the 450 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 451 * contiguous buffers. On TX, we'll get a FIFO underrun error. 452 */ 453 if (status & MCI_RXDATAAVLBLMASK) { 454 mmci_dma_data_error(host); 455 if (!data->error) 456 data->error = -EIO; 457 } 458 459 if (!data->host_cookie) 460 mmci_dma_unmap(host, data); 461 462 /* 463 * Use of DMA with scatter-gather is impossible. 464 * Give up with DMA and switch back to PIO mode. 465 */ 466 if (status & MCI_RXDATAAVLBLMASK) { 467 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 468 mmci_dma_release(host); 469 } 470 471 host->dma_current = NULL; 472 host->dma_desc_current = NULL; 473} 474 475/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 476static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 477 struct dma_chan **dma_chan, 478 struct dma_async_tx_descriptor **dma_desc) 479{ 480 struct variant_data *variant = host->variant; 481 struct dma_slave_config conf = { 482 .src_addr = host->phybase + MMCIFIFO, 483 .dst_addr = host->phybase + MMCIFIFO, 484 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 485 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 486 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 487 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 488 .device_fc = false, 489 }; 490 struct dma_chan *chan; 491 struct dma_device *device; 492 struct dma_async_tx_descriptor *desc; 493 enum dma_data_direction buffer_dirn; 494 int nr_sg; 495 496 if (data->flags & MMC_DATA_READ) { 497 conf.direction = DMA_DEV_TO_MEM; 498 buffer_dirn = DMA_FROM_DEVICE; 499 chan = host->dma_rx_channel; 500 } else { 501 conf.direction = DMA_MEM_TO_DEV; 502 buffer_dirn = DMA_TO_DEVICE; 503 chan = host->dma_tx_channel; 504 } 505 506 /* If there's no DMA channel, fall back to PIO */ 507 if (!chan) 508 return -EINVAL; 509 510 /* If less than or equal to the fifo size, don't bother with DMA */ 511 if (data->blksz * data->blocks <= variant->fifosize) 512 return -EINVAL; 513 514 device = chan->device; 515 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 516 if (nr_sg == 0) 517 return -EINVAL; 518 519 dmaengine_slave_config(chan, &conf); 520 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 521 conf.direction, DMA_CTRL_ACK); 522 if (!desc) 523 goto unmap_exit; 524 525 *dma_chan = chan; 526 *dma_desc = desc; 527 528 return 0; 529 530 unmap_exit: 531 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 532 return -ENOMEM; 533} 534 535static inline int mmci_dma_prep_data(struct mmci_host *host, 536 struct mmc_data *data) 537{ 538 /* Check if next job is already prepared. */ 539 if (host->dma_current && host->dma_desc_current) 540 return 0; 541 542 /* No job were prepared thus do it now. */ 543 return __mmci_dma_prep_data(host, data, &host->dma_current, 544 &host->dma_desc_current); 545} 546 547static inline int mmci_dma_prep_next(struct mmci_host *host, 548 struct mmc_data *data) 549{ 550 struct mmci_host_next *nd = &host->next_data; 551 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 552} 553 554static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 555{ 556 int ret; 557 struct mmc_data *data = host->data; 558 559 ret = mmci_dma_prep_data(host, host->data); 560 if (ret) 561 return ret; 562 563 /* Okay, go for it. */ 564 dev_vdbg(mmc_dev(host->mmc), 565 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 566 data->sg_len, data->blksz, data->blocks, data->flags); 567 dmaengine_submit(host->dma_desc_current); 568 dma_async_issue_pending(host->dma_current); 569 570 datactrl |= MCI_DPSM_DMAENABLE; 571 572 /* Trigger the DMA transfer */ 573 mmci_write_datactrlreg(host, datactrl); 574 575 /* 576 * Let the MMCI say when the data is ended and it's time 577 * to fire next DMA request. When that happens, MMCI will 578 * call mmci_data_end() 579 */ 580 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 581 host->base + MMCIMASK0); 582 return 0; 583} 584 585static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 586{ 587 struct mmci_host_next *next = &host->next_data; 588 589 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 590 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 591 592 host->dma_desc_current = next->dma_desc; 593 host->dma_current = next->dma_chan; 594 next->dma_desc = NULL; 595 next->dma_chan = NULL; 596} 597 598static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 599 bool is_first_req) 600{ 601 struct mmci_host *host = mmc_priv(mmc); 602 struct mmc_data *data = mrq->data; 603 struct mmci_host_next *nd = &host->next_data; 604 605 if (!data) 606 return; 607 608 BUG_ON(data->host_cookie); 609 610 if (mmci_validate_data(host, data)) 611 return; 612 613 if (!mmci_dma_prep_next(host, data)) 614 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 615} 616 617static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 618 int err) 619{ 620 struct mmci_host *host = mmc_priv(mmc); 621 struct mmc_data *data = mrq->data; 622 623 if (!data || !data->host_cookie) 624 return; 625 626 mmci_dma_unmap(host, data); 627 628 if (err) { 629 struct mmci_host_next *next = &host->next_data; 630 struct dma_chan *chan; 631 if (data->flags & MMC_DATA_READ) 632 chan = host->dma_rx_channel; 633 else 634 chan = host->dma_tx_channel; 635 dmaengine_terminate_all(chan); 636 637 next->dma_desc = NULL; 638 next->dma_chan = NULL; 639 } 640} 641 642#else 643/* Blank functions if the DMA engine is not available */ 644static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 645{ 646} 647static inline void mmci_dma_setup(struct mmci_host *host) 648{ 649} 650 651static inline void mmci_dma_release(struct mmci_host *host) 652{ 653} 654 655static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 656{ 657} 658 659static inline void mmci_dma_finalize(struct mmci_host *host, 660 struct mmc_data *data) 661{ 662} 663 664static inline void mmci_dma_data_error(struct mmci_host *host) 665{ 666} 667 668static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 669{ 670 return -ENOSYS; 671} 672 673#define mmci_pre_request NULL 674#define mmci_post_request NULL 675 676#endif 677 678static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 679{ 680 struct variant_data *variant = host->variant; 681 unsigned int datactrl, timeout, irqmask; 682 unsigned long long clks; 683 void __iomem *base; 684 int blksz_bits; 685 686 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 687 data->blksz, data->blocks, data->flags); 688 689 host->data = data; 690 host->size = data->blksz * data->blocks; 691 data->bytes_xfered = 0; 692 693 clks = (unsigned long long)data->timeout_ns * host->cclk; 694 do_div(clks, 1000000000UL); 695 696 timeout = data->timeout_clks + (unsigned int)clks; 697 698 base = host->base; 699 writel(timeout, base + MMCIDATATIMER); 700 writel(host->size, base + MMCIDATALENGTH); 701 702 blksz_bits = ffs(data->blksz) - 1; 703 BUG_ON(1 << blksz_bits != data->blksz); 704 705 if (variant->blksz_datactrl16) 706 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 707 else 708 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 709 710 if (data->flags & MMC_DATA_READ) 711 datactrl |= MCI_DPSM_DIRECTION; 712 713 /* The ST Micro variants has a special bit to enable SDIO */ 714 if (variant->sdio && host->mmc->card) 715 if (mmc_card_sdio(host->mmc->card)) { 716 /* 717 * The ST Micro variants has a special bit 718 * to enable SDIO. 719 */ 720 u32 clk; 721 722 datactrl |= MCI_ST_DPSM_SDIOEN; 723 724 /* 725 * The ST Micro variant for SDIO small write transfers 726 * needs to have clock H/W flow control disabled, 727 * otherwise the transfer will not start. The threshold 728 * depends on the rate of MCLK. 729 */ 730 if (data->flags & MMC_DATA_WRITE && 731 (host->size < 8 || 732 (host->size <= 8 && host->mclk > 50000000))) 733 clk = host->clk_reg & ~variant->clkreg_enable; 734 else 735 clk = host->clk_reg | variant->clkreg_enable; 736 737 mmci_write_clkreg(host, clk); 738 } 739 740 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 741 datactrl |= MCI_ST_DPSM_DDRMODE; 742 743 /* 744 * Attempt to use DMA operation mode, if this 745 * should fail, fall back to PIO mode 746 */ 747 if (!mmci_dma_start_data(host, datactrl)) 748 return; 749 750 /* IRQ mode, map the SG list for CPU reading/writing */ 751 mmci_init_sg(host, data); 752 753 if (data->flags & MMC_DATA_READ) { 754 irqmask = MCI_RXFIFOHALFFULLMASK; 755 756 /* 757 * If we have less than the fifo 'half-full' threshold to 758 * transfer, trigger a PIO interrupt as soon as any data 759 * is available. 760 */ 761 if (host->size < variant->fifohalfsize) 762 irqmask |= MCI_RXDATAAVLBLMASK; 763 } else { 764 /* 765 * We don't actually need to include "FIFO empty" here 766 * since its implicit in "FIFO half empty". 767 */ 768 irqmask = MCI_TXFIFOHALFEMPTYMASK; 769 } 770 771 mmci_write_datactrlreg(host, datactrl); 772 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 773 mmci_set_mask1(host, irqmask); 774} 775 776static void 777mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 778{ 779 void __iomem *base = host->base; 780 781 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 782 cmd->opcode, cmd->arg, cmd->flags); 783 784 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 785 writel(0, base + MMCICOMMAND); 786 udelay(1); 787 } 788 789 c |= cmd->opcode | MCI_CPSM_ENABLE; 790 if (cmd->flags & MMC_RSP_PRESENT) { 791 if (cmd->flags & MMC_RSP_136) 792 c |= MCI_CPSM_LONGRSP; 793 c |= MCI_CPSM_RESPONSE; 794 } 795 if (/*interrupt*/0) 796 c |= MCI_CPSM_INTERRUPT; 797 798 host->cmd = cmd; 799 800 writel(cmd->arg, base + MMCIARGUMENT); 801 writel(c, base + MMCICOMMAND); 802} 803 804static void 805mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 806 unsigned int status) 807{ 808 /* First check for errors */ 809 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 810 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 811 u32 remain, success; 812 813 /* Terminate the DMA transfer */ 814 if (dma_inprogress(host)) { 815 mmci_dma_data_error(host); 816 mmci_dma_unmap(host, data); 817 } 818 819 /* 820 * Calculate how far we are into the transfer. Note that 821 * the data counter gives the number of bytes transferred 822 * on the MMC bus, not on the host side. On reads, this 823 * can be as much as a FIFO-worth of data ahead. This 824 * matters for FIFO overruns only. 825 */ 826 remain = readl(host->base + MMCIDATACNT); 827 success = data->blksz * data->blocks - remain; 828 829 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 830 status, success); 831 if (status & MCI_DATACRCFAIL) { 832 /* Last block was not successful */ 833 success -= 1; 834 data->error = -EILSEQ; 835 } else if (status & MCI_DATATIMEOUT) { 836 data->error = -ETIMEDOUT; 837 } else if (status & MCI_STARTBITERR) { 838 data->error = -ECOMM; 839 } else if (status & MCI_TXUNDERRUN) { 840 data->error = -EIO; 841 } else if (status & MCI_RXOVERRUN) { 842 if (success > host->variant->fifosize) 843 success -= host->variant->fifosize; 844 else 845 success = 0; 846 data->error = -EIO; 847 } 848 data->bytes_xfered = round_down(success, data->blksz); 849 } 850 851 if (status & MCI_DATABLOCKEND) 852 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 853 854 if (status & MCI_DATAEND || data->error) { 855 if (dma_inprogress(host)) 856 mmci_dma_finalize(host, data); 857 mmci_stop_data(host); 858 859 if (!data->error) 860 /* The error clause is handled above, success! */ 861 data->bytes_xfered = data->blksz * data->blocks; 862 863 if (!data->stop || host->mrq->sbc) { 864 mmci_request_end(host, data->mrq); 865 } else { 866 mmci_start_command(host, data->stop, 0); 867 } 868 } 869} 870 871static void 872mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 873 unsigned int status) 874{ 875 void __iomem *base = host->base; 876 bool sbc = (cmd == host->mrq->sbc); 877 878 host->cmd = NULL; 879 880 if (status & MCI_CMDTIMEOUT) { 881 cmd->error = -ETIMEDOUT; 882 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 883 cmd->error = -EILSEQ; 884 } else { 885 cmd->resp[0] = readl(base + MMCIRESPONSE0); 886 cmd->resp[1] = readl(base + MMCIRESPONSE1); 887 cmd->resp[2] = readl(base + MMCIRESPONSE2); 888 cmd->resp[3] = readl(base + MMCIRESPONSE3); 889 } 890 891 if ((!sbc && !cmd->data) || cmd->error) { 892 if (host->data) { 893 /* Terminate the DMA transfer */ 894 if (dma_inprogress(host)) { 895 mmci_dma_data_error(host); 896 mmci_dma_unmap(host, host->data); 897 } 898 mmci_stop_data(host); 899 } 900 mmci_request_end(host, host->mrq); 901 } else if (sbc) { 902 mmci_start_command(host, host->mrq->cmd, 0); 903 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 904 mmci_start_data(host, cmd->data); 905 } 906} 907 908static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 909{ 910 void __iomem *base = host->base; 911 char *ptr = buffer; 912 u32 status; 913 int host_remain = host->size; 914 915 do { 916 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 917 918 if (count > remain) 919 count = remain; 920 921 if (count <= 0) 922 break; 923 924 /* 925 * SDIO especially may want to send something that is 926 * not divisible by 4 (as opposed to card sectors 927 * etc). Therefore make sure to always read the last bytes 928 * while only doing full 32-bit reads towards the FIFO. 929 */ 930 if (unlikely(count & 0x3)) { 931 if (count < 4) { 932 unsigned char buf[4]; 933 ioread32_rep(base + MMCIFIFO, buf, 1); 934 memcpy(ptr, buf, count); 935 } else { 936 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 937 count &= ~0x3; 938 } 939 } else { 940 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 941 } 942 943 ptr += count; 944 remain -= count; 945 host_remain -= count; 946 947 if (remain == 0) 948 break; 949 950 status = readl(base + MMCISTATUS); 951 } while (status & MCI_RXDATAAVLBL); 952 953 return ptr - buffer; 954} 955 956static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 957{ 958 struct variant_data *variant = host->variant; 959 void __iomem *base = host->base; 960 char *ptr = buffer; 961 962 do { 963 unsigned int count, maxcnt; 964 965 maxcnt = status & MCI_TXFIFOEMPTY ? 966 variant->fifosize : variant->fifohalfsize; 967 count = min(remain, maxcnt); 968 969 /* 970 * SDIO especially may want to send something that is 971 * not divisible by 4 (as opposed to card sectors 972 * etc), and the FIFO only accept full 32-bit writes. 973 * So compensate by adding +3 on the count, a single 974 * byte become a 32bit write, 7 bytes will be two 975 * 32bit writes etc. 976 */ 977 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 978 979 ptr += count; 980 remain -= count; 981 982 if (remain == 0) 983 break; 984 985 status = readl(base + MMCISTATUS); 986 } while (status & MCI_TXFIFOHALFEMPTY); 987 988 return ptr - buffer; 989} 990 991/* 992 * PIO data transfer IRQ handler. 993 */ 994static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 995{ 996 struct mmci_host *host = dev_id; 997 struct sg_mapping_iter *sg_miter = &host->sg_miter; 998 struct variant_data *variant = host->variant; 999 void __iomem *base = host->base; 1000 unsigned long flags; 1001 u32 status; 1002 1003 status = readl(base + MMCISTATUS); 1004 1005 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1006 1007 local_irq_save(flags); 1008 1009 do { 1010 unsigned int remain, len; 1011 char *buffer; 1012 1013 /* 1014 * For write, we only need to test the half-empty flag 1015 * here - if the FIFO is completely empty, then by 1016 * definition it is more than half empty. 1017 * 1018 * For read, check for data available. 1019 */ 1020 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1021 break; 1022 1023 if (!sg_miter_next(sg_miter)) 1024 break; 1025 1026 buffer = sg_miter->addr; 1027 remain = sg_miter->length; 1028 1029 len = 0; 1030 if (status & MCI_RXACTIVE) 1031 len = mmci_pio_read(host, buffer, remain); 1032 if (status & MCI_TXACTIVE) 1033 len = mmci_pio_write(host, buffer, remain, status); 1034 1035 sg_miter->consumed = len; 1036 1037 host->size -= len; 1038 remain -= len; 1039 1040 if (remain) 1041 break; 1042 1043 status = readl(base + MMCISTATUS); 1044 } while (1); 1045 1046 sg_miter_stop(sg_miter); 1047 1048 local_irq_restore(flags); 1049 1050 /* 1051 * If we have less than the fifo 'half-full' threshold to transfer, 1052 * trigger a PIO interrupt as soon as any data is available. 1053 */ 1054 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1055 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1056 1057 /* 1058 * If we run out of data, disable the data IRQs; this 1059 * prevents a race where the FIFO becomes empty before 1060 * the chip itself has disabled the data path, and 1061 * stops us racing with our data end IRQ. 1062 */ 1063 if (host->size == 0) { 1064 mmci_set_mask1(host, 0); 1065 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1066 } 1067 1068 return IRQ_HANDLED; 1069} 1070 1071/* 1072 * Handle completion of command and data transfers. 1073 */ 1074static irqreturn_t mmci_irq(int irq, void *dev_id) 1075{ 1076 struct mmci_host *host = dev_id; 1077 u32 status; 1078 int ret = 0; 1079 1080 spin_lock(&host->lock); 1081 1082 do { 1083 struct mmc_command *cmd; 1084 struct mmc_data *data; 1085 1086 status = readl(host->base + MMCISTATUS); 1087 1088 if (host->singleirq) { 1089 if (status & readl(host->base + MMCIMASK1)) 1090 mmci_pio_irq(irq, dev_id); 1091 1092 status &= ~MCI_IRQ1MASK; 1093 } 1094 1095 status &= readl(host->base + MMCIMASK0); 1096 writel(status, host->base + MMCICLEAR); 1097 1098 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1099 1100 data = host->data; 1101 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1102 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1103 MCI_DATABLOCKEND) && data) 1104 mmci_data_irq(host, data, status); 1105 1106 cmd = host->cmd; 1107 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1108 mmci_cmd_irq(host, cmd, status); 1109 1110 ret = 1; 1111 } while (status); 1112 1113 spin_unlock(&host->lock); 1114 1115 return IRQ_RETVAL(ret); 1116} 1117 1118static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1119{ 1120 struct mmci_host *host = mmc_priv(mmc); 1121 unsigned long flags; 1122 1123 WARN_ON(host->mrq != NULL); 1124 1125 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1126 if (mrq->cmd->error) { 1127 mmc_request_done(mmc, mrq); 1128 return; 1129 } 1130 1131 pm_runtime_get_sync(mmc_dev(mmc)); 1132 1133 spin_lock_irqsave(&host->lock, flags); 1134 1135 host->mrq = mrq; 1136 1137 if (mrq->data) 1138 mmci_get_next_data(host, mrq->data); 1139 1140 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1141 mmci_start_data(host, mrq->data); 1142 1143 if (mrq->sbc) 1144 mmci_start_command(host, mrq->sbc, 0); 1145 else 1146 mmci_start_command(host, mrq->cmd, 0); 1147 1148 spin_unlock_irqrestore(&host->lock, flags); 1149} 1150 1151static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1152{ 1153 struct mmci_host *host = mmc_priv(mmc); 1154 struct variant_data *variant = host->variant; 1155 u32 pwr = 0; 1156 unsigned long flags; 1157 int ret; 1158 1159 pm_runtime_get_sync(mmc_dev(mmc)); 1160 1161 if (host->plat->ios_handler && 1162 host->plat->ios_handler(mmc_dev(mmc), ios)) 1163 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1164 1165 switch (ios->power_mode) { 1166 case MMC_POWER_OFF: 1167 if (!IS_ERR(mmc->supply.vmmc)) 1168 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1169 1170 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1171 regulator_disable(mmc->supply.vqmmc); 1172 host->vqmmc_enabled = false; 1173 } 1174 1175 break; 1176 case MMC_POWER_UP: 1177 if (!IS_ERR(mmc->supply.vmmc)) 1178 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1179 1180 /* 1181 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1182 * and instead uses MCI_PWR_ON so apply whatever value is 1183 * configured in the variant data. 1184 */ 1185 pwr |= variant->pwrreg_powerup; 1186 1187 break; 1188 case MMC_POWER_ON: 1189 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1190 ret = regulator_enable(mmc->supply.vqmmc); 1191 if (ret < 0) 1192 dev_err(mmc_dev(mmc), 1193 "failed to enable vqmmc regulator\n"); 1194 else 1195 host->vqmmc_enabled = true; 1196 } 1197 1198 pwr |= MCI_PWR_ON; 1199 break; 1200 } 1201 1202 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1203 /* 1204 * The ST Micro variant has some additional bits 1205 * indicating signal direction for the signals in 1206 * the SD/MMC bus and feedback-clock usage. 1207 */ 1208 pwr |= host->plat->sigdir; 1209 1210 if (ios->bus_width == MMC_BUS_WIDTH_4) 1211 pwr &= ~MCI_ST_DATA74DIREN; 1212 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1213 pwr &= (~MCI_ST_DATA74DIREN & 1214 ~MCI_ST_DATA31DIREN & 1215 ~MCI_ST_DATA2DIREN); 1216 } 1217 1218 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1219 if (host->hw_designer != AMBA_VENDOR_ST) 1220 pwr |= MCI_ROD; 1221 else { 1222 /* 1223 * The ST Micro variant use the ROD bit for something 1224 * else and only has OD (Open Drain). 1225 */ 1226 pwr |= MCI_OD; 1227 } 1228 } 1229 1230 /* 1231 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1232 * gating the clock, the MCI_PWR_ON bit is cleared. 1233 */ 1234 if (!ios->clock && variant->pwrreg_clkgate) 1235 pwr &= ~MCI_PWR_ON; 1236 1237 spin_lock_irqsave(&host->lock, flags); 1238 1239 mmci_set_clkreg(host, ios->clock); 1240 mmci_write_pwrreg(host, pwr); 1241 1242 spin_unlock_irqrestore(&host->lock, flags); 1243 1244 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1245 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1246} 1247 1248static int mmci_get_ro(struct mmc_host *mmc) 1249{ 1250 struct mmci_host *host = mmc_priv(mmc); 1251 1252 if (host->gpio_wp == -ENOSYS) 1253 return -ENOSYS; 1254 1255 return gpio_get_value_cansleep(host->gpio_wp); 1256} 1257 1258static int mmci_get_cd(struct mmc_host *mmc) 1259{ 1260 struct mmci_host *host = mmc_priv(mmc); 1261 struct mmci_platform_data *plat = host->plat; 1262 unsigned int status; 1263 1264 if (host->gpio_cd == -ENOSYS) { 1265 if (!plat->status) 1266 return 1; /* Assume always present */ 1267 1268 status = plat->status(mmc_dev(host->mmc)); 1269 } else 1270 status = !!gpio_get_value_cansleep(host->gpio_cd) 1271 ^ plat->cd_invert; 1272 1273 /* 1274 * Use positive logic throughout - status is zero for no card, 1275 * non-zero for card inserted. 1276 */ 1277 return status; 1278} 1279 1280static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1281{ 1282 int ret = 0; 1283 1284 if (!IS_ERR(mmc->supply.vqmmc)) { 1285 1286 pm_runtime_get_sync(mmc_dev(mmc)); 1287 1288 switch (ios->signal_voltage) { 1289 case MMC_SIGNAL_VOLTAGE_330: 1290 ret = regulator_set_voltage(mmc->supply.vqmmc, 1291 2700000, 3600000); 1292 break; 1293 case MMC_SIGNAL_VOLTAGE_180: 1294 ret = regulator_set_voltage(mmc->supply.vqmmc, 1295 1700000, 1950000); 1296 break; 1297 case MMC_SIGNAL_VOLTAGE_120: 1298 ret = regulator_set_voltage(mmc->supply.vqmmc, 1299 1100000, 1300000); 1300 break; 1301 } 1302 1303 if (ret) 1304 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1305 1306 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1307 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1308 } 1309 1310 return ret; 1311} 1312 1313static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1314{ 1315 struct mmci_host *host = dev_id; 1316 1317 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1318 1319 return IRQ_HANDLED; 1320} 1321 1322static const struct mmc_host_ops mmci_ops = { 1323 .request = mmci_request, 1324 .pre_req = mmci_pre_request, 1325 .post_req = mmci_post_request, 1326 .set_ios = mmci_set_ios, 1327 .get_ro = mmci_get_ro, 1328 .get_cd = mmci_get_cd, 1329 .start_signal_voltage_switch = mmci_sig_volt_switch, 1330}; 1331 1332#ifdef CONFIG_OF 1333static void mmci_dt_populate_generic_pdata(struct device_node *np, 1334 struct mmci_platform_data *pdata) 1335{ 1336 int bus_width = 0; 1337 1338 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1339 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1340 1341 if (of_get_property(np, "cd-inverted", NULL)) 1342 pdata->cd_invert = true; 1343 else 1344 pdata->cd_invert = false; 1345 1346 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1347 if (!pdata->f_max) 1348 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1349 1350 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1351 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1352 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1353 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1354 1355 of_property_read_u32(np, "bus-width", &bus_width); 1356 switch (bus_width) { 1357 case 0 : 1358 /* No bus-width supplied. */ 1359 break; 1360 case 4 : 1361 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1362 break; 1363 case 8 : 1364 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1365 break; 1366 default : 1367 pr_warn("%s: Unsupported bus width\n", np->full_name); 1368 } 1369} 1370#else 1371static void mmci_dt_populate_generic_pdata(struct device_node *np, 1372 struct mmci_platform_data *pdata) 1373{ 1374 return; 1375} 1376#endif 1377 1378static int mmci_probe(struct amba_device *dev, 1379 const struct amba_id *id) 1380{ 1381 struct mmci_platform_data *plat = dev->dev.platform_data; 1382 struct device_node *np = dev->dev.of_node; 1383 struct variant_data *variant = id->data; 1384 struct mmci_host *host; 1385 struct mmc_host *mmc; 1386 int ret; 1387 1388 /* Must have platform data or Device Tree. */ 1389 if (!plat && !np) { 1390 dev_err(&dev->dev, "No plat data or DT found\n"); 1391 return -EINVAL; 1392 } 1393 1394 if (!plat) { 1395 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1396 if (!plat) 1397 return -ENOMEM; 1398 } 1399 1400 if (np) 1401 mmci_dt_populate_generic_pdata(np, plat); 1402 1403 ret = amba_request_regions(dev, DRIVER_NAME); 1404 if (ret) 1405 goto out; 1406 1407 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1408 if (!mmc) { 1409 ret = -ENOMEM; 1410 goto rel_regions; 1411 } 1412 1413 host = mmc_priv(mmc); 1414 host->mmc = mmc; 1415 1416 host->gpio_wp = -ENOSYS; 1417 host->gpio_cd = -ENOSYS; 1418 host->gpio_cd_irq = -1; 1419 1420 host->hw_designer = amba_manf(dev); 1421 host->hw_revision = amba_rev(dev); 1422 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1423 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1424 1425 host->clk = devm_clk_get(&dev->dev, NULL); 1426 if (IS_ERR(host->clk)) { 1427 ret = PTR_ERR(host->clk); 1428 goto host_free; 1429 } 1430 1431 ret = clk_prepare_enable(host->clk); 1432 if (ret) 1433 goto host_free; 1434 1435 host->plat = plat; 1436 host->variant = variant; 1437 host->mclk = clk_get_rate(host->clk); 1438 /* 1439 * According to the spec, mclk is max 100 MHz, 1440 * so we try to adjust the clock down to this, 1441 * (if possible). 1442 */ 1443 if (host->mclk > 100000000) { 1444 ret = clk_set_rate(host->clk, 100000000); 1445 if (ret < 0) 1446 goto clk_disable; 1447 host->mclk = clk_get_rate(host->clk); 1448 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1449 host->mclk); 1450 } 1451 host->phybase = dev->res.start; 1452 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1453 if (!host->base) { 1454 ret = -ENOMEM; 1455 goto clk_disable; 1456 } 1457 1458 mmc->ops = &mmci_ops; 1459 /* 1460 * The ARM and ST versions of the block have slightly different 1461 * clock divider equations which means that the minimum divider 1462 * differs too. 1463 */ 1464 if (variant->st_clkdiv) 1465 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1466 else 1467 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1468 /* 1469 * If the platform data supplies a maximum operating 1470 * frequency, this takes precedence. Else, we fall back 1471 * to using the module parameter, which has a (low) 1472 * default value in case it is not specified. Either 1473 * value must not exceed the clock rate into the block, 1474 * of course. 1475 */ 1476 if (plat->f_max) 1477 mmc->f_max = min(host->mclk, plat->f_max); 1478 else 1479 mmc->f_max = min(host->mclk, fmax); 1480 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1481 1482 host->pinctrl = devm_pinctrl_get(&dev->dev); 1483 if (IS_ERR(host->pinctrl)) { 1484 ret = PTR_ERR(host->pinctrl); 1485 goto clk_disable; 1486 } 1487 1488 host->pins_default = pinctrl_lookup_state(host->pinctrl, 1489 PINCTRL_STATE_DEFAULT); 1490 1491 /* enable pins to be muxed in and configured */ 1492 if (!IS_ERR(host->pins_default)) { 1493 ret = pinctrl_select_state(host->pinctrl, host->pins_default); 1494 if (ret) 1495 dev_warn(&dev->dev, "could not set default pins\n"); 1496 } else 1497 dev_warn(&dev->dev, "could not get default pinstate\n"); 1498 1499 /* Get regulators and the supported OCR mask */ 1500 mmc_regulator_get_supply(mmc); 1501 if (!mmc->ocr_avail) 1502 mmc->ocr_avail = plat->ocr_mask; 1503 else if (plat->ocr_mask) 1504 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1505 1506 mmc->caps = plat->capabilities; 1507 mmc->caps2 = plat->capabilities2; 1508 1509 /* We support these PM capabilities. */ 1510 mmc->pm_caps = MMC_PM_KEEP_POWER; 1511 1512 /* 1513 * We can do SGIO 1514 */ 1515 mmc->max_segs = NR_SG; 1516 1517 /* 1518 * Since only a certain number of bits are valid in the data length 1519 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1520 * single request. 1521 */ 1522 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1523 1524 /* 1525 * Set the maximum segment size. Since we aren't doing DMA 1526 * (yet) we are only limited by the data length register. 1527 */ 1528 mmc->max_seg_size = mmc->max_req_size; 1529 1530 /* 1531 * Block size can be up to 2048 bytes, but must be a power of two. 1532 */ 1533 mmc->max_blk_size = 1 << 11; 1534 1535 /* 1536 * Limit the number of blocks transferred so that we don't overflow 1537 * the maximum request size. 1538 */ 1539 mmc->max_blk_count = mmc->max_req_size >> 11; 1540 1541 spin_lock_init(&host->lock); 1542 1543 writel(0, host->base + MMCIMASK0); 1544 writel(0, host->base + MMCIMASK1); 1545 writel(0xfff, host->base + MMCICLEAR); 1546 1547 if (plat->gpio_cd == -EPROBE_DEFER) { 1548 ret = -EPROBE_DEFER; 1549 goto err_gpio_cd; 1550 } 1551 if (gpio_is_valid(plat->gpio_cd)) { 1552 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1553 if (ret == 0) 1554 ret = gpio_direction_input(plat->gpio_cd); 1555 if (ret == 0) 1556 host->gpio_cd = plat->gpio_cd; 1557 else if (ret != -ENOSYS) 1558 goto err_gpio_cd; 1559 1560 /* 1561 * A gpio pin that will detect cards when inserted and removed 1562 * will most likely want to trigger on the edges if it is 1563 * 0 when ejected and 1 when inserted (or mutatis mutandis 1564 * for the inverted case) so we request triggers on both 1565 * edges. 1566 */ 1567 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1568 mmci_cd_irq, 1569 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1570 DRIVER_NAME " (cd)", host); 1571 if (ret >= 0) 1572 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1573 } 1574 if (plat->gpio_wp == -EPROBE_DEFER) { 1575 ret = -EPROBE_DEFER; 1576 goto err_gpio_wp; 1577 } 1578 if (gpio_is_valid(plat->gpio_wp)) { 1579 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1580 if (ret == 0) 1581 ret = gpio_direction_input(plat->gpio_wp); 1582 if (ret == 0) 1583 host->gpio_wp = plat->gpio_wp; 1584 else if (ret != -ENOSYS) 1585 goto err_gpio_wp; 1586 } 1587 1588 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1589 && host->gpio_cd_irq < 0) 1590 mmc->caps |= MMC_CAP_NEEDS_POLL; 1591 1592 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1593 if (ret) 1594 goto unmap; 1595 1596 if (!dev->irq[1]) 1597 host->singleirq = true; 1598 else { 1599 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1600 DRIVER_NAME " (pio)", host); 1601 if (ret) 1602 goto irq0_free; 1603 } 1604 1605 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1606 1607 amba_set_drvdata(dev, mmc); 1608 1609 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1610 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1611 amba_rev(dev), (unsigned long long)dev->res.start, 1612 dev->irq[0], dev->irq[1]); 1613 1614 mmci_dma_setup(host); 1615 1616 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1617 pm_runtime_use_autosuspend(&dev->dev); 1618 pm_runtime_put(&dev->dev); 1619 1620 mmc_add_host(mmc); 1621 1622 return 0; 1623 1624 irq0_free: 1625 free_irq(dev->irq[0], host); 1626 unmap: 1627 if (host->gpio_wp != -ENOSYS) 1628 gpio_free(host->gpio_wp); 1629 err_gpio_wp: 1630 if (host->gpio_cd_irq >= 0) 1631 free_irq(host->gpio_cd_irq, host); 1632 if (host->gpio_cd != -ENOSYS) 1633 gpio_free(host->gpio_cd); 1634 err_gpio_cd: 1635 iounmap(host->base); 1636 clk_disable: 1637 clk_disable_unprepare(host->clk); 1638 host_free: 1639 mmc_free_host(mmc); 1640 rel_regions: 1641 amba_release_regions(dev); 1642 out: 1643 return ret; 1644} 1645 1646static int mmci_remove(struct amba_device *dev) 1647{ 1648 struct mmc_host *mmc = amba_get_drvdata(dev); 1649 1650 amba_set_drvdata(dev, NULL); 1651 1652 if (mmc) { 1653 struct mmci_host *host = mmc_priv(mmc); 1654 1655 /* 1656 * Undo pm_runtime_put() in probe. We use the _sync 1657 * version here so that we can access the primecell. 1658 */ 1659 pm_runtime_get_sync(&dev->dev); 1660 1661 mmc_remove_host(mmc); 1662 1663 writel(0, host->base + MMCIMASK0); 1664 writel(0, host->base + MMCIMASK1); 1665 1666 writel(0, host->base + MMCICOMMAND); 1667 writel(0, host->base + MMCIDATACTRL); 1668 1669 mmci_dma_release(host); 1670 free_irq(dev->irq[0], host); 1671 if (!host->singleirq) 1672 free_irq(dev->irq[1], host); 1673 1674 if (host->gpio_wp != -ENOSYS) 1675 gpio_free(host->gpio_wp); 1676 if (host->gpio_cd_irq >= 0) 1677 free_irq(host->gpio_cd_irq, host); 1678 if (host->gpio_cd != -ENOSYS) 1679 gpio_free(host->gpio_cd); 1680 1681 iounmap(host->base); 1682 clk_disable_unprepare(host->clk); 1683 1684 mmc_free_host(mmc); 1685 1686 amba_release_regions(dev); 1687 } 1688 1689 return 0; 1690} 1691 1692#ifdef CONFIG_SUSPEND 1693static int mmci_suspend(struct device *dev) 1694{ 1695 struct amba_device *adev = to_amba_device(dev); 1696 struct mmc_host *mmc = amba_get_drvdata(adev); 1697 int ret = 0; 1698 1699 if (mmc) { 1700 struct mmci_host *host = mmc_priv(mmc); 1701 1702 ret = mmc_suspend_host(mmc); 1703 if (ret == 0) { 1704 pm_runtime_get_sync(dev); 1705 writel(0, host->base + MMCIMASK0); 1706 } 1707 } 1708 1709 return ret; 1710} 1711 1712static int mmci_resume(struct device *dev) 1713{ 1714 struct amba_device *adev = to_amba_device(dev); 1715 struct mmc_host *mmc = amba_get_drvdata(adev); 1716 int ret = 0; 1717 1718 if (mmc) { 1719 struct mmci_host *host = mmc_priv(mmc); 1720 1721 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1722 pm_runtime_put(dev); 1723 1724 ret = mmc_resume_host(mmc); 1725 } 1726 1727 return ret; 1728} 1729#endif 1730 1731#ifdef CONFIG_PM_RUNTIME 1732static int mmci_runtime_suspend(struct device *dev) 1733{ 1734 struct amba_device *adev = to_amba_device(dev); 1735 struct mmc_host *mmc = amba_get_drvdata(adev); 1736 1737 if (mmc) { 1738 struct mmci_host *host = mmc_priv(mmc); 1739 clk_disable_unprepare(host->clk); 1740 } 1741 1742 return 0; 1743} 1744 1745static int mmci_runtime_resume(struct device *dev) 1746{ 1747 struct amba_device *adev = to_amba_device(dev); 1748 struct mmc_host *mmc = amba_get_drvdata(adev); 1749 1750 if (mmc) { 1751 struct mmci_host *host = mmc_priv(mmc); 1752 clk_prepare_enable(host->clk); 1753 } 1754 1755 return 0; 1756} 1757#endif 1758 1759static const struct dev_pm_ops mmci_dev_pm_ops = { 1760 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1761 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1762}; 1763 1764static struct amba_id mmci_ids[] = { 1765 { 1766 .id = 0x00041180, 1767 .mask = 0xff0fffff, 1768 .data = &variant_arm, 1769 }, 1770 { 1771 .id = 0x01041180, 1772 .mask = 0xff0fffff, 1773 .data = &variant_arm_extended_fifo, 1774 }, 1775 { 1776 .id = 0x02041180, 1777 .mask = 0xff0fffff, 1778 .data = &variant_arm_extended_fifo_hwfc, 1779 }, 1780 { 1781 .id = 0x00041181, 1782 .mask = 0x000fffff, 1783 .data = &variant_arm, 1784 }, 1785 /* ST Micro variants */ 1786 { 1787 .id = 0x00180180, 1788 .mask = 0x00ffffff, 1789 .data = &variant_u300, 1790 }, 1791 { 1792 .id = 0x10180180, 1793 .mask = 0xf0ffffff, 1794 .data = &variant_nomadik, 1795 }, 1796 { 1797 .id = 0x00280180, 1798 .mask = 0x00ffffff, 1799 .data = &variant_u300, 1800 }, 1801 { 1802 .id = 0x00480180, 1803 .mask = 0xf0ffffff, 1804 .data = &variant_ux500, 1805 }, 1806 { 1807 .id = 0x10480180, 1808 .mask = 0xf0ffffff, 1809 .data = &variant_ux500v2, 1810 }, 1811 { 0, 0 }, 1812}; 1813 1814MODULE_DEVICE_TABLE(amba, mmci_ids); 1815 1816static struct amba_driver mmci_driver = { 1817 .drv = { 1818 .name = DRIVER_NAME, 1819 .pm = &mmci_dev_pm_ops, 1820 }, 1821 .probe = mmci_probe, 1822 .remove = mmci_remove, 1823 .id_table = mmci_ids, 1824}; 1825 1826module_amba_driver(mmci_driver); 1827 1828module_param(fmax, uint, 0444); 1829 1830MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1831MODULE_LICENSE("GPL"); 1832