mmci.c revision ae7b0061f61e7c96884f4080b4e28544a0cedd76
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/io.h> 17#include <linux/interrupt.h> 18#include <linux/kernel.h> 19#include <linux/slab.h> 20#include <linux/delay.h> 21#include <linux/err.h> 22#include <linux/highmem.h> 23#include <linux/log2.h> 24#include <linux/mmc/pm.h> 25#include <linux/mmc/host.h> 26#include <linux/mmc/card.h> 27#include <linux/mmc/slot-gpio.h> 28#include <linux/amba/bus.h> 29#include <linux/clk.h> 30#include <linux/scatterlist.h> 31#include <linux/gpio.h> 32#include <linux/of_gpio.h> 33#include <linux/regulator/consumer.h> 34#include <linux/dmaengine.h> 35#include <linux/dma-mapping.h> 36#include <linux/amba/mmci.h> 37#include <linux/pm_runtime.h> 38#include <linux/types.h> 39#include <linux/pinctrl/consumer.h> 40 41#include <asm/div64.h> 42#include <asm/io.h> 43#include <asm/sizes.h> 44 45#include "mmci.h" 46 47#define DRIVER_NAME "mmci-pl18x" 48 49static unsigned int fmax = 515633; 50 51/** 52 * struct variant_data - MMCI variant-specific quirks 53 * @clkreg: default value for MCICLOCK register 54 * @clkreg_enable: enable value for MMCICLOCK register 55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus 56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output 57 * @datalength_bits: number of bits in the MMCIDATALENGTH register 58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 59 * is asserted (likewise for RX) 60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 61 * is asserted (likewise for RX) 62 * @data_cmd_enable: enable value for data commands. 63 * @sdio: variant supports SDIO 64 * @st_clkdiv: true if using a ST-specific clock divider algorithm 65 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register. 66 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 67 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 68 * register 69 * @pwrreg_powerup: power up value for MMCIPOWER register 70 * @signal_direction: input/out direction of bus signals can be indicated 71 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 72 * @busy_detect: true if busy detection on dat0 is supported 73 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 74 */ 75struct variant_data { 76 unsigned int clkreg; 77 unsigned int clkreg_enable; 78 unsigned int clkreg_8bit_bus_enable; 79 unsigned int clkreg_neg_edge_enable; 80 unsigned int datalength_bits; 81 unsigned int fifosize; 82 unsigned int fifohalfsize; 83 unsigned int data_cmd_enable; 84 unsigned int datactrl_mask_ddrmode; 85 bool sdio; 86 bool st_clkdiv; 87 bool blksz_datactrl16; 88 bool blksz_datactrl4; 89 u32 pwrreg_powerup; 90 bool signal_direction; 91 bool pwrreg_clkgate; 92 bool busy_detect; 93 bool pwrreg_nopower; 94}; 95 96static struct variant_data variant_arm = { 97 .fifosize = 16 * 4, 98 .fifohalfsize = 8 * 4, 99 .datalength_bits = 16, 100 .pwrreg_powerup = MCI_PWR_UP, 101}; 102 103static struct variant_data variant_arm_extended_fifo = { 104 .fifosize = 128 * 4, 105 .fifohalfsize = 64 * 4, 106 .datalength_bits = 16, 107 .pwrreg_powerup = MCI_PWR_UP, 108}; 109 110static struct variant_data variant_arm_extended_fifo_hwfc = { 111 .fifosize = 128 * 4, 112 .fifohalfsize = 64 * 4, 113 .clkreg_enable = MCI_ARM_HWFCEN, 114 .datalength_bits = 16, 115 .pwrreg_powerup = MCI_PWR_UP, 116}; 117 118static struct variant_data variant_u300 = { 119 .fifosize = 16 * 4, 120 .fifohalfsize = 8 * 4, 121 .clkreg_enable = MCI_ST_U300_HWFCEN, 122 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 123 .datalength_bits = 16, 124 .sdio = true, 125 .pwrreg_powerup = MCI_PWR_ON, 126 .signal_direction = true, 127 .pwrreg_clkgate = true, 128 .pwrreg_nopower = true, 129}; 130 131static struct variant_data variant_nomadik = { 132 .fifosize = 16 * 4, 133 .fifohalfsize = 8 * 4, 134 .clkreg = MCI_CLK_ENABLE, 135 .datalength_bits = 24, 136 .sdio = true, 137 .st_clkdiv = true, 138 .pwrreg_powerup = MCI_PWR_ON, 139 .signal_direction = true, 140 .pwrreg_clkgate = true, 141 .pwrreg_nopower = true, 142}; 143 144static struct variant_data variant_ux500 = { 145 .fifosize = 30 * 4, 146 .fifohalfsize = 8 * 4, 147 .clkreg = MCI_CLK_ENABLE, 148 .clkreg_enable = MCI_ST_UX500_HWFCEN, 149 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 150 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 151 .datalength_bits = 24, 152 .sdio = true, 153 .st_clkdiv = true, 154 .pwrreg_powerup = MCI_PWR_ON, 155 .signal_direction = true, 156 .pwrreg_clkgate = true, 157 .busy_detect = true, 158 .pwrreg_nopower = true, 159}; 160 161static struct variant_data variant_ux500v2 = { 162 .fifosize = 30 * 4, 163 .fifohalfsize = 8 * 4, 164 .clkreg = MCI_CLK_ENABLE, 165 .clkreg_enable = MCI_ST_UX500_HWFCEN, 166 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, 167 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, 168 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE, 169 .datalength_bits = 24, 170 .sdio = true, 171 .st_clkdiv = true, 172 .blksz_datactrl16 = true, 173 .pwrreg_powerup = MCI_PWR_ON, 174 .signal_direction = true, 175 .pwrreg_clkgate = true, 176 .busy_detect = true, 177 .pwrreg_nopower = true, 178}; 179 180static int mmci_card_busy(struct mmc_host *mmc) 181{ 182 struct mmci_host *host = mmc_priv(mmc); 183 unsigned long flags; 184 int busy = 0; 185 186 pm_runtime_get_sync(mmc_dev(mmc)); 187 188 spin_lock_irqsave(&host->lock, flags); 189 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 190 busy = 1; 191 spin_unlock_irqrestore(&host->lock, flags); 192 193 pm_runtime_mark_last_busy(mmc_dev(mmc)); 194 pm_runtime_put_autosuspend(mmc_dev(mmc)); 195 196 return busy; 197} 198 199/* 200 * Validate mmc prerequisites 201 */ 202static int mmci_validate_data(struct mmci_host *host, 203 struct mmc_data *data) 204{ 205 if (!data) 206 return 0; 207 208 if (!is_power_of_2(data->blksz)) { 209 dev_err(mmc_dev(host->mmc), 210 "unsupported block size (%d bytes)\n", data->blksz); 211 return -EINVAL; 212 } 213 214 return 0; 215} 216 217static void mmci_reg_delay(struct mmci_host *host) 218{ 219 /* 220 * According to the spec, at least three feedback clock cycles 221 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 222 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 223 * Worst delay time during card init is at 100 kHz => 30 us. 224 * Worst delay time when up and running is at 25 MHz => 120 ns. 225 */ 226 if (host->cclk < 25000000) 227 udelay(30); 228 else 229 ndelay(120); 230} 231 232/* 233 * This must be called with host->lock held 234 */ 235static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 236{ 237 if (host->clk_reg != clk) { 238 host->clk_reg = clk; 239 writel(clk, host->base + MMCICLOCK); 240 } 241} 242 243/* 244 * This must be called with host->lock held 245 */ 246static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 247{ 248 if (host->pwr_reg != pwr) { 249 host->pwr_reg = pwr; 250 writel(pwr, host->base + MMCIPOWER); 251 } 252} 253 254/* 255 * This must be called with host->lock held 256 */ 257static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 258{ 259 /* Keep ST Micro busy mode if enabled */ 260 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 261 262 if (host->datactrl_reg != datactrl) { 263 host->datactrl_reg = datactrl; 264 writel(datactrl, host->base + MMCIDATACTRL); 265 } 266} 267 268/* 269 * This must be called with host->lock held 270 */ 271static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 272{ 273 struct variant_data *variant = host->variant; 274 u32 clk = variant->clkreg; 275 276 /* Make sure cclk reflects the current calculated clock */ 277 host->cclk = 0; 278 279 if (desired) { 280 if (desired >= host->mclk) { 281 clk = MCI_CLK_BYPASS; 282 if (variant->st_clkdiv) 283 clk |= MCI_ST_UX500_NEG_EDGE; 284 host->cclk = host->mclk; 285 } else if (variant->st_clkdiv) { 286 /* 287 * DB8500 TRM says f = mclk / (clkdiv + 2) 288 * => clkdiv = (mclk / f) - 2 289 * Round the divider up so we don't exceed the max 290 * frequency 291 */ 292 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 293 if (clk >= 256) 294 clk = 255; 295 host->cclk = host->mclk / (clk + 2); 296 } else { 297 /* 298 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 299 * => clkdiv = mclk / (2 * f) - 1 300 */ 301 clk = host->mclk / (2 * desired) - 1; 302 if (clk >= 256) 303 clk = 255; 304 host->cclk = host->mclk / (2 * (clk + 1)); 305 } 306 307 clk |= variant->clkreg_enable; 308 clk |= MCI_CLK_ENABLE; 309 /* This hasn't proven to be worthwhile */ 310 /* clk |= MCI_CLK_PWRSAVE; */ 311 } 312 313 /* Set actual clock for debug */ 314 host->mmc->actual_clock = host->cclk; 315 316 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 317 clk |= MCI_4BIT_BUS; 318 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 319 clk |= variant->clkreg_8bit_bus_enable; 320 321 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 322 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 323 clk |= variant->clkreg_neg_edge_enable; 324 325 mmci_write_clkreg(host, clk); 326} 327 328static void 329mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 330{ 331 writel(0, host->base + MMCICOMMAND); 332 333 BUG_ON(host->data); 334 335 host->mrq = NULL; 336 host->cmd = NULL; 337 338 mmc_request_done(host->mmc, mrq); 339 340 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 341 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 342} 343 344static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 345{ 346 void __iomem *base = host->base; 347 348 if (host->singleirq) { 349 unsigned int mask0 = readl(base + MMCIMASK0); 350 351 mask0 &= ~MCI_IRQ1MASK; 352 mask0 |= mask; 353 354 writel(mask0, base + MMCIMASK0); 355 } 356 357 writel(mask, base + MMCIMASK1); 358} 359 360static void mmci_stop_data(struct mmci_host *host) 361{ 362 mmci_write_datactrlreg(host, 0); 363 mmci_set_mask1(host, 0); 364 host->data = NULL; 365} 366 367static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 368{ 369 unsigned int flags = SG_MITER_ATOMIC; 370 371 if (data->flags & MMC_DATA_READ) 372 flags |= SG_MITER_TO_SG; 373 else 374 flags |= SG_MITER_FROM_SG; 375 376 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 377} 378 379/* 380 * All the DMA operation mode stuff goes inside this ifdef. 381 * This assumes that you have a generic DMA device interface, 382 * no custom DMA interfaces are supported. 383 */ 384#ifdef CONFIG_DMA_ENGINE 385static void mmci_dma_setup(struct mmci_host *host) 386{ 387 const char *rxname, *txname; 388 dma_cap_mask_t mask; 389 390 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 391 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 392 393 /* initialize pre request cookie */ 394 host->next_data.cookie = 1; 395 396 /* Try to acquire a generic DMA engine slave channel */ 397 dma_cap_zero(mask); 398 dma_cap_set(DMA_SLAVE, mask); 399 400 /* 401 * If only an RX channel is specified, the driver will 402 * attempt to use it bidirectionally, however if it is 403 * is specified but cannot be located, DMA will be disabled. 404 */ 405 if (host->dma_rx_channel && !host->dma_tx_channel) 406 host->dma_tx_channel = host->dma_rx_channel; 407 408 if (host->dma_rx_channel) 409 rxname = dma_chan_name(host->dma_rx_channel); 410 else 411 rxname = "none"; 412 413 if (host->dma_tx_channel) 414 txname = dma_chan_name(host->dma_tx_channel); 415 else 416 txname = "none"; 417 418 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 419 rxname, txname); 420 421 /* 422 * Limit the maximum segment size in any SG entry according to 423 * the parameters of the DMA engine device. 424 */ 425 if (host->dma_tx_channel) { 426 struct device *dev = host->dma_tx_channel->device->dev; 427 unsigned int max_seg_size = dma_get_max_seg_size(dev); 428 429 if (max_seg_size < host->mmc->max_seg_size) 430 host->mmc->max_seg_size = max_seg_size; 431 } 432 if (host->dma_rx_channel) { 433 struct device *dev = host->dma_rx_channel->device->dev; 434 unsigned int max_seg_size = dma_get_max_seg_size(dev); 435 436 if (max_seg_size < host->mmc->max_seg_size) 437 host->mmc->max_seg_size = max_seg_size; 438 } 439} 440 441/* 442 * This is used in or so inline it 443 * so it can be discarded. 444 */ 445static inline void mmci_dma_release(struct mmci_host *host) 446{ 447 if (host->dma_rx_channel) 448 dma_release_channel(host->dma_rx_channel); 449 if (host->dma_tx_channel) 450 dma_release_channel(host->dma_tx_channel); 451 host->dma_rx_channel = host->dma_tx_channel = NULL; 452} 453 454static void mmci_dma_data_error(struct mmci_host *host) 455{ 456 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 457 dmaengine_terminate_all(host->dma_current); 458 host->dma_current = NULL; 459 host->dma_desc_current = NULL; 460 host->data->host_cookie = 0; 461} 462 463static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 464{ 465 struct dma_chan *chan; 466 enum dma_data_direction dir; 467 468 if (data->flags & MMC_DATA_READ) { 469 dir = DMA_FROM_DEVICE; 470 chan = host->dma_rx_channel; 471 } else { 472 dir = DMA_TO_DEVICE; 473 chan = host->dma_tx_channel; 474 } 475 476 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 477} 478 479static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 480{ 481 u32 status; 482 int i; 483 484 /* Wait up to 1ms for the DMA to complete */ 485 for (i = 0; ; i++) { 486 status = readl(host->base + MMCISTATUS); 487 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 488 break; 489 udelay(10); 490 } 491 492 /* 493 * Check to see whether we still have some data left in the FIFO - 494 * this catches DMA controllers which are unable to monitor the 495 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 496 * contiguous buffers. On TX, we'll get a FIFO underrun error. 497 */ 498 if (status & MCI_RXDATAAVLBLMASK) { 499 mmci_dma_data_error(host); 500 if (!data->error) 501 data->error = -EIO; 502 } 503 504 if (!data->host_cookie) 505 mmci_dma_unmap(host, data); 506 507 /* 508 * Use of DMA with scatter-gather is impossible. 509 * Give up with DMA and switch back to PIO mode. 510 */ 511 if (status & MCI_RXDATAAVLBLMASK) { 512 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 513 mmci_dma_release(host); 514 } 515 516 host->dma_current = NULL; 517 host->dma_desc_current = NULL; 518} 519 520/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 521static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 522 struct dma_chan **dma_chan, 523 struct dma_async_tx_descriptor **dma_desc) 524{ 525 struct variant_data *variant = host->variant; 526 struct dma_slave_config conf = { 527 .src_addr = host->phybase + MMCIFIFO, 528 .dst_addr = host->phybase + MMCIFIFO, 529 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 530 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 531 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 532 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 533 .device_fc = false, 534 }; 535 struct dma_chan *chan; 536 struct dma_device *device; 537 struct dma_async_tx_descriptor *desc; 538 enum dma_data_direction buffer_dirn; 539 int nr_sg; 540 541 if (data->flags & MMC_DATA_READ) { 542 conf.direction = DMA_DEV_TO_MEM; 543 buffer_dirn = DMA_FROM_DEVICE; 544 chan = host->dma_rx_channel; 545 } else { 546 conf.direction = DMA_MEM_TO_DEV; 547 buffer_dirn = DMA_TO_DEVICE; 548 chan = host->dma_tx_channel; 549 } 550 551 /* If there's no DMA channel, fall back to PIO */ 552 if (!chan) 553 return -EINVAL; 554 555 /* If less than or equal to the fifo size, don't bother with DMA */ 556 if (data->blksz * data->blocks <= variant->fifosize) 557 return -EINVAL; 558 559 device = chan->device; 560 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 561 if (nr_sg == 0) 562 return -EINVAL; 563 564 dmaengine_slave_config(chan, &conf); 565 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 566 conf.direction, DMA_CTRL_ACK); 567 if (!desc) 568 goto unmap_exit; 569 570 *dma_chan = chan; 571 *dma_desc = desc; 572 573 return 0; 574 575 unmap_exit: 576 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 577 return -ENOMEM; 578} 579 580static inline int mmci_dma_prep_data(struct mmci_host *host, 581 struct mmc_data *data) 582{ 583 /* Check if next job is already prepared. */ 584 if (host->dma_current && host->dma_desc_current) 585 return 0; 586 587 /* No job were prepared thus do it now. */ 588 return __mmci_dma_prep_data(host, data, &host->dma_current, 589 &host->dma_desc_current); 590} 591 592static inline int mmci_dma_prep_next(struct mmci_host *host, 593 struct mmc_data *data) 594{ 595 struct mmci_host_next *nd = &host->next_data; 596 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 597} 598 599static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 600{ 601 int ret; 602 struct mmc_data *data = host->data; 603 604 ret = mmci_dma_prep_data(host, host->data); 605 if (ret) 606 return ret; 607 608 /* Okay, go for it. */ 609 dev_vdbg(mmc_dev(host->mmc), 610 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 611 data->sg_len, data->blksz, data->blocks, data->flags); 612 dmaengine_submit(host->dma_desc_current); 613 dma_async_issue_pending(host->dma_current); 614 615 datactrl |= MCI_DPSM_DMAENABLE; 616 617 /* Trigger the DMA transfer */ 618 mmci_write_datactrlreg(host, datactrl); 619 620 /* 621 * Let the MMCI say when the data is ended and it's time 622 * to fire next DMA request. When that happens, MMCI will 623 * call mmci_data_end() 624 */ 625 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 626 host->base + MMCIMASK0); 627 return 0; 628} 629 630static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 631{ 632 struct mmci_host_next *next = &host->next_data; 633 634 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 635 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 636 637 host->dma_desc_current = next->dma_desc; 638 host->dma_current = next->dma_chan; 639 next->dma_desc = NULL; 640 next->dma_chan = NULL; 641} 642 643static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 644 bool is_first_req) 645{ 646 struct mmci_host *host = mmc_priv(mmc); 647 struct mmc_data *data = mrq->data; 648 struct mmci_host_next *nd = &host->next_data; 649 650 if (!data) 651 return; 652 653 BUG_ON(data->host_cookie); 654 655 if (mmci_validate_data(host, data)) 656 return; 657 658 if (!mmci_dma_prep_next(host, data)) 659 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 660} 661 662static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 663 int err) 664{ 665 struct mmci_host *host = mmc_priv(mmc); 666 struct mmc_data *data = mrq->data; 667 668 if (!data || !data->host_cookie) 669 return; 670 671 mmci_dma_unmap(host, data); 672 673 if (err) { 674 struct mmci_host_next *next = &host->next_data; 675 struct dma_chan *chan; 676 if (data->flags & MMC_DATA_READ) 677 chan = host->dma_rx_channel; 678 else 679 chan = host->dma_tx_channel; 680 dmaengine_terminate_all(chan); 681 682 next->dma_desc = NULL; 683 next->dma_chan = NULL; 684 } 685} 686 687#else 688/* Blank functions if the DMA engine is not available */ 689static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 690{ 691} 692static inline void mmci_dma_setup(struct mmci_host *host) 693{ 694} 695 696static inline void mmci_dma_release(struct mmci_host *host) 697{ 698} 699 700static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 701{ 702} 703 704static inline void mmci_dma_finalize(struct mmci_host *host, 705 struct mmc_data *data) 706{ 707} 708 709static inline void mmci_dma_data_error(struct mmci_host *host) 710{ 711} 712 713static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 714{ 715 return -ENOSYS; 716} 717 718#define mmci_pre_request NULL 719#define mmci_post_request NULL 720 721#endif 722 723static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 724{ 725 struct variant_data *variant = host->variant; 726 unsigned int datactrl, timeout, irqmask; 727 unsigned long long clks; 728 void __iomem *base; 729 int blksz_bits; 730 731 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 732 data->blksz, data->blocks, data->flags); 733 734 host->data = data; 735 host->size = data->blksz * data->blocks; 736 data->bytes_xfered = 0; 737 738 clks = (unsigned long long)data->timeout_ns * host->cclk; 739 do_div(clks, NSEC_PER_SEC); 740 741 timeout = data->timeout_clks + (unsigned int)clks; 742 743 base = host->base; 744 writel(timeout, base + MMCIDATATIMER); 745 writel(host->size, base + MMCIDATALENGTH); 746 747 blksz_bits = ffs(data->blksz) - 1; 748 BUG_ON(1 << blksz_bits != data->blksz); 749 750 if (variant->blksz_datactrl16) 751 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 752 else if (variant->blksz_datactrl4) 753 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 754 else 755 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 756 757 if (data->flags & MMC_DATA_READ) 758 datactrl |= MCI_DPSM_DIRECTION; 759 760 /* The ST Micro variants has a special bit to enable SDIO */ 761 if (variant->sdio && host->mmc->card) 762 if (mmc_card_sdio(host->mmc->card)) { 763 /* 764 * The ST Micro variants has a special bit 765 * to enable SDIO. 766 */ 767 u32 clk; 768 769 datactrl |= MCI_ST_DPSM_SDIOEN; 770 771 /* 772 * The ST Micro variant for SDIO small write transfers 773 * needs to have clock H/W flow control disabled, 774 * otherwise the transfer will not start. The threshold 775 * depends on the rate of MCLK. 776 */ 777 if (data->flags & MMC_DATA_WRITE && 778 (host->size < 8 || 779 (host->size <= 8 && host->mclk > 50000000))) 780 clk = host->clk_reg & ~variant->clkreg_enable; 781 else 782 clk = host->clk_reg | variant->clkreg_enable; 783 784 mmci_write_clkreg(host, clk); 785 } 786 787 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 788 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 789 datactrl |= variant->datactrl_mask_ddrmode; 790 791 /* 792 * Attempt to use DMA operation mode, if this 793 * should fail, fall back to PIO mode 794 */ 795 if (!mmci_dma_start_data(host, datactrl)) 796 return; 797 798 /* IRQ mode, map the SG list for CPU reading/writing */ 799 mmci_init_sg(host, data); 800 801 if (data->flags & MMC_DATA_READ) { 802 irqmask = MCI_RXFIFOHALFFULLMASK; 803 804 /* 805 * If we have less than the fifo 'half-full' threshold to 806 * transfer, trigger a PIO interrupt as soon as any data 807 * is available. 808 */ 809 if (host->size < variant->fifohalfsize) 810 irqmask |= MCI_RXDATAAVLBLMASK; 811 } else { 812 /* 813 * We don't actually need to include "FIFO empty" here 814 * since its implicit in "FIFO half empty". 815 */ 816 irqmask = MCI_TXFIFOHALFEMPTYMASK; 817 } 818 819 mmci_write_datactrlreg(host, datactrl); 820 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 821 mmci_set_mask1(host, irqmask); 822} 823 824static void 825mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 826{ 827 void __iomem *base = host->base; 828 829 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 830 cmd->opcode, cmd->arg, cmd->flags); 831 832 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 833 writel(0, base + MMCICOMMAND); 834 mmci_reg_delay(host); 835 } 836 837 c |= cmd->opcode | MCI_CPSM_ENABLE; 838 if (cmd->flags & MMC_RSP_PRESENT) { 839 if (cmd->flags & MMC_RSP_136) 840 c |= MCI_CPSM_LONGRSP; 841 c |= MCI_CPSM_RESPONSE; 842 } 843 if (/*interrupt*/0) 844 c |= MCI_CPSM_INTERRUPT; 845 846 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) 847 c |= host->variant->data_cmd_enable; 848 849 host->cmd = cmd; 850 851 writel(cmd->arg, base + MMCIARGUMENT); 852 writel(c, base + MMCICOMMAND); 853} 854 855static void 856mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 857 unsigned int status) 858{ 859 /* First check for errors */ 860 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 861 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 862 u32 remain, success; 863 864 /* Terminate the DMA transfer */ 865 if (dma_inprogress(host)) { 866 mmci_dma_data_error(host); 867 mmci_dma_unmap(host, data); 868 } 869 870 /* 871 * Calculate how far we are into the transfer. Note that 872 * the data counter gives the number of bytes transferred 873 * on the MMC bus, not on the host side. On reads, this 874 * can be as much as a FIFO-worth of data ahead. This 875 * matters for FIFO overruns only. 876 */ 877 remain = readl(host->base + MMCIDATACNT); 878 success = data->blksz * data->blocks - remain; 879 880 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 881 status, success); 882 if (status & MCI_DATACRCFAIL) { 883 /* Last block was not successful */ 884 success -= 1; 885 data->error = -EILSEQ; 886 } else if (status & MCI_DATATIMEOUT) { 887 data->error = -ETIMEDOUT; 888 } else if (status & MCI_STARTBITERR) { 889 data->error = -ECOMM; 890 } else if (status & MCI_TXUNDERRUN) { 891 data->error = -EIO; 892 } else if (status & MCI_RXOVERRUN) { 893 if (success > host->variant->fifosize) 894 success -= host->variant->fifosize; 895 else 896 success = 0; 897 data->error = -EIO; 898 } 899 data->bytes_xfered = round_down(success, data->blksz); 900 } 901 902 if (status & MCI_DATABLOCKEND) 903 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 904 905 if (status & MCI_DATAEND || data->error) { 906 if (dma_inprogress(host)) 907 mmci_dma_finalize(host, data); 908 mmci_stop_data(host); 909 910 if (!data->error) 911 /* The error clause is handled above, success! */ 912 data->bytes_xfered = data->blksz * data->blocks; 913 914 if (!data->stop || host->mrq->sbc) { 915 mmci_request_end(host, data->mrq); 916 } else { 917 mmci_start_command(host, data->stop, 0); 918 } 919 } 920} 921 922static void 923mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 924 unsigned int status) 925{ 926 void __iomem *base = host->base; 927 bool sbc = (cmd == host->mrq->sbc); 928 bool busy_resp = host->variant->busy_detect && 929 (cmd->flags & MMC_RSP_BUSY); 930 931 /* Check if we need to wait for busy completion. */ 932 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 933 return; 934 935 /* Enable busy completion if needed and supported. */ 936 if (!host->busy_status && busy_resp && 937 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 938 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 939 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 940 base + MMCIMASK0); 941 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 942 return; 943 } 944 945 /* At busy completion, mask the IRQ and complete the request. */ 946 if (host->busy_status) { 947 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 948 base + MMCIMASK0); 949 host->busy_status = 0; 950 } 951 952 host->cmd = NULL; 953 954 if (status & MCI_CMDTIMEOUT) { 955 cmd->error = -ETIMEDOUT; 956 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 957 cmd->error = -EILSEQ; 958 } else { 959 cmd->resp[0] = readl(base + MMCIRESPONSE0); 960 cmd->resp[1] = readl(base + MMCIRESPONSE1); 961 cmd->resp[2] = readl(base + MMCIRESPONSE2); 962 cmd->resp[3] = readl(base + MMCIRESPONSE3); 963 } 964 965 if ((!sbc && !cmd->data) || cmd->error) { 966 if (host->data) { 967 /* Terminate the DMA transfer */ 968 if (dma_inprogress(host)) { 969 mmci_dma_data_error(host); 970 mmci_dma_unmap(host, host->data); 971 } 972 mmci_stop_data(host); 973 } 974 mmci_request_end(host, host->mrq); 975 } else if (sbc) { 976 mmci_start_command(host, host->mrq->cmd, 0); 977 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 978 mmci_start_data(host, cmd->data); 979 } 980} 981 982static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 983{ 984 void __iomem *base = host->base; 985 char *ptr = buffer; 986 u32 status; 987 int host_remain = host->size; 988 989 do { 990 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 991 992 if (count > remain) 993 count = remain; 994 995 if (count <= 0) 996 break; 997 998 /* 999 * SDIO especially may want to send something that is 1000 * not divisible by 4 (as opposed to card sectors 1001 * etc). Therefore make sure to always read the last bytes 1002 * while only doing full 32-bit reads towards the FIFO. 1003 */ 1004 if (unlikely(count & 0x3)) { 1005 if (count < 4) { 1006 unsigned char buf[4]; 1007 ioread32_rep(base + MMCIFIFO, buf, 1); 1008 memcpy(ptr, buf, count); 1009 } else { 1010 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1011 count &= ~0x3; 1012 } 1013 } else { 1014 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 1015 } 1016 1017 ptr += count; 1018 remain -= count; 1019 host_remain -= count; 1020 1021 if (remain == 0) 1022 break; 1023 1024 status = readl(base + MMCISTATUS); 1025 } while (status & MCI_RXDATAAVLBL); 1026 1027 return ptr - buffer; 1028} 1029 1030static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1031{ 1032 struct variant_data *variant = host->variant; 1033 void __iomem *base = host->base; 1034 char *ptr = buffer; 1035 1036 do { 1037 unsigned int count, maxcnt; 1038 1039 maxcnt = status & MCI_TXFIFOEMPTY ? 1040 variant->fifosize : variant->fifohalfsize; 1041 count = min(remain, maxcnt); 1042 1043 /* 1044 * SDIO especially may want to send something that is 1045 * not divisible by 4 (as opposed to card sectors 1046 * etc), and the FIFO only accept full 32-bit writes. 1047 * So compensate by adding +3 on the count, a single 1048 * byte become a 32bit write, 7 bytes will be two 1049 * 32bit writes etc. 1050 */ 1051 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1052 1053 ptr += count; 1054 remain -= count; 1055 1056 if (remain == 0) 1057 break; 1058 1059 status = readl(base + MMCISTATUS); 1060 } while (status & MCI_TXFIFOHALFEMPTY); 1061 1062 return ptr - buffer; 1063} 1064 1065/* 1066 * PIO data transfer IRQ handler. 1067 */ 1068static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1069{ 1070 struct mmci_host *host = dev_id; 1071 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1072 struct variant_data *variant = host->variant; 1073 void __iomem *base = host->base; 1074 unsigned long flags; 1075 u32 status; 1076 1077 status = readl(base + MMCISTATUS); 1078 1079 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1080 1081 local_irq_save(flags); 1082 1083 do { 1084 unsigned int remain, len; 1085 char *buffer; 1086 1087 /* 1088 * For write, we only need to test the half-empty flag 1089 * here - if the FIFO is completely empty, then by 1090 * definition it is more than half empty. 1091 * 1092 * For read, check for data available. 1093 */ 1094 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1095 break; 1096 1097 if (!sg_miter_next(sg_miter)) 1098 break; 1099 1100 buffer = sg_miter->addr; 1101 remain = sg_miter->length; 1102 1103 len = 0; 1104 if (status & MCI_RXACTIVE) 1105 len = mmci_pio_read(host, buffer, remain); 1106 if (status & MCI_TXACTIVE) 1107 len = mmci_pio_write(host, buffer, remain, status); 1108 1109 sg_miter->consumed = len; 1110 1111 host->size -= len; 1112 remain -= len; 1113 1114 if (remain) 1115 break; 1116 1117 status = readl(base + MMCISTATUS); 1118 } while (1); 1119 1120 sg_miter_stop(sg_miter); 1121 1122 local_irq_restore(flags); 1123 1124 /* 1125 * If we have less than the fifo 'half-full' threshold to transfer, 1126 * trigger a PIO interrupt as soon as any data is available. 1127 */ 1128 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1129 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1130 1131 /* 1132 * If we run out of data, disable the data IRQs; this 1133 * prevents a race where the FIFO becomes empty before 1134 * the chip itself has disabled the data path, and 1135 * stops us racing with our data end IRQ. 1136 */ 1137 if (host->size == 0) { 1138 mmci_set_mask1(host, 0); 1139 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1140 } 1141 1142 return IRQ_HANDLED; 1143} 1144 1145/* 1146 * Handle completion of command and data transfers. 1147 */ 1148static irqreturn_t mmci_irq(int irq, void *dev_id) 1149{ 1150 struct mmci_host *host = dev_id; 1151 u32 status; 1152 int ret = 0; 1153 1154 spin_lock(&host->lock); 1155 1156 do { 1157 struct mmc_command *cmd; 1158 struct mmc_data *data; 1159 1160 status = readl(host->base + MMCISTATUS); 1161 1162 if (host->singleirq) { 1163 if (status & readl(host->base + MMCIMASK1)) 1164 mmci_pio_irq(irq, dev_id); 1165 1166 status &= ~MCI_IRQ1MASK; 1167 } 1168 1169 /* 1170 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1171 * enabled) since the HW seems to be triggering the IRQ on both 1172 * edges while monitoring DAT0 for busy completion. 1173 */ 1174 status &= readl(host->base + MMCIMASK0); 1175 writel(status, host->base + MMCICLEAR); 1176 1177 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1178 1179 cmd = host->cmd; 1180 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 1181 MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1182 mmci_cmd_irq(host, cmd, status); 1183 1184 data = host->data; 1185 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1186 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1187 MCI_DATABLOCKEND) && data) 1188 mmci_data_irq(host, data, status); 1189 1190 /* Don't poll for busy completion in irq context. */ 1191 if (host->busy_status) 1192 status &= ~MCI_ST_CARDBUSY; 1193 1194 ret = 1; 1195 } while (status); 1196 1197 spin_unlock(&host->lock); 1198 1199 return IRQ_RETVAL(ret); 1200} 1201 1202static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1203{ 1204 struct mmci_host *host = mmc_priv(mmc); 1205 unsigned long flags; 1206 1207 WARN_ON(host->mrq != NULL); 1208 1209 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1210 if (mrq->cmd->error) { 1211 mmc_request_done(mmc, mrq); 1212 return; 1213 } 1214 1215 pm_runtime_get_sync(mmc_dev(mmc)); 1216 1217 spin_lock_irqsave(&host->lock, flags); 1218 1219 host->mrq = mrq; 1220 1221 if (mrq->data) 1222 mmci_get_next_data(host, mrq->data); 1223 1224 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1225 mmci_start_data(host, mrq->data); 1226 1227 if (mrq->sbc) 1228 mmci_start_command(host, mrq->sbc, 0); 1229 else 1230 mmci_start_command(host, mrq->cmd, 0); 1231 1232 spin_unlock_irqrestore(&host->lock, flags); 1233} 1234 1235static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1236{ 1237 struct mmci_host *host = mmc_priv(mmc); 1238 struct variant_data *variant = host->variant; 1239 u32 pwr = 0; 1240 unsigned long flags; 1241 int ret; 1242 1243 pm_runtime_get_sync(mmc_dev(mmc)); 1244 1245 if (host->plat->ios_handler && 1246 host->plat->ios_handler(mmc_dev(mmc), ios)) 1247 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1248 1249 switch (ios->power_mode) { 1250 case MMC_POWER_OFF: 1251 if (!IS_ERR(mmc->supply.vmmc)) 1252 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1253 1254 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1255 regulator_disable(mmc->supply.vqmmc); 1256 host->vqmmc_enabled = false; 1257 } 1258 1259 break; 1260 case MMC_POWER_UP: 1261 if (!IS_ERR(mmc->supply.vmmc)) 1262 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1263 1264 /* 1265 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1266 * and instead uses MCI_PWR_ON so apply whatever value is 1267 * configured in the variant data. 1268 */ 1269 pwr |= variant->pwrreg_powerup; 1270 1271 break; 1272 case MMC_POWER_ON: 1273 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1274 ret = regulator_enable(mmc->supply.vqmmc); 1275 if (ret < 0) 1276 dev_err(mmc_dev(mmc), 1277 "failed to enable vqmmc regulator\n"); 1278 else 1279 host->vqmmc_enabled = true; 1280 } 1281 1282 pwr |= MCI_PWR_ON; 1283 break; 1284 } 1285 1286 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1287 /* 1288 * The ST Micro variant has some additional bits 1289 * indicating signal direction for the signals in 1290 * the SD/MMC bus and feedback-clock usage. 1291 */ 1292 pwr |= host->pwr_reg_add; 1293 1294 if (ios->bus_width == MMC_BUS_WIDTH_4) 1295 pwr &= ~MCI_ST_DATA74DIREN; 1296 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1297 pwr &= (~MCI_ST_DATA74DIREN & 1298 ~MCI_ST_DATA31DIREN & 1299 ~MCI_ST_DATA2DIREN); 1300 } 1301 1302 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1303 if (host->hw_designer != AMBA_VENDOR_ST) 1304 pwr |= MCI_ROD; 1305 else { 1306 /* 1307 * The ST Micro variant use the ROD bit for something 1308 * else and only has OD (Open Drain). 1309 */ 1310 pwr |= MCI_OD; 1311 } 1312 } 1313 1314 /* 1315 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1316 * gating the clock, the MCI_PWR_ON bit is cleared. 1317 */ 1318 if (!ios->clock && variant->pwrreg_clkgate) 1319 pwr &= ~MCI_PWR_ON; 1320 1321 spin_lock_irqsave(&host->lock, flags); 1322 1323 mmci_set_clkreg(host, ios->clock); 1324 mmci_write_pwrreg(host, pwr); 1325 mmci_reg_delay(host); 1326 1327 spin_unlock_irqrestore(&host->lock, flags); 1328 1329 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1330 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1331} 1332 1333static int mmci_get_cd(struct mmc_host *mmc) 1334{ 1335 struct mmci_host *host = mmc_priv(mmc); 1336 struct mmci_platform_data *plat = host->plat; 1337 unsigned int status = mmc_gpio_get_cd(mmc); 1338 1339 if (status == -ENOSYS) { 1340 if (!plat->status) 1341 return 1; /* Assume always present */ 1342 1343 status = plat->status(mmc_dev(host->mmc)); 1344 } 1345 return status; 1346} 1347 1348static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1349{ 1350 int ret = 0; 1351 1352 if (!IS_ERR(mmc->supply.vqmmc)) { 1353 1354 pm_runtime_get_sync(mmc_dev(mmc)); 1355 1356 switch (ios->signal_voltage) { 1357 case MMC_SIGNAL_VOLTAGE_330: 1358 ret = regulator_set_voltage(mmc->supply.vqmmc, 1359 2700000, 3600000); 1360 break; 1361 case MMC_SIGNAL_VOLTAGE_180: 1362 ret = regulator_set_voltage(mmc->supply.vqmmc, 1363 1700000, 1950000); 1364 break; 1365 case MMC_SIGNAL_VOLTAGE_120: 1366 ret = regulator_set_voltage(mmc->supply.vqmmc, 1367 1100000, 1300000); 1368 break; 1369 } 1370 1371 if (ret) 1372 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1373 1374 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1375 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1376 } 1377 1378 return ret; 1379} 1380 1381static struct mmc_host_ops mmci_ops = { 1382 .request = mmci_request, 1383 .pre_req = mmci_pre_request, 1384 .post_req = mmci_post_request, 1385 .set_ios = mmci_set_ios, 1386 .get_ro = mmc_gpio_get_ro, 1387 .get_cd = mmci_get_cd, 1388 .start_signal_voltage_switch = mmci_sig_volt_switch, 1389}; 1390 1391static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1392{ 1393 struct mmci_host *host = mmc_priv(mmc); 1394 int ret = mmc_of_parse(mmc); 1395 1396 if (ret) 1397 return ret; 1398 1399 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1400 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1401 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1402 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1403 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1404 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1405 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1406 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1407 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1408 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1409 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1410 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1411 1412 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1413 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1414 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1415 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1416 1417 return 0; 1418} 1419 1420static int mmci_probe(struct amba_device *dev, 1421 const struct amba_id *id) 1422{ 1423 struct mmci_platform_data *plat = dev->dev.platform_data; 1424 struct device_node *np = dev->dev.of_node; 1425 struct variant_data *variant = id->data; 1426 struct mmci_host *host; 1427 struct mmc_host *mmc; 1428 int ret; 1429 1430 /* Must have platform data or Device Tree. */ 1431 if (!plat && !np) { 1432 dev_err(&dev->dev, "No plat data or DT found\n"); 1433 return -EINVAL; 1434 } 1435 1436 if (!plat) { 1437 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1438 if (!plat) 1439 return -ENOMEM; 1440 } 1441 1442 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1443 if (!mmc) 1444 return -ENOMEM; 1445 1446 ret = mmci_of_parse(np, mmc); 1447 if (ret) 1448 goto host_free; 1449 1450 host = mmc_priv(mmc); 1451 host->mmc = mmc; 1452 1453 host->hw_designer = amba_manf(dev); 1454 host->hw_revision = amba_rev(dev); 1455 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1456 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1457 1458 host->clk = devm_clk_get(&dev->dev, NULL); 1459 if (IS_ERR(host->clk)) { 1460 ret = PTR_ERR(host->clk); 1461 goto host_free; 1462 } 1463 1464 ret = clk_prepare_enable(host->clk); 1465 if (ret) 1466 goto host_free; 1467 1468 host->plat = plat; 1469 host->variant = variant; 1470 host->mclk = clk_get_rate(host->clk); 1471 /* 1472 * According to the spec, mclk is max 100 MHz, 1473 * so we try to adjust the clock down to this, 1474 * (if possible). 1475 */ 1476 if (host->mclk > 100000000) { 1477 ret = clk_set_rate(host->clk, 100000000); 1478 if (ret < 0) 1479 goto clk_disable; 1480 host->mclk = clk_get_rate(host->clk); 1481 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1482 host->mclk); 1483 } 1484 1485 host->phybase = dev->res.start; 1486 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1487 if (IS_ERR(host->base)) { 1488 ret = PTR_ERR(host->base); 1489 goto clk_disable; 1490 } 1491 1492 /* 1493 * The ARM and ST versions of the block have slightly different 1494 * clock divider equations which means that the minimum divider 1495 * differs too. 1496 */ 1497 if (variant->st_clkdiv) 1498 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1499 else 1500 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1501 /* 1502 * If no maximum operating frequency is supplied, fall back to use 1503 * the module parameter, which has a (low) default value in case it 1504 * is not specified. Either value must not exceed the clock rate into 1505 * the block, of course. 1506 */ 1507 if (mmc->f_max) 1508 mmc->f_max = min(host->mclk, mmc->f_max); 1509 else 1510 mmc->f_max = min(host->mclk, fmax); 1511 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1512 1513 /* Get regulators and the supported OCR mask */ 1514 mmc_regulator_get_supply(mmc); 1515 if (!mmc->ocr_avail) 1516 mmc->ocr_avail = plat->ocr_mask; 1517 else if (plat->ocr_mask) 1518 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1519 1520 /* DT takes precedence over platform data. */ 1521 if (!np) { 1522 if (!plat->cd_invert) 1523 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1524 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1525 } 1526 1527 /* We support these capabilities. */ 1528 mmc->caps |= MMC_CAP_CMD23; 1529 1530 if (variant->busy_detect) { 1531 mmci_ops.card_busy = mmci_card_busy; 1532 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1533 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1534 mmc->max_busy_timeout = 0; 1535 } 1536 1537 mmc->ops = &mmci_ops; 1538 1539 /* We support these PM capabilities. */ 1540 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1541 1542 /* 1543 * We can do SGIO 1544 */ 1545 mmc->max_segs = NR_SG; 1546 1547 /* 1548 * Since only a certain number of bits are valid in the data length 1549 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1550 * single request. 1551 */ 1552 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1553 1554 /* 1555 * Set the maximum segment size. Since we aren't doing DMA 1556 * (yet) we are only limited by the data length register. 1557 */ 1558 mmc->max_seg_size = mmc->max_req_size; 1559 1560 /* 1561 * Block size can be up to 2048 bytes, but must be a power of two. 1562 */ 1563 mmc->max_blk_size = 1 << 11; 1564 1565 /* 1566 * Limit the number of blocks transferred so that we don't overflow 1567 * the maximum request size. 1568 */ 1569 mmc->max_blk_count = mmc->max_req_size >> 11; 1570 1571 spin_lock_init(&host->lock); 1572 1573 writel(0, host->base + MMCIMASK0); 1574 writel(0, host->base + MMCIMASK1); 1575 writel(0xfff, host->base + MMCICLEAR); 1576 1577 /* If DT, cd/wp gpios must be supplied through it. */ 1578 if (!np && gpio_is_valid(plat->gpio_cd)) { 1579 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1580 if (ret) 1581 goto clk_disable; 1582 } 1583 if (!np && gpio_is_valid(plat->gpio_wp)) { 1584 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1585 if (ret) 1586 goto clk_disable; 1587 } 1588 1589 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1590 DRIVER_NAME " (cmd)", host); 1591 if (ret) 1592 goto clk_disable; 1593 1594 if (!dev->irq[1]) 1595 host->singleirq = true; 1596 else { 1597 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1598 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1599 if (ret) 1600 goto clk_disable; 1601 } 1602 1603 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1604 1605 amba_set_drvdata(dev, mmc); 1606 1607 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1608 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1609 amba_rev(dev), (unsigned long long)dev->res.start, 1610 dev->irq[0], dev->irq[1]); 1611 1612 mmci_dma_setup(host); 1613 1614 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1615 pm_runtime_use_autosuspend(&dev->dev); 1616 pm_runtime_put(&dev->dev); 1617 1618 mmc_add_host(mmc); 1619 1620 return 0; 1621 1622 clk_disable: 1623 clk_disable_unprepare(host->clk); 1624 host_free: 1625 mmc_free_host(mmc); 1626 return ret; 1627} 1628 1629static int mmci_remove(struct amba_device *dev) 1630{ 1631 struct mmc_host *mmc = amba_get_drvdata(dev); 1632 1633 if (mmc) { 1634 struct mmci_host *host = mmc_priv(mmc); 1635 1636 /* 1637 * Undo pm_runtime_put() in probe. We use the _sync 1638 * version here so that we can access the primecell. 1639 */ 1640 pm_runtime_get_sync(&dev->dev); 1641 1642 mmc_remove_host(mmc); 1643 1644 writel(0, host->base + MMCIMASK0); 1645 writel(0, host->base + MMCIMASK1); 1646 1647 writel(0, host->base + MMCICOMMAND); 1648 writel(0, host->base + MMCIDATACTRL); 1649 1650 mmci_dma_release(host); 1651 clk_disable_unprepare(host->clk); 1652 mmc_free_host(mmc); 1653 } 1654 1655 return 0; 1656} 1657 1658#ifdef CONFIG_PM 1659static void mmci_save(struct mmci_host *host) 1660{ 1661 unsigned long flags; 1662 1663 spin_lock_irqsave(&host->lock, flags); 1664 1665 writel(0, host->base + MMCIMASK0); 1666 if (host->variant->pwrreg_nopower) { 1667 writel(0, host->base + MMCIDATACTRL); 1668 writel(0, host->base + MMCIPOWER); 1669 writel(0, host->base + MMCICLOCK); 1670 } 1671 mmci_reg_delay(host); 1672 1673 spin_unlock_irqrestore(&host->lock, flags); 1674} 1675 1676static void mmci_restore(struct mmci_host *host) 1677{ 1678 unsigned long flags; 1679 1680 spin_lock_irqsave(&host->lock, flags); 1681 1682 if (host->variant->pwrreg_nopower) { 1683 writel(host->clk_reg, host->base + MMCICLOCK); 1684 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1685 writel(host->pwr_reg, host->base + MMCIPOWER); 1686 } 1687 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1688 mmci_reg_delay(host); 1689 1690 spin_unlock_irqrestore(&host->lock, flags); 1691} 1692 1693static int mmci_runtime_suspend(struct device *dev) 1694{ 1695 struct amba_device *adev = to_amba_device(dev); 1696 struct mmc_host *mmc = amba_get_drvdata(adev); 1697 1698 if (mmc) { 1699 struct mmci_host *host = mmc_priv(mmc); 1700 pinctrl_pm_select_sleep_state(dev); 1701 mmci_save(host); 1702 clk_disable_unprepare(host->clk); 1703 } 1704 1705 return 0; 1706} 1707 1708static int mmci_runtime_resume(struct device *dev) 1709{ 1710 struct amba_device *adev = to_amba_device(dev); 1711 struct mmc_host *mmc = amba_get_drvdata(adev); 1712 1713 if (mmc) { 1714 struct mmci_host *host = mmc_priv(mmc); 1715 clk_prepare_enable(host->clk); 1716 mmci_restore(host); 1717 pinctrl_pm_select_default_state(dev); 1718 } 1719 1720 return 0; 1721} 1722#endif 1723 1724static const struct dev_pm_ops mmci_dev_pm_ops = { 1725 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1726 pm_runtime_force_resume) 1727 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1728}; 1729 1730static struct amba_id mmci_ids[] = { 1731 { 1732 .id = 0x00041180, 1733 .mask = 0xff0fffff, 1734 .data = &variant_arm, 1735 }, 1736 { 1737 .id = 0x01041180, 1738 .mask = 0xff0fffff, 1739 .data = &variant_arm_extended_fifo, 1740 }, 1741 { 1742 .id = 0x02041180, 1743 .mask = 0xff0fffff, 1744 .data = &variant_arm_extended_fifo_hwfc, 1745 }, 1746 { 1747 .id = 0x00041181, 1748 .mask = 0x000fffff, 1749 .data = &variant_arm, 1750 }, 1751 /* ST Micro variants */ 1752 { 1753 .id = 0x00180180, 1754 .mask = 0x00ffffff, 1755 .data = &variant_u300, 1756 }, 1757 { 1758 .id = 0x10180180, 1759 .mask = 0xf0ffffff, 1760 .data = &variant_nomadik, 1761 }, 1762 { 1763 .id = 0x00280180, 1764 .mask = 0x00ffffff, 1765 .data = &variant_u300, 1766 }, 1767 { 1768 .id = 0x00480180, 1769 .mask = 0xf0ffffff, 1770 .data = &variant_ux500, 1771 }, 1772 { 1773 .id = 0x10480180, 1774 .mask = 0xf0ffffff, 1775 .data = &variant_ux500v2, 1776 }, 1777 { 0, 0 }, 1778}; 1779 1780MODULE_DEVICE_TABLE(amba, mmci_ids); 1781 1782static struct amba_driver mmci_driver = { 1783 .drv = { 1784 .name = DRIVER_NAME, 1785 .pm = &mmci_dev_pm_ops, 1786 }, 1787 .probe = mmci_probe, 1788 .remove = mmci_remove, 1789 .id_table = mmci_ids, 1790}; 1791 1792module_amba_driver(mmci_driver); 1793 1794module_param(fmax, uint, 0444); 1795 1796MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1797MODULE_LICENSE("GPL"); 1798