mmci.c revision bb8f563c848faa113059973f68c24a3bb6a9585e 
1/*
2 *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *  Copyright (C) 2010 ST-Ericsson AB.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/highmem.h>
20#include <linux/log2.h>
21#include <linux/mmc/host.h>
22#include <linux/amba/bus.h>
23#include <linux/clk.h>
24#include <linux/scatterlist.h>
25#include <linux/gpio.h>
26#include <linux/amba/mmci.h>
27#include <linux/regulator/consumer.h>
28
29#include <asm/div64.h>
30#include <asm/io.h>
31#include <asm/sizes.h>
32
33#include "mmci.h"
34
35#define DRIVER_NAME "mmci-pl18x"
36
37static unsigned int fmax = 515633;
38
39/*
40 * This must be called with host->lock held
41 */
42static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
43{
44	u32 clk = 0;
45
46	if (desired) {
47		if (desired >= host->mclk) {
48			clk = MCI_CLK_BYPASS;
49			host->cclk = host->mclk;
50		} else {
51			clk = host->mclk / (2 * desired) - 1;
52			if (clk >= 256)
53				clk = 255;
54			host->cclk = host->mclk / (2 * (clk + 1));
55		}
56		if (host->hw_designer == AMBA_VENDOR_ST)
57			clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */
58		clk |= MCI_CLK_ENABLE;
59		/* This hasn't proven to be worthwhile */
60		/* clk |= MCI_CLK_PWRSAVE; */
61	}
62
63	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
64		clk |= MCI_4BIT_BUS;
65	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
66		clk |= MCI_ST_8BIT_BUS;
67
68	writel(clk, host->base + MMCICLOCK);
69}
70
71static void
72mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
73{
74	writel(0, host->base + MMCICOMMAND);
75
76	BUG_ON(host->data);
77
78	host->mrq = NULL;
79	host->cmd = NULL;
80
81	if (mrq->data)
82		mrq->data->bytes_xfered = host->data_xfered;
83
84	/*
85	 * Need to drop the host lock here; mmc_request_done may call
86	 * back into the driver...
87	 */
88	spin_unlock(&host->lock);
89	mmc_request_done(host->mmc, mrq);
90	spin_lock(&host->lock);
91}
92
93static void mmci_stop_data(struct mmci_host *host)
94{
95	writel(0, host->base + MMCIDATACTRL);
96	writel(0, host->base + MMCIMASK1);
97	host->data = NULL;
98}
99
100static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
101{
102	unsigned int flags = SG_MITER_ATOMIC;
103
104	if (data->flags & MMC_DATA_READ)
105		flags |= SG_MITER_TO_SG;
106	else
107		flags |= SG_MITER_FROM_SG;
108
109	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
110}
111
112static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
113{
114	unsigned int datactrl, timeout, irqmask;
115	unsigned long long clks;
116	void __iomem *base;
117	int blksz_bits;
118
119	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
120		data->blksz, data->blocks, data->flags);
121
122	host->data = data;
123	host->size = data->blksz * data->blocks;
124	host->data_xfered = 0;
125
126	mmci_init_sg(host, data);
127
128	clks = (unsigned long long)data->timeout_ns * host->cclk;
129	do_div(clks, 1000000000UL);
130
131	timeout = data->timeout_clks + (unsigned int)clks;
132
133	base = host->base;
134	writel(timeout, base + MMCIDATATIMER);
135	writel(host->size, base + MMCIDATALENGTH);
136
137	blksz_bits = ffs(data->blksz) - 1;
138	BUG_ON(1 << blksz_bits != data->blksz);
139
140	datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
141	if (data->flags & MMC_DATA_READ) {
142		datactrl |= MCI_DPSM_DIRECTION;
143		irqmask = MCI_RXFIFOHALFFULLMASK;
144
145		/*
146		 * If we have less than a FIFOSIZE of bytes to transfer,
147		 * trigger a PIO interrupt as soon as any data is available.
148		 */
149		if (host->size < MCI_FIFOSIZE)
150			irqmask |= MCI_RXDATAAVLBLMASK;
151	} else {
152		/*
153		 * We don't actually need to include "FIFO empty" here
154		 * since its implicit in "FIFO half empty".
155		 */
156		irqmask = MCI_TXFIFOHALFEMPTYMASK;
157	}
158
159	writel(datactrl, base + MMCIDATACTRL);
160	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
161	writel(irqmask, base + MMCIMASK1);
162}
163
164static void
165mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
166{
167	void __iomem *base = host->base;
168
169	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
170	    cmd->opcode, cmd->arg, cmd->flags);
171
172	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
173		writel(0, base + MMCICOMMAND);
174		udelay(1);
175	}
176
177	c |= cmd->opcode | MCI_CPSM_ENABLE;
178	if (cmd->flags & MMC_RSP_PRESENT) {
179		if (cmd->flags & MMC_RSP_136)
180			c |= MCI_CPSM_LONGRSP;
181		c |= MCI_CPSM_RESPONSE;
182	}
183	if (/*interrupt*/0)
184		c |= MCI_CPSM_INTERRUPT;
185
186	host->cmd = cmd;
187
188	writel(cmd->arg, base + MMCIARGUMENT);
189	writel(c, base + MMCICOMMAND);
190}
191
192static void
193mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
194	      unsigned int status)
195{
196	if (status & MCI_DATABLOCKEND) {
197		host->data_xfered += data->blksz;
198#ifdef CONFIG_ARCH_U300
199		/*
200		 * On the U300 some signal or other is
201		 * badly routed so that a data write does
202		 * not properly terminate with a MCI_DATAEND
203		 * status flag. This quirk will make writes
204		 * work again.
205		 */
206		if (data->flags & MMC_DATA_WRITE)
207			status |= MCI_DATAEND;
208#endif
209	}
210	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
211		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status);
212		if (status & MCI_DATACRCFAIL)
213			data->error = -EILSEQ;
214		else if (status & MCI_DATATIMEOUT)
215			data->error = -ETIMEDOUT;
216		else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
217			data->error = -EIO;
218		status |= MCI_DATAEND;
219
220		/*
221		 * We hit an error condition.  Ensure that any data
222		 * partially written to a page is properly coherent.
223		 */
224		if (data->flags & MMC_DATA_READ) {
225			struct sg_mapping_iter *sg_miter = &host->sg_miter;
226			unsigned long flags;
227
228			local_irq_save(flags);
229			if (sg_miter_next(sg_miter)) {
230				flush_dcache_page(sg_miter->page);
231				sg_miter_stop(sg_miter);
232			}
233			local_irq_restore(flags);
234		}
235	}
236	if (status & MCI_DATAEND) {
237		mmci_stop_data(host);
238
239		if (!data->stop) {
240			mmci_request_end(host, data->mrq);
241		} else {
242			mmci_start_command(host, data->stop, 0);
243		}
244	}
245}
246
247static void
248mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
249	     unsigned int status)
250{
251	void __iomem *base = host->base;
252
253	host->cmd = NULL;
254
255	cmd->resp[0] = readl(base + MMCIRESPONSE0);
256	cmd->resp[1] = readl(base + MMCIRESPONSE1);
257	cmd->resp[2] = readl(base + MMCIRESPONSE2);
258	cmd->resp[3] = readl(base + MMCIRESPONSE3);
259
260	if (status & MCI_CMDTIMEOUT) {
261		cmd->error = -ETIMEDOUT;
262	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
263		cmd->error = -EILSEQ;
264	}
265
266	if (!cmd->data || cmd->error) {
267		if (host->data)
268			mmci_stop_data(host);
269		mmci_request_end(host, cmd->mrq);
270	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
271		mmci_start_data(host, cmd->data);
272	}
273}
274
275static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
276{
277	void __iomem *base = host->base;
278	char *ptr = buffer;
279	u32 status;
280	int host_remain = host->size;
281
282	do {
283		int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
284
285		if (count > remain)
286			count = remain;
287
288		if (count <= 0)
289			break;
290
291		readsl(base + MMCIFIFO, ptr, count >> 2);
292
293		ptr += count;
294		remain -= count;
295		host_remain -= count;
296
297		if (remain == 0)
298			break;
299
300		status = readl(base + MMCISTATUS);
301	} while (status & MCI_RXDATAAVLBL);
302
303	return ptr - buffer;
304}
305
306static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
307{
308	void __iomem *base = host->base;
309	char *ptr = buffer;
310
311	do {
312		unsigned int count, maxcnt;
313
314		maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
315		count = min(remain, maxcnt);
316
317		writesl(base + MMCIFIFO, ptr, count >> 2);
318
319		ptr += count;
320		remain -= count;
321
322		if (remain == 0)
323			break;
324
325		status = readl(base + MMCISTATUS);
326	} while (status & MCI_TXFIFOHALFEMPTY);
327
328	return ptr - buffer;
329}
330
331/*
332 * PIO data transfer IRQ handler.
333 */
334static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
335{
336	struct mmci_host *host = dev_id;
337	struct sg_mapping_iter *sg_miter = &host->sg_miter;
338	void __iomem *base = host->base;
339	unsigned long flags;
340	u32 status;
341
342	status = readl(base + MMCISTATUS);
343
344	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
345
346	local_irq_save(flags);
347
348	do {
349		unsigned int remain, len;
350		char *buffer;
351
352		/*
353		 * For write, we only need to test the half-empty flag
354		 * here - if the FIFO is completely empty, then by
355		 * definition it is more than half empty.
356		 *
357		 * For read, check for data available.
358		 */
359		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
360			break;
361
362		if (!sg_miter_next(sg_miter))
363			break;
364
365		buffer = sg_miter->addr;
366		remain = sg_miter->length;
367
368		len = 0;
369		if (status & MCI_RXACTIVE)
370			len = mmci_pio_read(host, buffer, remain);
371		if (status & MCI_TXACTIVE)
372			len = mmci_pio_write(host, buffer, remain, status);
373
374		sg_miter->consumed = len;
375
376		host->size -= len;
377		remain -= len;
378
379		if (remain)
380			break;
381
382		if (status & MCI_RXACTIVE)
383			flush_dcache_page(sg_miter->page);
384
385		status = readl(base + MMCISTATUS);
386	} while (1);
387
388	sg_miter_stop(sg_miter);
389
390	local_irq_restore(flags);
391
392	/*
393	 * If we're nearing the end of the read, switch to
394	 * "any data available" mode.
395	 */
396	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
397		writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
398
399	/*
400	 * If we run out of data, disable the data IRQs; this
401	 * prevents a race where the FIFO becomes empty before
402	 * the chip itself has disabled the data path, and
403	 * stops us racing with our data end IRQ.
404	 */
405	if (host->size == 0) {
406		writel(0, base + MMCIMASK1);
407		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
408	}
409
410	return IRQ_HANDLED;
411}
412
413/*
414 * Handle completion of command and data transfers.
415 */
416static irqreturn_t mmci_irq(int irq, void *dev_id)
417{
418	struct mmci_host *host = dev_id;
419	u32 status;
420	int ret = 0;
421
422	spin_lock(&host->lock);
423
424	do {
425		struct mmc_command *cmd;
426		struct mmc_data *data;
427
428		status = readl(host->base + MMCISTATUS);
429		status &= readl(host->base + MMCIMASK0);
430		writel(status, host->base + MMCICLEAR);
431
432		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
433
434		data = host->data;
435		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
436			      MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
437			mmci_data_irq(host, data, status);
438
439		cmd = host->cmd;
440		if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
441			mmci_cmd_irq(host, cmd, status);
442
443		ret = 1;
444	} while (status);
445
446	spin_unlock(&host->lock);
447
448	return IRQ_RETVAL(ret);
449}
450
451static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
452{
453	struct mmci_host *host = mmc_priv(mmc);
454	unsigned long flags;
455
456	WARN_ON(host->mrq != NULL);
457
458	if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
459		dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
460			mrq->data->blksz);
461		mrq->cmd->error = -EINVAL;
462		mmc_request_done(mmc, mrq);
463		return;
464	}
465
466	spin_lock_irqsave(&host->lock, flags);
467
468	host->mrq = mrq;
469
470	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
471		mmci_start_data(host, mrq->data);
472
473	mmci_start_command(host, mrq->cmd, 0);
474
475	spin_unlock_irqrestore(&host->lock, flags);
476}
477
478static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
479{
480	struct mmci_host *host = mmc_priv(mmc);
481	u32 pwr = 0;
482	unsigned long flags;
483
484	switch (ios->power_mode) {
485	case MMC_POWER_OFF:
486		if(host->vcc &&
487		   regulator_is_enabled(host->vcc))
488			regulator_disable(host->vcc);
489		break;
490	case MMC_POWER_UP:
491#ifdef CONFIG_REGULATOR
492		if (host->vcc)
493			/* This implicitly enables the regulator */
494			mmc_regulator_set_ocr(host->vcc, ios->vdd);
495#endif
496		if (host->plat->vdd_handler)
497			pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
498						       ios->power_mode);
499		/* The ST version does not have this, fall through to POWER_ON */
500		if (host->hw_designer != AMBA_VENDOR_ST) {
501			pwr |= MCI_PWR_UP;
502			break;
503		}
504	case MMC_POWER_ON:
505		pwr |= MCI_PWR_ON;
506		break;
507	}
508
509	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
510		if (host->hw_designer != AMBA_VENDOR_ST)
511			pwr |= MCI_ROD;
512		else {
513			/*
514			 * The ST Micro variant use the ROD bit for something
515			 * else and only has OD (Open Drain).
516			 */
517			pwr |= MCI_OD;
518		}
519	}
520
521	spin_lock_irqsave(&host->lock, flags);
522
523	mmci_set_clkreg(host, ios->clock);
524
525	if (host->pwr != pwr) {
526		host->pwr = pwr;
527		writel(pwr, host->base + MMCIPOWER);
528	}
529
530	spin_unlock_irqrestore(&host->lock, flags);
531}
532
533static int mmci_get_ro(struct mmc_host *mmc)
534{
535	struct mmci_host *host = mmc_priv(mmc);
536
537	if (host->gpio_wp == -ENOSYS)
538		return -ENOSYS;
539
540	return gpio_get_value(host->gpio_wp);
541}
542
543static int mmci_get_cd(struct mmc_host *mmc)
544{
545	struct mmci_host *host = mmc_priv(mmc);
546	unsigned int status;
547
548	if (host->gpio_cd == -ENOSYS)
549		status = host->plat->status(mmc_dev(host->mmc));
550	else
551		status = gpio_get_value(host->gpio_cd);
552
553	return !status;
554}
555
556static const struct mmc_host_ops mmci_ops = {
557	.request	= mmci_request,
558	.set_ios	= mmci_set_ios,
559	.get_ro		= mmci_get_ro,
560	.get_cd		= mmci_get_cd,
561};
562
563static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
564{
565	struct mmci_platform_data *plat = dev->dev.platform_data;
566	struct mmci_host *host;
567	struct mmc_host *mmc;
568	int ret;
569
570	/* must have platform data */
571	if (!plat) {
572		ret = -EINVAL;
573		goto out;
574	}
575
576	ret = amba_request_regions(dev, DRIVER_NAME);
577	if (ret)
578		goto out;
579
580	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
581	if (!mmc) {
582		ret = -ENOMEM;
583		goto rel_regions;
584	}
585
586	host = mmc_priv(mmc);
587	host->mmc = mmc;
588
589	host->gpio_wp = -ENOSYS;
590	host->gpio_cd = -ENOSYS;
591
592	host->hw_designer = amba_manf(dev);
593	host->hw_revision = amba_rev(dev);
594	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
595	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
596
597	host->clk = clk_get(&dev->dev, NULL);
598	if (IS_ERR(host->clk)) {
599		ret = PTR_ERR(host->clk);
600		host->clk = NULL;
601		goto host_free;
602	}
603
604	ret = clk_enable(host->clk);
605	if (ret)
606		goto clk_free;
607
608	host->plat = plat;
609	host->mclk = clk_get_rate(host->clk);
610	/*
611	 * According to the spec, mclk is max 100 MHz,
612	 * so we try to adjust the clock down to this,
613	 * (if possible).
614	 */
615	if (host->mclk > 100000000) {
616		ret = clk_set_rate(host->clk, 100000000);
617		if (ret < 0)
618			goto clk_disable;
619		host->mclk = clk_get_rate(host->clk);
620		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
621			host->mclk);
622	}
623	host->base = ioremap(dev->res.start, resource_size(&dev->res));
624	if (!host->base) {
625		ret = -ENOMEM;
626		goto clk_disable;
627	}
628
629	mmc->ops = &mmci_ops;
630	mmc->f_min = (host->mclk + 511) / 512;
631	/*
632	 * If the platform data supplies a maximum operating
633	 * frequency, this takes precedence. Else, we fall back
634	 * to using the module parameter, which has a (low)
635	 * default value in case it is not specified. Either
636	 * value must not exceed the clock rate into the block,
637	 * of course.
638	 */
639	if (plat->f_max)
640		mmc->f_max = min(host->mclk, plat->f_max);
641	else
642		mmc->f_max = min(host->mclk, fmax);
643	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
644
645#ifdef CONFIG_REGULATOR
646	/* If we're using the regulator framework, try to fetch a regulator */
647	host->vcc = regulator_get(&dev->dev, "vmmc");
648	if (IS_ERR(host->vcc))
649		host->vcc = NULL;
650	else {
651		int mask = mmc_regulator_get_ocrmask(host->vcc);
652
653		if (mask < 0)
654			dev_err(&dev->dev, "error getting OCR mask (%d)\n",
655				mask);
656		else {
657			host->mmc->ocr_avail = (u32) mask;
658			if (plat->ocr_mask)
659				dev_warn(&dev->dev,
660				 "Provided ocr_mask/setpower will not be used "
661				 "(using regulator instead)\n");
662		}
663	}
664#endif
665	/* Fall back to platform data if no regulator is found */
666	if (host->vcc == NULL)
667		mmc->ocr_avail = plat->ocr_mask;
668	mmc->caps = plat->capabilities;
669	mmc->caps |= MMC_CAP_NEEDS_POLL;
670
671	/*
672	 * We can do SGIO
673	 */
674	mmc->max_hw_segs = 16;
675	mmc->max_phys_segs = NR_SG;
676
677	/*
678	 * Since we only have a 16-bit data length register, we must
679	 * ensure that we don't exceed 2^16-1 bytes in a single request.
680	 */
681	mmc->max_req_size = 65535;
682
683	/*
684	 * Set the maximum segment size.  Since we aren't doing DMA
685	 * (yet) we are only limited by the data length register.
686	 */
687	mmc->max_seg_size = mmc->max_req_size;
688
689	/*
690	 * Block size can be up to 2048 bytes, but must be a power of two.
691	 */
692	mmc->max_blk_size = 2048;
693
694	/*
695	 * No limit on the number of blocks transferred.
696	 */
697	mmc->max_blk_count = mmc->max_req_size;
698
699	spin_lock_init(&host->lock);
700
701	writel(0, host->base + MMCIMASK0);
702	writel(0, host->base + MMCIMASK1);
703	writel(0xfff, host->base + MMCICLEAR);
704
705	if (gpio_is_valid(plat->gpio_cd)) {
706		ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
707		if (ret == 0)
708			ret = gpio_direction_input(plat->gpio_cd);
709		if (ret == 0)
710			host->gpio_cd = plat->gpio_cd;
711		else if (ret != -ENOSYS)
712			goto err_gpio_cd;
713	}
714	if (gpio_is_valid(plat->gpio_wp)) {
715		ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
716		if (ret == 0)
717			ret = gpio_direction_input(plat->gpio_wp);
718		if (ret == 0)
719			host->gpio_wp = plat->gpio_wp;
720		else if (ret != -ENOSYS)
721			goto err_gpio_wp;
722	}
723
724	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
725	if (ret)
726		goto unmap;
727
728	ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
729	if (ret)
730		goto irq0_free;
731
732	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
733
734	amba_set_drvdata(dev, mmc);
735
736	mmc_add_host(mmc);
737
738	dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
739		mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
740		(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
741
742	return 0;
743
744 irq0_free:
745	free_irq(dev->irq[0], host);
746 unmap:
747	if (host->gpio_wp != -ENOSYS)
748		gpio_free(host->gpio_wp);
749 err_gpio_wp:
750	if (host->gpio_cd != -ENOSYS)
751		gpio_free(host->gpio_cd);
752 err_gpio_cd:
753	iounmap(host->base);
754 clk_disable:
755	clk_disable(host->clk);
756 clk_free:
757	clk_put(host->clk);
758 host_free:
759	mmc_free_host(mmc);
760 rel_regions:
761	amba_release_regions(dev);
762 out:
763	return ret;
764}
765
766static int __devexit mmci_remove(struct amba_device *dev)
767{
768	struct mmc_host *mmc = amba_get_drvdata(dev);
769
770	amba_set_drvdata(dev, NULL);
771
772	if (mmc) {
773		struct mmci_host *host = mmc_priv(mmc);
774
775		mmc_remove_host(mmc);
776
777		writel(0, host->base + MMCIMASK0);
778		writel(0, host->base + MMCIMASK1);
779
780		writel(0, host->base + MMCICOMMAND);
781		writel(0, host->base + MMCIDATACTRL);
782
783		free_irq(dev->irq[0], host);
784		free_irq(dev->irq[1], host);
785
786		if (host->gpio_wp != -ENOSYS)
787			gpio_free(host->gpio_wp);
788		if (host->gpio_cd != -ENOSYS)
789			gpio_free(host->gpio_cd);
790
791		iounmap(host->base);
792		clk_disable(host->clk);
793		clk_put(host->clk);
794
795		if (regulator_is_enabled(host->vcc))
796			regulator_disable(host->vcc);
797		regulator_put(host->vcc);
798
799		mmc_free_host(mmc);
800
801		amba_release_regions(dev);
802	}
803
804	return 0;
805}
806
807#ifdef CONFIG_PM
808static int mmci_suspend(struct amba_device *dev, pm_message_t state)
809{
810	struct mmc_host *mmc = amba_get_drvdata(dev);
811	int ret = 0;
812
813	if (mmc) {
814		struct mmci_host *host = mmc_priv(mmc);
815
816		ret = mmc_suspend_host(mmc);
817		if (ret == 0)
818			writel(0, host->base + MMCIMASK0);
819	}
820
821	return ret;
822}
823
824static int mmci_resume(struct amba_device *dev)
825{
826	struct mmc_host *mmc = amba_get_drvdata(dev);
827	int ret = 0;
828
829	if (mmc) {
830		struct mmci_host *host = mmc_priv(mmc);
831
832		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
833
834		ret = mmc_resume_host(mmc);
835	}
836
837	return ret;
838}
839#else
840#define mmci_suspend	NULL
841#define mmci_resume	NULL
842#endif
843
844static struct amba_id mmci_ids[] = {
845	{
846		.id	= 0x00041180,
847		.mask	= 0x000fffff,
848	},
849	{
850		.id	= 0x00041181,
851		.mask	= 0x000fffff,
852	},
853	/* ST Micro variants */
854	{
855		.id     = 0x00180180,
856		.mask   = 0x00ffffff,
857	},
858	{
859		.id     = 0x00280180,
860		.mask   = 0x00ffffff,
861	},
862	{ 0, 0 },
863};
864
865static struct amba_driver mmci_driver = {
866	.drv		= {
867		.name	= DRIVER_NAME,
868	},
869	.probe		= mmci_probe,
870	.remove		= __devexit_p(mmci_remove),
871	.suspend	= mmci_suspend,
872	.resume		= mmci_resume,
873	.id_table	= mmci_ids,
874};
875
876static int __init mmci_init(void)
877{
878	return amba_driver_register(&mmci_driver);
879}
880
881static void __exit mmci_exit(void)
882{
883	amba_driver_unregister(&mmci_driver);
884}
885
886module_init(mmci_init);
887module_exit(mmci_exit);
888module_param(fmax, uint, 0444);
889
890MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
891MODULE_LICENSE("GPL");
892