mmci.c revision c0a120a4bc68f5dc5f5238e76013cc18bac0ffed
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/highmem.h> 22#include <linux/log2.h> 23#include <linux/mmc/host.h> 24#include <linux/mmc/card.h> 25#include <linux/amba/bus.h> 26#include <linux/clk.h> 27#include <linux/scatterlist.h> 28#include <linux/gpio.h> 29#include <linux/of_gpio.h> 30#include <linux/regulator/consumer.h> 31#include <linux/dmaengine.h> 32#include <linux/dma-mapping.h> 33#include <linux/amba/mmci.h> 34#include <linux/pm_runtime.h> 35#include <linux/types.h> 36 37#include <asm/div64.h> 38#include <asm/io.h> 39#include <asm/sizes.h> 40 41#include "mmci.h" 42 43#define DRIVER_NAME "mmci-pl18x" 44 45static unsigned int fmax = 515633; 46 47/** 48 * struct variant_data - MMCI variant-specific quirks 49 * @clkreg: default value for MCICLOCK register 50 * @clkreg_enable: enable value for MMCICLOCK register 51 * @datalength_bits: number of bits in the MMCIDATALENGTH register 52 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 53 * is asserted (likewise for RX) 54 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 55 * is asserted (likewise for RX) 56 * @sdio: variant supports SDIO 57 * @st_clkdiv: true if using a ST-specific clock divider algorithm 58 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 59 * @pwrreg_powerup: power up value for MMCIPOWER register 60 * @signal_direction: input/out direction of bus signals can be indicated 61 */ 62struct variant_data { 63 unsigned int clkreg; 64 unsigned int clkreg_enable; 65 unsigned int datalength_bits; 66 unsigned int fifosize; 67 unsigned int fifohalfsize; 68 bool sdio; 69 bool st_clkdiv; 70 bool blksz_datactrl16; 71 u32 pwrreg_powerup; 72 bool signal_direction; 73}; 74 75static struct variant_data variant_arm = { 76 .fifosize = 16 * 4, 77 .fifohalfsize = 8 * 4, 78 .datalength_bits = 16, 79 .pwrreg_powerup = MCI_PWR_UP, 80}; 81 82static struct variant_data variant_arm_extended_fifo = { 83 .fifosize = 128 * 4, 84 .fifohalfsize = 64 * 4, 85 .datalength_bits = 16, 86 .pwrreg_powerup = MCI_PWR_UP, 87}; 88 89static struct variant_data variant_u300 = { 90 .fifosize = 16 * 4, 91 .fifohalfsize = 8 * 4, 92 .clkreg_enable = MCI_ST_U300_HWFCEN, 93 .datalength_bits = 16, 94 .sdio = true, 95 .pwrreg_powerup = MCI_PWR_ON, 96 .signal_direction = true, 97}; 98 99static struct variant_data variant_ux500 = { 100 .fifosize = 30 * 4, 101 .fifohalfsize = 8 * 4, 102 .clkreg = MCI_CLK_ENABLE, 103 .clkreg_enable = MCI_ST_UX500_HWFCEN, 104 .datalength_bits = 24, 105 .sdio = true, 106 .st_clkdiv = true, 107 .pwrreg_powerup = MCI_PWR_ON, 108 .signal_direction = true, 109}; 110 111static struct variant_data variant_ux500v2 = { 112 .fifosize = 30 * 4, 113 .fifohalfsize = 8 * 4, 114 .clkreg = MCI_CLK_ENABLE, 115 .clkreg_enable = MCI_ST_UX500_HWFCEN, 116 .datalength_bits = 24, 117 .sdio = true, 118 .st_clkdiv = true, 119 .blksz_datactrl16 = true, 120 .pwrreg_powerup = MCI_PWR_ON, 121 .signal_direction = true, 122}; 123 124/* 125 * This must be called with host->lock held 126 */ 127static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 128{ 129 if (host->clk_reg != clk) { 130 host->clk_reg = clk; 131 writel(clk, host->base + MMCICLOCK); 132 } 133} 134 135/* 136 * This must be called with host->lock held 137 */ 138static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 139{ 140 if (host->pwr_reg != pwr) { 141 host->pwr_reg = pwr; 142 writel(pwr, host->base + MMCIPOWER); 143 } 144} 145 146/* 147 * This must be called with host->lock held 148 */ 149static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 150{ 151 struct variant_data *variant = host->variant; 152 u32 clk = variant->clkreg; 153 154 if (desired) { 155 if (desired >= host->mclk) { 156 clk = MCI_CLK_BYPASS; 157 if (variant->st_clkdiv) 158 clk |= MCI_ST_UX500_NEG_EDGE; 159 host->cclk = host->mclk; 160 } else if (variant->st_clkdiv) { 161 /* 162 * DB8500 TRM says f = mclk / (clkdiv + 2) 163 * => clkdiv = (mclk / f) - 2 164 * Round the divider up so we don't exceed the max 165 * frequency 166 */ 167 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 168 if (clk >= 256) 169 clk = 255; 170 host->cclk = host->mclk / (clk + 2); 171 } else { 172 /* 173 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 174 * => clkdiv = mclk / (2 * f) - 1 175 */ 176 clk = host->mclk / (2 * desired) - 1; 177 if (clk >= 256) 178 clk = 255; 179 host->cclk = host->mclk / (2 * (clk + 1)); 180 } 181 182 clk |= variant->clkreg_enable; 183 clk |= MCI_CLK_ENABLE; 184 /* This hasn't proven to be worthwhile */ 185 /* clk |= MCI_CLK_PWRSAVE; */ 186 } 187 188 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 189 clk |= MCI_4BIT_BUS; 190 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 191 clk |= MCI_ST_8BIT_BUS; 192 193 mmci_write_clkreg(host, clk); 194} 195 196static void 197mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 198{ 199 writel(0, host->base + MMCICOMMAND); 200 201 BUG_ON(host->data); 202 203 host->mrq = NULL; 204 host->cmd = NULL; 205 206 mmc_request_done(host->mmc, mrq); 207 208 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 209 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 210} 211 212static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 213{ 214 void __iomem *base = host->base; 215 216 if (host->singleirq) { 217 unsigned int mask0 = readl(base + MMCIMASK0); 218 219 mask0 &= ~MCI_IRQ1MASK; 220 mask0 |= mask; 221 222 writel(mask0, base + MMCIMASK0); 223 } 224 225 writel(mask, base + MMCIMASK1); 226} 227 228static void mmci_stop_data(struct mmci_host *host) 229{ 230 writel(0, host->base + MMCIDATACTRL); 231 mmci_set_mask1(host, 0); 232 host->data = NULL; 233} 234 235static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 236{ 237 unsigned int flags = SG_MITER_ATOMIC; 238 239 if (data->flags & MMC_DATA_READ) 240 flags |= SG_MITER_TO_SG; 241 else 242 flags |= SG_MITER_FROM_SG; 243 244 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 245} 246 247/* 248 * All the DMA operation mode stuff goes inside this ifdef. 249 * This assumes that you have a generic DMA device interface, 250 * no custom DMA interfaces are supported. 251 */ 252#ifdef CONFIG_DMA_ENGINE 253static void __devinit mmci_dma_setup(struct mmci_host *host) 254{ 255 struct mmci_platform_data *plat = host->plat; 256 const char *rxname, *txname; 257 dma_cap_mask_t mask; 258 259 if (!plat || !plat->dma_filter) { 260 dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); 261 return; 262 } 263 264 /* initialize pre request cookie */ 265 host->next_data.cookie = 1; 266 267 /* Try to acquire a generic DMA engine slave channel */ 268 dma_cap_zero(mask); 269 dma_cap_set(DMA_SLAVE, mask); 270 271 /* 272 * If only an RX channel is specified, the driver will 273 * attempt to use it bidirectionally, however if it is 274 * is specified but cannot be located, DMA will be disabled. 275 */ 276 if (plat->dma_rx_param) { 277 host->dma_rx_channel = dma_request_channel(mask, 278 plat->dma_filter, 279 plat->dma_rx_param); 280 /* E.g if no DMA hardware is present */ 281 if (!host->dma_rx_channel) 282 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 283 } 284 285 if (plat->dma_tx_param) { 286 host->dma_tx_channel = dma_request_channel(mask, 287 plat->dma_filter, 288 plat->dma_tx_param); 289 if (!host->dma_tx_channel) 290 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 291 } else { 292 host->dma_tx_channel = host->dma_rx_channel; 293 } 294 295 if (host->dma_rx_channel) 296 rxname = dma_chan_name(host->dma_rx_channel); 297 else 298 rxname = "none"; 299 300 if (host->dma_tx_channel) 301 txname = dma_chan_name(host->dma_tx_channel); 302 else 303 txname = "none"; 304 305 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 306 rxname, txname); 307 308 /* 309 * Limit the maximum segment size in any SG entry according to 310 * the parameters of the DMA engine device. 311 */ 312 if (host->dma_tx_channel) { 313 struct device *dev = host->dma_tx_channel->device->dev; 314 unsigned int max_seg_size = dma_get_max_seg_size(dev); 315 316 if (max_seg_size < host->mmc->max_seg_size) 317 host->mmc->max_seg_size = max_seg_size; 318 } 319 if (host->dma_rx_channel) { 320 struct device *dev = host->dma_rx_channel->device->dev; 321 unsigned int max_seg_size = dma_get_max_seg_size(dev); 322 323 if (max_seg_size < host->mmc->max_seg_size) 324 host->mmc->max_seg_size = max_seg_size; 325 } 326} 327 328/* 329 * This is used in __devinit or __devexit so inline it 330 * so it can be discarded. 331 */ 332static inline void mmci_dma_release(struct mmci_host *host) 333{ 334 struct mmci_platform_data *plat = host->plat; 335 336 if (host->dma_rx_channel) 337 dma_release_channel(host->dma_rx_channel); 338 if (host->dma_tx_channel && plat->dma_tx_param) 339 dma_release_channel(host->dma_tx_channel); 340 host->dma_rx_channel = host->dma_tx_channel = NULL; 341} 342 343static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 344{ 345 struct dma_chan *chan = host->dma_current; 346 enum dma_data_direction dir; 347 u32 status; 348 int i; 349 350 /* Wait up to 1ms for the DMA to complete */ 351 for (i = 0; ; i++) { 352 status = readl(host->base + MMCISTATUS); 353 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 354 break; 355 udelay(10); 356 } 357 358 /* 359 * Check to see whether we still have some data left in the FIFO - 360 * this catches DMA controllers which are unable to monitor the 361 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 362 * contiguous buffers. On TX, we'll get a FIFO underrun error. 363 */ 364 if (status & MCI_RXDATAAVLBLMASK) { 365 dmaengine_terminate_all(chan); 366 if (!data->error) 367 data->error = -EIO; 368 } 369 370 if (data->flags & MMC_DATA_WRITE) { 371 dir = DMA_TO_DEVICE; 372 } else { 373 dir = DMA_FROM_DEVICE; 374 } 375 376 if (!data->host_cookie) 377 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 378 379 /* 380 * Use of DMA with scatter-gather is impossible. 381 * Give up with DMA and switch back to PIO mode. 382 */ 383 if (status & MCI_RXDATAAVLBLMASK) { 384 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 385 mmci_dma_release(host); 386 } 387} 388 389static void mmci_dma_data_error(struct mmci_host *host) 390{ 391 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 392 dmaengine_terminate_all(host->dma_current); 393} 394 395static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 396 struct mmci_host_next *next) 397{ 398 struct variant_data *variant = host->variant; 399 struct dma_slave_config conf = { 400 .src_addr = host->phybase + MMCIFIFO, 401 .dst_addr = host->phybase + MMCIFIFO, 402 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 403 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 404 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 405 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 406 .device_fc = false, 407 }; 408 struct dma_chan *chan; 409 struct dma_device *device; 410 struct dma_async_tx_descriptor *desc; 411 enum dma_data_direction buffer_dirn; 412 int nr_sg; 413 414 /* Check if next job is already prepared */ 415 if (data->host_cookie && !next && 416 host->dma_current && host->dma_desc_current) 417 return 0; 418 419 if (!next) { 420 host->dma_current = NULL; 421 host->dma_desc_current = NULL; 422 } 423 424 if (data->flags & MMC_DATA_READ) { 425 conf.direction = DMA_DEV_TO_MEM; 426 buffer_dirn = DMA_FROM_DEVICE; 427 chan = host->dma_rx_channel; 428 } else { 429 conf.direction = DMA_MEM_TO_DEV; 430 buffer_dirn = DMA_TO_DEVICE; 431 chan = host->dma_tx_channel; 432 } 433 434 /* If there's no DMA channel, fall back to PIO */ 435 if (!chan) 436 return -EINVAL; 437 438 /* If less than or equal to the fifo size, don't bother with DMA */ 439 if (data->blksz * data->blocks <= variant->fifosize) 440 return -EINVAL; 441 442 device = chan->device; 443 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 444 if (nr_sg == 0) 445 return -EINVAL; 446 447 dmaengine_slave_config(chan, &conf); 448 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 449 conf.direction, DMA_CTRL_ACK); 450 if (!desc) 451 goto unmap_exit; 452 453 if (next) { 454 next->dma_chan = chan; 455 next->dma_desc = desc; 456 } else { 457 host->dma_current = chan; 458 host->dma_desc_current = desc; 459 } 460 461 return 0; 462 463 unmap_exit: 464 if (!next) 465 dmaengine_terminate_all(chan); 466 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 467 return -ENOMEM; 468} 469 470static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 471{ 472 int ret; 473 struct mmc_data *data = host->data; 474 475 ret = mmci_dma_prep_data(host, host->data, NULL); 476 if (ret) 477 return ret; 478 479 /* Okay, go for it. */ 480 dev_vdbg(mmc_dev(host->mmc), 481 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 482 data->sg_len, data->blksz, data->blocks, data->flags); 483 dmaengine_submit(host->dma_desc_current); 484 dma_async_issue_pending(host->dma_current); 485 486 datactrl |= MCI_DPSM_DMAENABLE; 487 488 /* Trigger the DMA transfer */ 489 writel(datactrl, host->base + MMCIDATACTRL); 490 491 /* 492 * Let the MMCI say when the data is ended and it's time 493 * to fire next DMA request. When that happens, MMCI will 494 * call mmci_data_end() 495 */ 496 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 497 host->base + MMCIMASK0); 498 return 0; 499} 500 501static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 502{ 503 struct mmci_host_next *next = &host->next_data; 504 505 if (data->host_cookie && data->host_cookie != next->cookie) { 506 pr_warning("[%s] invalid cookie: data->host_cookie %d" 507 " host->next_data.cookie %d\n", 508 __func__, data->host_cookie, host->next_data.cookie); 509 data->host_cookie = 0; 510 } 511 512 if (!data->host_cookie) 513 return; 514 515 host->dma_desc_current = next->dma_desc; 516 host->dma_current = next->dma_chan; 517 518 next->dma_desc = NULL; 519 next->dma_chan = NULL; 520} 521 522static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 523 bool is_first_req) 524{ 525 struct mmci_host *host = mmc_priv(mmc); 526 struct mmc_data *data = mrq->data; 527 struct mmci_host_next *nd = &host->next_data; 528 529 if (!data) 530 return; 531 532 if (data->host_cookie) { 533 data->host_cookie = 0; 534 return; 535 } 536 537 /* if config for dma */ 538 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || 539 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { 540 if (mmci_dma_prep_data(host, data, nd)) 541 data->host_cookie = 0; 542 else 543 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 544 } 545} 546 547static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 548 int err) 549{ 550 struct mmci_host *host = mmc_priv(mmc); 551 struct mmc_data *data = mrq->data; 552 struct dma_chan *chan; 553 enum dma_data_direction dir; 554 555 if (!data) 556 return; 557 558 if (data->flags & MMC_DATA_READ) { 559 dir = DMA_FROM_DEVICE; 560 chan = host->dma_rx_channel; 561 } else { 562 dir = DMA_TO_DEVICE; 563 chan = host->dma_tx_channel; 564 } 565 566 567 /* if config for dma */ 568 if (chan) { 569 if (err) 570 dmaengine_terminate_all(chan); 571 if (data->host_cookie) 572 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 573 data->sg_len, dir); 574 mrq->data->host_cookie = 0; 575 } 576} 577 578#else 579/* Blank functions if the DMA engine is not available */ 580static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 581{ 582} 583static inline void mmci_dma_setup(struct mmci_host *host) 584{ 585} 586 587static inline void mmci_dma_release(struct mmci_host *host) 588{ 589} 590 591static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 592{ 593} 594 595static inline void mmci_dma_data_error(struct mmci_host *host) 596{ 597} 598 599static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 600{ 601 return -ENOSYS; 602} 603 604#define mmci_pre_request NULL 605#define mmci_post_request NULL 606 607#endif 608 609static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 610{ 611 struct variant_data *variant = host->variant; 612 unsigned int datactrl, timeout, irqmask; 613 unsigned long long clks; 614 void __iomem *base; 615 int blksz_bits; 616 617 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 618 data->blksz, data->blocks, data->flags); 619 620 host->data = data; 621 host->size = data->blksz * data->blocks; 622 data->bytes_xfered = 0; 623 624 clks = (unsigned long long)data->timeout_ns * host->cclk; 625 do_div(clks, 1000000000UL); 626 627 timeout = data->timeout_clks + (unsigned int)clks; 628 629 base = host->base; 630 writel(timeout, base + MMCIDATATIMER); 631 writel(host->size, base + MMCIDATALENGTH); 632 633 blksz_bits = ffs(data->blksz) - 1; 634 BUG_ON(1 << blksz_bits != data->blksz); 635 636 if (variant->blksz_datactrl16) 637 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 638 else 639 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 640 641 if (data->flags & MMC_DATA_READ) 642 datactrl |= MCI_DPSM_DIRECTION; 643 644 /* The ST Micro variants has a special bit to enable SDIO */ 645 if (variant->sdio && host->mmc->card) 646 if (mmc_card_sdio(host->mmc->card)) 647 datactrl |= MCI_ST_DPSM_SDIOEN; 648 649 /* 650 * Attempt to use DMA operation mode, if this 651 * should fail, fall back to PIO mode 652 */ 653 if (!mmci_dma_start_data(host, datactrl)) 654 return; 655 656 /* IRQ mode, map the SG list for CPU reading/writing */ 657 mmci_init_sg(host, data); 658 659 if (data->flags & MMC_DATA_READ) { 660 irqmask = MCI_RXFIFOHALFFULLMASK; 661 662 /* 663 * If we have less than the fifo 'half-full' threshold to 664 * transfer, trigger a PIO interrupt as soon as any data 665 * is available. 666 */ 667 if (host->size < variant->fifohalfsize) 668 irqmask |= MCI_RXDATAAVLBLMASK; 669 } else { 670 /* 671 * We don't actually need to include "FIFO empty" here 672 * since its implicit in "FIFO half empty". 673 */ 674 irqmask = MCI_TXFIFOHALFEMPTYMASK; 675 } 676 677 writel(datactrl, base + MMCIDATACTRL); 678 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 679 mmci_set_mask1(host, irqmask); 680} 681 682static void 683mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 684{ 685 void __iomem *base = host->base; 686 687 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 688 cmd->opcode, cmd->arg, cmd->flags); 689 690 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 691 writel(0, base + MMCICOMMAND); 692 udelay(1); 693 } 694 695 c |= cmd->opcode | MCI_CPSM_ENABLE; 696 if (cmd->flags & MMC_RSP_PRESENT) { 697 if (cmd->flags & MMC_RSP_136) 698 c |= MCI_CPSM_LONGRSP; 699 c |= MCI_CPSM_RESPONSE; 700 } 701 if (/*interrupt*/0) 702 c |= MCI_CPSM_INTERRUPT; 703 704 host->cmd = cmd; 705 706 writel(cmd->arg, base + MMCIARGUMENT); 707 writel(c, base + MMCICOMMAND); 708} 709 710static void 711mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 712 unsigned int status) 713{ 714 /* First check for errors */ 715 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 716 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 717 u32 remain, success; 718 719 /* Terminate the DMA transfer */ 720 if (dma_inprogress(host)) 721 mmci_dma_data_error(host); 722 723 /* 724 * Calculate how far we are into the transfer. Note that 725 * the data counter gives the number of bytes transferred 726 * on the MMC bus, not on the host side. On reads, this 727 * can be as much as a FIFO-worth of data ahead. This 728 * matters for FIFO overruns only. 729 */ 730 remain = readl(host->base + MMCIDATACNT); 731 success = data->blksz * data->blocks - remain; 732 733 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 734 status, success); 735 if (status & MCI_DATACRCFAIL) { 736 /* Last block was not successful */ 737 success -= 1; 738 data->error = -EILSEQ; 739 } else if (status & MCI_DATATIMEOUT) { 740 data->error = -ETIMEDOUT; 741 } else if (status & MCI_STARTBITERR) { 742 data->error = -ECOMM; 743 } else if (status & MCI_TXUNDERRUN) { 744 data->error = -EIO; 745 } else if (status & MCI_RXOVERRUN) { 746 if (success > host->variant->fifosize) 747 success -= host->variant->fifosize; 748 else 749 success = 0; 750 data->error = -EIO; 751 } 752 data->bytes_xfered = round_down(success, data->blksz); 753 } 754 755 if (status & MCI_DATABLOCKEND) 756 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 757 758 if (status & MCI_DATAEND || data->error) { 759 if (dma_inprogress(host)) 760 mmci_dma_unmap(host, data); 761 mmci_stop_data(host); 762 763 if (!data->error) 764 /* The error clause is handled above, success! */ 765 data->bytes_xfered = data->blksz * data->blocks; 766 767 if (!data->stop) { 768 mmci_request_end(host, data->mrq); 769 } else { 770 mmci_start_command(host, data->stop, 0); 771 } 772 } 773} 774 775static void 776mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 777 unsigned int status) 778{ 779 void __iomem *base = host->base; 780 781 host->cmd = NULL; 782 783 if (status & MCI_CMDTIMEOUT) { 784 cmd->error = -ETIMEDOUT; 785 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 786 cmd->error = -EILSEQ; 787 } else { 788 cmd->resp[0] = readl(base + MMCIRESPONSE0); 789 cmd->resp[1] = readl(base + MMCIRESPONSE1); 790 cmd->resp[2] = readl(base + MMCIRESPONSE2); 791 cmd->resp[3] = readl(base + MMCIRESPONSE3); 792 } 793 794 if (!cmd->data || cmd->error) { 795 if (host->data) { 796 /* Terminate the DMA transfer */ 797 if (dma_inprogress(host)) 798 mmci_dma_data_error(host); 799 mmci_stop_data(host); 800 } 801 mmci_request_end(host, cmd->mrq); 802 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 803 mmci_start_data(host, cmd->data); 804 } 805} 806 807static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 808{ 809 void __iomem *base = host->base; 810 char *ptr = buffer; 811 u32 status; 812 int host_remain = host->size; 813 814 do { 815 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 816 817 if (count > remain) 818 count = remain; 819 820 if (count <= 0) 821 break; 822 823 /* 824 * SDIO especially may want to send something that is 825 * not divisible by 4 (as opposed to card sectors 826 * etc). Therefore make sure to always read the last bytes 827 * while only doing full 32-bit reads towards the FIFO. 828 */ 829 if (unlikely(count & 0x3)) { 830 if (count < 4) { 831 unsigned char buf[4]; 832 readsl(base + MMCIFIFO, buf, 1); 833 memcpy(ptr, buf, count); 834 } else { 835 readsl(base + MMCIFIFO, ptr, count >> 2); 836 count &= ~0x3; 837 } 838 } else { 839 readsl(base + MMCIFIFO, ptr, count >> 2); 840 } 841 842 ptr += count; 843 remain -= count; 844 host_remain -= count; 845 846 if (remain == 0) 847 break; 848 849 status = readl(base + MMCISTATUS); 850 } while (status & MCI_RXDATAAVLBL); 851 852 return ptr - buffer; 853} 854 855static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 856{ 857 struct variant_data *variant = host->variant; 858 void __iomem *base = host->base; 859 char *ptr = buffer; 860 861 do { 862 unsigned int count, maxcnt; 863 864 maxcnt = status & MCI_TXFIFOEMPTY ? 865 variant->fifosize : variant->fifohalfsize; 866 count = min(remain, maxcnt); 867 868 /* 869 * The ST Micro variant for SDIO transfer sizes 870 * less then 8 bytes should have clock H/W flow 871 * control disabled. 872 */ 873 if (variant->sdio && 874 mmc_card_sdio(host->mmc->card)) { 875 u32 clk; 876 if (count < 8) 877 clk = host->clk_reg & ~variant->clkreg_enable; 878 else 879 clk = host->clk_reg | variant->clkreg_enable; 880 881 mmci_write_clkreg(host, clk); 882 } 883 884 /* 885 * SDIO especially may want to send something that is 886 * not divisible by 4 (as opposed to card sectors 887 * etc), and the FIFO only accept full 32-bit writes. 888 * So compensate by adding +3 on the count, a single 889 * byte become a 32bit write, 7 bytes will be two 890 * 32bit writes etc. 891 */ 892 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 893 894 ptr += count; 895 remain -= count; 896 897 if (remain == 0) 898 break; 899 900 status = readl(base + MMCISTATUS); 901 } while (status & MCI_TXFIFOHALFEMPTY); 902 903 return ptr - buffer; 904} 905 906/* 907 * PIO data transfer IRQ handler. 908 */ 909static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 910{ 911 struct mmci_host *host = dev_id; 912 struct sg_mapping_iter *sg_miter = &host->sg_miter; 913 struct variant_data *variant = host->variant; 914 void __iomem *base = host->base; 915 unsigned long flags; 916 u32 status; 917 918 status = readl(base + MMCISTATUS); 919 920 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 921 922 local_irq_save(flags); 923 924 do { 925 unsigned int remain, len; 926 char *buffer; 927 928 /* 929 * For write, we only need to test the half-empty flag 930 * here - if the FIFO is completely empty, then by 931 * definition it is more than half empty. 932 * 933 * For read, check for data available. 934 */ 935 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 936 break; 937 938 if (!sg_miter_next(sg_miter)) 939 break; 940 941 buffer = sg_miter->addr; 942 remain = sg_miter->length; 943 944 len = 0; 945 if (status & MCI_RXACTIVE) 946 len = mmci_pio_read(host, buffer, remain); 947 if (status & MCI_TXACTIVE) 948 len = mmci_pio_write(host, buffer, remain, status); 949 950 sg_miter->consumed = len; 951 952 host->size -= len; 953 remain -= len; 954 955 if (remain) 956 break; 957 958 status = readl(base + MMCISTATUS); 959 } while (1); 960 961 sg_miter_stop(sg_miter); 962 963 local_irq_restore(flags); 964 965 /* 966 * If we have less than the fifo 'half-full' threshold to transfer, 967 * trigger a PIO interrupt as soon as any data is available. 968 */ 969 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 970 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 971 972 /* 973 * If we run out of data, disable the data IRQs; this 974 * prevents a race where the FIFO becomes empty before 975 * the chip itself has disabled the data path, and 976 * stops us racing with our data end IRQ. 977 */ 978 if (host->size == 0) { 979 mmci_set_mask1(host, 0); 980 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 981 } 982 983 return IRQ_HANDLED; 984} 985 986/* 987 * Handle completion of command and data transfers. 988 */ 989static irqreturn_t mmci_irq(int irq, void *dev_id) 990{ 991 struct mmci_host *host = dev_id; 992 u32 status; 993 int ret = 0; 994 995 spin_lock(&host->lock); 996 997 do { 998 struct mmc_command *cmd; 999 struct mmc_data *data; 1000 1001 status = readl(host->base + MMCISTATUS); 1002 1003 if (host->singleirq) { 1004 if (status & readl(host->base + MMCIMASK1)) 1005 mmci_pio_irq(irq, dev_id); 1006 1007 status &= ~MCI_IRQ1MASK; 1008 } 1009 1010 status &= readl(host->base + MMCIMASK0); 1011 writel(status, host->base + MMCICLEAR); 1012 1013 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1014 1015 data = host->data; 1016 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1017 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1018 MCI_DATABLOCKEND) && data) 1019 mmci_data_irq(host, data, status); 1020 1021 cmd = host->cmd; 1022 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1023 mmci_cmd_irq(host, cmd, status); 1024 1025 ret = 1; 1026 } while (status); 1027 1028 spin_unlock(&host->lock); 1029 1030 return IRQ_RETVAL(ret); 1031} 1032 1033static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1034{ 1035 struct mmci_host *host = mmc_priv(mmc); 1036 unsigned long flags; 1037 1038 WARN_ON(host->mrq != NULL); 1039 1040 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1041 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 1042 mrq->data->blksz); 1043 mrq->cmd->error = -EINVAL; 1044 mmc_request_done(mmc, mrq); 1045 return; 1046 } 1047 1048 pm_runtime_get_sync(mmc_dev(mmc)); 1049 1050 spin_lock_irqsave(&host->lock, flags); 1051 1052 host->mrq = mrq; 1053 1054 if (mrq->data) 1055 mmci_get_next_data(host, mrq->data); 1056 1057 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1058 mmci_start_data(host, mrq->data); 1059 1060 mmci_start_command(host, mrq->cmd, 0); 1061 1062 spin_unlock_irqrestore(&host->lock, flags); 1063} 1064 1065static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1066{ 1067 struct mmci_host *host = mmc_priv(mmc); 1068 struct variant_data *variant = host->variant; 1069 u32 pwr = 0; 1070 unsigned long flags; 1071 int ret; 1072 1073 pm_runtime_get_sync(mmc_dev(mmc)); 1074 1075 if (host->plat->ios_handler && 1076 host->plat->ios_handler(mmc_dev(mmc), ios)) 1077 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1078 1079 switch (ios->power_mode) { 1080 case MMC_POWER_OFF: 1081 if (host->vcc) 1082 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 1083 break; 1084 case MMC_POWER_UP: 1085 if (host->vcc) { 1086 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 1087 if (ret) { 1088 dev_err(mmc_dev(mmc), "unable to set OCR\n"); 1089 /* 1090 * The .set_ios() function in the mmc_host_ops 1091 * struct return void, and failing to set the 1092 * power should be rare so we print an error 1093 * and return here. 1094 */ 1095 goto out; 1096 } 1097 } 1098 /* 1099 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1100 * and instead uses MCI_PWR_ON so apply whatever value is 1101 * configured in the variant data. 1102 */ 1103 pwr |= variant->pwrreg_powerup; 1104 1105 break; 1106 case MMC_POWER_ON: 1107 pwr |= MCI_PWR_ON; 1108 break; 1109 } 1110 1111 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1112 /* 1113 * The ST Micro variant has some additional bits 1114 * indicating signal direction for the signals in 1115 * the SD/MMC bus and feedback-clock usage. 1116 */ 1117 pwr |= host->plat->sigdir; 1118 1119 if (ios->bus_width == MMC_BUS_WIDTH_4) 1120 pwr &= ~MCI_ST_DATA74DIREN; 1121 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1122 pwr &= (~MCI_ST_DATA74DIREN & 1123 ~MCI_ST_DATA31DIREN & 1124 ~MCI_ST_DATA2DIREN); 1125 } 1126 1127 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1128 if (host->hw_designer != AMBA_VENDOR_ST) 1129 pwr |= MCI_ROD; 1130 else { 1131 /* 1132 * The ST Micro variant use the ROD bit for something 1133 * else and only has OD (Open Drain). 1134 */ 1135 pwr |= MCI_OD; 1136 } 1137 } 1138 1139 spin_lock_irqsave(&host->lock, flags); 1140 1141 mmci_set_clkreg(host, ios->clock); 1142 mmci_write_pwrreg(host, pwr); 1143 1144 spin_unlock_irqrestore(&host->lock, flags); 1145 1146 out: 1147 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1148 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1149} 1150 1151static int mmci_get_ro(struct mmc_host *mmc) 1152{ 1153 struct mmci_host *host = mmc_priv(mmc); 1154 1155 if (host->gpio_wp == -ENOSYS) 1156 return -ENOSYS; 1157 1158 return gpio_get_value_cansleep(host->gpio_wp); 1159} 1160 1161static int mmci_get_cd(struct mmc_host *mmc) 1162{ 1163 struct mmci_host *host = mmc_priv(mmc); 1164 struct mmci_platform_data *plat = host->plat; 1165 unsigned int status; 1166 1167 if (host->gpio_cd == -ENOSYS) { 1168 if (!plat->status) 1169 return 1; /* Assume always present */ 1170 1171 status = plat->status(mmc_dev(host->mmc)); 1172 } else 1173 status = !!gpio_get_value_cansleep(host->gpio_cd) 1174 ^ plat->cd_invert; 1175 1176 /* 1177 * Use positive logic throughout - status is zero for no card, 1178 * non-zero for card inserted. 1179 */ 1180 return status; 1181} 1182 1183static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1184{ 1185 struct mmci_host *host = dev_id; 1186 1187 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1188 1189 return IRQ_HANDLED; 1190} 1191 1192static const struct mmc_host_ops mmci_ops = { 1193 .request = mmci_request, 1194 .pre_req = mmci_pre_request, 1195 .post_req = mmci_post_request, 1196 .set_ios = mmci_set_ios, 1197 .get_ro = mmci_get_ro, 1198 .get_cd = mmci_get_cd, 1199}; 1200 1201#ifdef CONFIG_OF 1202static void mmci_dt_populate_generic_pdata(struct device_node *np, 1203 struct mmci_platform_data *pdata) 1204{ 1205 int bus_width = 0; 1206 1207 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1208 if (!pdata->gpio_wp) 1209 pdata->gpio_wp = -1; 1210 1211 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1212 if (!pdata->gpio_cd) 1213 pdata->gpio_cd = -1; 1214 1215 if (of_get_property(np, "cd-inverted", NULL)) 1216 pdata->cd_invert = true; 1217 else 1218 pdata->cd_invert = false; 1219 1220 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1221 if (!pdata->f_max) 1222 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1223 1224 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1225 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1226 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1227 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1228 1229 of_property_read_u32(np, "bus-width", &bus_width); 1230 switch (bus_width) { 1231 case 0 : 1232 /* No bus-width supplied. */ 1233 break; 1234 case 4 : 1235 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1236 break; 1237 case 8 : 1238 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1239 break; 1240 default : 1241 pr_warn("%s: Unsupported bus width\n", np->full_name); 1242 } 1243} 1244#else 1245static void mmci_dt_populate_generic_pdata(struct device_node *np, 1246 struct mmci_platform_data *pdata) 1247{ 1248 return; 1249} 1250#endif 1251 1252static int __devinit mmci_probe(struct amba_device *dev, 1253 const struct amba_id *id) 1254{ 1255 struct mmci_platform_data *plat = dev->dev.platform_data; 1256 struct device_node *np = dev->dev.of_node; 1257 struct variant_data *variant = id->data; 1258 struct mmci_host *host; 1259 struct mmc_host *mmc; 1260 int ret; 1261 1262 /* Must have platform data or Device Tree. */ 1263 if (!plat && !np) { 1264 dev_err(&dev->dev, "No plat data or DT found\n"); 1265 return -EINVAL; 1266 } 1267 1268 if (np) 1269 mmci_dt_populate_generic_pdata(np, plat); 1270 1271 ret = amba_request_regions(dev, DRIVER_NAME); 1272 if (ret) 1273 goto out; 1274 1275 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1276 if (!mmc) { 1277 ret = -ENOMEM; 1278 goto rel_regions; 1279 } 1280 1281 host = mmc_priv(mmc); 1282 host->mmc = mmc; 1283 1284 host->gpio_wp = -ENOSYS; 1285 host->gpio_cd = -ENOSYS; 1286 host->gpio_cd_irq = -1; 1287 1288 host->hw_designer = amba_manf(dev); 1289 host->hw_revision = amba_rev(dev); 1290 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1291 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1292 1293 host->clk = clk_get(&dev->dev, NULL); 1294 if (IS_ERR(host->clk)) { 1295 ret = PTR_ERR(host->clk); 1296 host->clk = NULL; 1297 goto host_free; 1298 } 1299 1300 ret = clk_prepare(host->clk); 1301 if (ret) 1302 goto clk_free; 1303 1304 ret = clk_enable(host->clk); 1305 if (ret) 1306 goto clk_unprep; 1307 1308 host->plat = plat; 1309 host->variant = variant; 1310 host->mclk = clk_get_rate(host->clk); 1311 /* 1312 * According to the spec, mclk is max 100 MHz, 1313 * so we try to adjust the clock down to this, 1314 * (if possible). 1315 */ 1316 if (host->mclk > 100000000) { 1317 ret = clk_set_rate(host->clk, 100000000); 1318 if (ret < 0) 1319 goto clk_disable; 1320 host->mclk = clk_get_rate(host->clk); 1321 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1322 host->mclk); 1323 } 1324 host->phybase = dev->res.start; 1325 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1326 if (!host->base) { 1327 ret = -ENOMEM; 1328 goto clk_disable; 1329 } 1330 1331 mmc->ops = &mmci_ops; 1332 /* 1333 * The ARM and ST versions of the block have slightly different 1334 * clock divider equations which means that the minimum divider 1335 * differs too. 1336 */ 1337 if (variant->st_clkdiv) 1338 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1339 else 1340 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1341 /* 1342 * If the platform data supplies a maximum operating 1343 * frequency, this takes precedence. Else, we fall back 1344 * to using the module parameter, which has a (low) 1345 * default value in case it is not specified. Either 1346 * value must not exceed the clock rate into the block, 1347 * of course. 1348 */ 1349 if (plat->f_max) 1350 mmc->f_max = min(host->mclk, plat->f_max); 1351 else 1352 mmc->f_max = min(host->mclk, fmax); 1353 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1354 1355#ifdef CONFIG_REGULATOR 1356 /* If we're using the regulator framework, try to fetch a regulator */ 1357 host->vcc = regulator_get(&dev->dev, "vmmc"); 1358 if (IS_ERR(host->vcc)) 1359 host->vcc = NULL; 1360 else { 1361 int mask = mmc_regulator_get_ocrmask(host->vcc); 1362 1363 if (mask < 0) 1364 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 1365 mask); 1366 else { 1367 host->mmc->ocr_avail = (u32) mask; 1368 if (plat->ocr_mask) 1369 dev_warn(&dev->dev, 1370 "Provided ocr_mask/setpower will not be used " 1371 "(using regulator instead)\n"); 1372 } 1373 } 1374#endif 1375 /* Fall back to platform data if no regulator is found */ 1376 if (host->vcc == NULL) 1377 mmc->ocr_avail = plat->ocr_mask; 1378 mmc->caps = plat->capabilities; 1379 mmc->caps2 = plat->capabilities2; 1380 1381 /* 1382 * We can do SGIO 1383 */ 1384 mmc->max_segs = NR_SG; 1385 1386 /* 1387 * Since only a certain number of bits are valid in the data length 1388 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1389 * single request. 1390 */ 1391 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1392 1393 /* 1394 * Set the maximum segment size. Since we aren't doing DMA 1395 * (yet) we are only limited by the data length register. 1396 */ 1397 mmc->max_seg_size = mmc->max_req_size; 1398 1399 /* 1400 * Block size can be up to 2048 bytes, but must be a power of two. 1401 */ 1402 mmc->max_blk_size = 1 << 11; 1403 1404 /* 1405 * Limit the number of blocks transferred so that we don't overflow 1406 * the maximum request size. 1407 */ 1408 mmc->max_blk_count = mmc->max_req_size >> 11; 1409 1410 spin_lock_init(&host->lock); 1411 1412 writel(0, host->base + MMCIMASK0); 1413 writel(0, host->base + MMCIMASK1); 1414 writel(0xfff, host->base + MMCICLEAR); 1415 1416 if (gpio_is_valid(plat->gpio_cd)) { 1417 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1418 if (ret == 0) 1419 ret = gpio_direction_input(plat->gpio_cd); 1420 if (ret == 0) 1421 host->gpio_cd = plat->gpio_cd; 1422 else if (ret != -ENOSYS) 1423 goto err_gpio_cd; 1424 1425 /* 1426 * A gpio pin that will detect cards when inserted and removed 1427 * will most likely want to trigger on the edges if it is 1428 * 0 when ejected and 1 when inserted (or mutatis mutandis 1429 * for the inverted case) so we request triggers on both 1430 * edges. 1431 */ 1432 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1433 mmci_cd_irq, 1434 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1435 DRIVER_NAME " (cd)", host); 1436 if (ret >= 0) 1437 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1438 } 1439 if (gpio_is_valid(plat->gpio_wp)) { 1440 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1441 if (ret == 0) 1442 ret = gpio_direction_input(plat->gpio_wp); 1443 if (ret == 0) 1444 host->gpio_wp = plat->gpio_wp; 1445 else if (ret != -ENOSYS) 1446 goto err_gpio_wp; 1447 } 1448 1449 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1450 && host->gpio_cd_irq < 0) 1451 mmc->caps |= MMC_CAP_NEEDS_POLL; 1452 1453 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1454 if (ret) 1455 goto unmap; 1456 1457 if (dev->irq[1] == NO_IRQ || !dev->irq[1]) 1458 host->singleirq = true; 1459 else { 1460 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1461 DRIVER_NAME " (pio)", host); 1462 if (ret) 1463 goto irq0_free; 1464 } 1465 1466 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1467 1468 amba_set_drvdata(dev, mmc); 1469 1470 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1471 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1472 amba_rev(dev), (unsigned long long)dev->res.start, 1473 dev->irq[0], dev->irq[1]); 1474 1475 mmci_dma_setup(host); 1476 1477 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1478 pm_runtime_use_autosuspend(&dev->dev); 1479 pm_runtime_put(&dev->dev); 1480 1481 mmc_add_host(mmc); 1482 1483 return 0; 1484 1485 irq0_free: 1486 free_irq(dev->irq[0], host); 1487 unmap: 1488 if (host->gpio_wp != -ENOSYS) 1489 gpio_free(host->gpio_wp); 1490 err_gpio_wp: 1491 if (host->gpio_cd_irq >= 0) 1492 free_irq(host->gpio_cd_irq, host); 1493 if (host->gpio_cd != -ENOSYS) 1494 gpio_free(host->gpio_cd); 1495 err_gpio_cd: 1496 iounmap(host->base); 1497 clk_disable: 1498 clk_disable(host->clk); 1499 clk_unprep: 1500 clk_unprepare(host->clk); 1501 clk_free: 1502 clk_put(host->clk); 1503 host_free: 1504 mmc_free_host(mmc); 1505 rel_regions: 1506 amba_release_regions(dev); 1507 out: 1508 return ret; 1509} 1510 1511static int __devexit mmci_remove(struct amba_device *dev) 1512{ 1513 struct mmc_host *mmc = amba_get_drvdata(dev); 1514 1515 amba_set_drvdata(dev, NULL); 1516 1517 if (mmc) { 1518 struct mmci_host *host = mmc_priv(mmc); 1519 1520 /* 1521 * Undo pm_runtime_put() in probe. We use the _sync 1522 * version here so that we can access the primecell. 1523 */ 1524 pm_runtime_get_sync(&dev->dev); 1525 1526 mmc_remove_host(mmc); 1527 1528 writel(0, host->base + MMCIMASK0); 1529 writel(0, host->base + MMCIMASK1); 1530 1531 writel(0, host->base + MMCICOMMAND); 1532 writel(0, host->base + MMCIDATACTRL); 1533 1534 mmci_dma_release(host); 1535 free_irq(dev->irq[0], host); 1536 if (!host->singleirq) 1537 free_irq(dev->irq[1], host); 1538 1539 if (host->gpio_wp != -ENOSYS) 1540 gpio_free(host->gpio_wp); 1541 if (host->gpio_cd_irq >= 0) 1542 free_irq(host->gpio_cd_irq, host); 1543 if (host->gpio_cd != -ENOSYS) 1544 gpio_free(host->gpio_cd); 1545 1546 iounmap(host->base); 1547 clk_disable(host->clk); 1548 clk_unprepare(host->clk); 1549 clk_put(host->clk); 1550 1551 if (host->vcc) 1552 mmc_regulator_set_ocr(mmc, host->vcc, 0); 1553 regulator_put(host->vcc); 1554 1555 mmc_free_host(mmc); 1556 1557 amba_release_regions(dev); 1558 } 1559 1560 return 0; 1561} 1562 1563#ifdef CONFIG_SUSPEND 1564static int mmci_suspend(struct device *dev) 1565{ 1566 struct amba_device *adev = to_amba_device(dev); 1567 struct mmc_host *mmc = amba_get_drvdata(adev); 1568 int ret = 0; 1569 1570 if (mmc) { 1571 struct mmci_host *host = mmc_priv(mmc); 1572 1573 ret = mmc_suspend_host(mmc); 1574 if (ret == 0) { 1575 pm_runtime_get_sync(dev); 1576 writel(0, host->base + MMCIMASK0); 1577 } 1578 } 1579 1580 return ret; 1581} 1582 1583static int mmci_resume(struct device *dev) 1584{ 1585 struct amba_device *adev = to_amba_device(dev); 1586 struct mmc_host *mmc = amba_get_drvdata(adev); 1587 int ret = 0; 1588 1589 if (mmc) { 1590 struct mmci_host *host = mmc_priv(mmc); 1591 1592 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1593 pm_runtime_put(dev); 1594 1595 ret = mmc_resume_host(mmc); 1596 } 1597 1598 return ret; 1599} 1600#endif 1601 1602static const struct dev_pm_ops mmci_dev_pm_ops = { 1603 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1604}; 1605 1606static struct amba_id mmci_ids[] = { 1607 { 1608 .id = 0x00041180, 1609 .mask = 0xff0fffff, 1610 .data = &variant_arm, 1611 }, 1612 { 1613 .id = 0x01041180, 1614 .mask = 0xff0fffff, 1615 .data = &variant_arm_extended_fifo, 1616 }, 1617 { 1618 .id = 0x00041181, 1619 .mask = 0x000fffff, 1620 .data = &variant_arm, 1621 }, 1622 /* ST Micro variants */ 1623 { 1624 .id = 0x00180180, 1625 .mask = 0x00ffffff, 1626 .data = &variant_u300, 1627 }, 1628 { 1629 .id = 0x00280180, 1630 .mask = 0x00ffffff, 1631 .data = &variant_u300, 1632 }, 1633 { 1634 .id = 0x00480180, 1635 .mask = 0xf0ffffff, 1636 .data = &variant_ux500, 1637 }, 1638 { 1639 .id = 0x10480180, 1640 .mask = 0xf0ffffff, 1641 .data = &variant_ux500v2, 1642 }, 1643 { 0, 0 }, 1644}; 1645 1646MODULE_DEVICE_TABLE(amba, mmci_ids); 1647 1648static struct amba_driver mmci_driver = { 1649 .drv = { 1650 .name = DRIVER_NAME, 1651 .pm = &mmci_dev_pm_ops, 1652 }, 1653 .probe = mmci_probe, 1654 .remove = __devexit_p(mmci_remove), 1655 .id_table = mmci_ids, 1656}; 1657 1658module_amba_driver(mmci_driver); 1659 1660module_param(fmax, uint, 0444); 1661 1662MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1663MODULE_LICENSE("GPL"); 1664