mmci.c revision c4d877c1b3df58d89f01d7b211f58b944356eea3
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson AB. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/delay.h> 19#include <linux/err.h> 20#include <linux/highmem.h> 21#include <linux/log2.h> 22#include <linux/mmc/host.h> 23#include <linux/mmc/card.h> 24#include <linux/amba/bus.h> 25#include <linux/clk.h> 26#include <linux/scatterlist.h> 27#include <linux/gpio.h> 28#include <linux/amba/mmci.h> 29#include <linux/regulator/consumer.h> 30 31#include <asm/div64.h> 32#include <asm/io.h> 33#include <asm/sizes.h> 34 35#include "mmci.h" 36 37#define DRIVER_NAME "mmci-pl18x" 38 39static unsigned int fmax = 515633; 40 41/** 42 * struct variant_data - MMCI variant-specific quirks 43 * @clkreg: default value for MCICLOCK register 44 * @clkreg_enable: enable value for MMCICLOCK register 45 * @datalength_bits: number of bits in the MMCIDATALENGTH register 46 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 47 * is asserted (likewise for RX) 48 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 49 * is asserted (likewise for RX) 50 * @sdio: variant supports SDIO 51 * @st_clkdiv: true if using a ST-specific clock divider algorithm 52 */ 53struct variant_data { 54 unsigned int clkreg; 55 unsigned int clkreg_enable; 56 unsigned int datalength_bits; 57 unsigned int fifosize; 58 unsigned int fifohalfsize; 59 bool sdio; 60 bool st_clkdiv; 61}; 62 63static struct variant_data variant_arm = { 64 .fifosize = 16 * 4, 65 .fifohalfsize = 8 * 4, 66 .datalength_bits = 16, 67}; 68 69static struct variant_data variant_u300 = { 70 .fifosize = 16 * 4, 71 .fifohalfsize = 8 * 4, 72 .clkreg_enable = 1 << 13, /* HWFCEN */ 73 .datalength_bits = 16, 74 .sdio = true, 75}; 76 77static struct variant_data variant_ux500 = { 78 .fifosize = 30 * 4, 79 .fifohalfsize = 8 * 4, 80 .clkreg = MCI_CLK_ENABLE, 81 .clkreg_enable = 1 << 14, /* HWFCEN */ 82 .datalength_bits = 24, 83 .sdio = true, 84 .st_clkdiv = true, 85}; 86 87/* 88 * This must be called with host->lock held 89 */ 90static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 91{ 92 struct variant_data *variant = host->variant; 93 u32 clk = variant->clkreg; 94 95 if (desired) { 96 if (desired >= host->mclk) { 97 clk = MCI_CLK_BYPASS; 98 host->cclk = host->mclk; 99 } else if (variant->st_clkdiv) { 100 /* 101 * DB8500 TRM says f = mclk / (clkdiv + 2) 102 * => clkdiv = (mclk / f) - 2 103 * Round the divider up so we don't exceed the max 104 * frequency 105 */ 106 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 107 if (clk >= 256) 108 clk = 255; 109 host->cclk = host->mclk / (clk + 2); 110 } else { 111 /* 112 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 113 * => clkdiv = mclk / (2 * f) - 1 114 */ 115 clk = host->mclk / (2 * desired) - 1; 116 if (clk >= 256) 117 clk = 255; 118 host->cclk = host->mclk / (2 * (clk + 1)); 119 } 120 121 clk |= variant->clkreg_enable; 122 clk |= MCI_CLK_ENABLE; 123 /* This hasn't proven to be worthwhile */ 124 /* clk |= MCI_CLK_PWRSAVE; */ 125 } 126 127 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 128 clk |= MCI_4BIT_BUS; 129 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 130 clk |= MCI_ST_8BIT_BUS; 131 132 writel(clk, host->base + MMCICLOCK); 133} 134 135static void 136mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 137{ 138 writel(0, host->base + MMCICOMMAND); 139 140 BUG_ON(host->data); 141 142 host->mrq = NULL; 143 host->cmd = NULL; 144 145 if (mrq->data) 146 mrq->data->bytes_xfered = host->data_xfered; 147 148 /* 149 * Need to drop the host lock here; mmc_request_done may call 150 * back into the driver... 151 */ 152 spin_unlock(&host->lock); 153 mmc_request_done(host->mmc, mrq); 154 spin_lock(&host->lock); 155} 156 157static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 158{ 159 void __iomem *base = host->base; 160 161 if (host->singleirq) { 162 unsigned int mask0 = readl(base + MMCIMASK0); 163 164 mask0 &= ~MCI_IRQ1MASK; 165 mask0 |= mask; 166 167 writel(mask0, base + MMCIMASK0); 168 } 169 170 writel(mask, base + MMCIMASK1); 171} 172 173static void mmci_stop_data(struct mmci_host *host) 174{ 175 writel(0, host->base + MMCIDATACTRL); 176 mmci_set_mask1(host, 0); 177 host->data = NULL; 178} 179 180static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 181{ 182 unsigned int flags = SG_MITER_ATOMIC; 183 184 if (data->flags & MMC_DATA_READ) 185 flags |= SG_MITER_TO_SG; 186 else 187 flags |= SG_MITER_FROM_SG; 188 189 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 190} 191 192static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 193{ 194 struct variant_data *variant = host->variant; 195 unsigned int datactrl, timeout, irqmask; 196 unsigned long long clks; 197 void __iomem *base; 198 int blksz_bits; 199 200 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 201 data->blksz, data->blocks, data->flags); 202 203 host->data = data; 204 host->size = data->blksz * data->blocks; 205 host->data_xfered = 0; 206 207 mmci_init_sg(host, data); 208 209 clks = (unsigned long long)data->timeout_ns * host->cclk; 210 do_div(clks, 1000000000UL); 211 212 timeout = data->timeout_clks + (unsigned int)clks; 213 214 base = host->base; 215 writel(timeout, base + MMCIDATATIMER); 216 writel(host->size, base + MMCIDATALENGTH); 217 218 blksz_bits = ffs(data->blksz) - 1; 219 BUG_ON(1 << blksz_bits != data->blksz); 220 221 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 222 if (data->flags & MMC_DATA_READ) { 223 datactrl |= MCI_DPSM_DIRECTION; 224 irqmask = MCI_RXFIFOHALFFULLMASK; 225 226 /* 227 * If we have less than the fifo 'half-full' threshold to 228 * transfer, trigger a PIO interrupt as soon as any data 229 * is available. 230 */ 231 if (host->size < variant->fifohalfsize) 232 irqmask |= MCI_RXDATAAVLBLMASK; 233 } else { 234 /* 235 * We don't actually need to include "FIFO empty" here 236 * since its implicit in "FIFO half empty". 237 */ 238 irqmask = MCI_TXFIFOHALFEMPTYMASK; 239 } 240 241 /* The ST Micro variants has a special bit to enable SDIO */ 242 if (variant->sdio && host->mmc->card) 243 if (mmc_card_sdio(host->mmc->card)) 244 datactrl |= MCI_ST_DPSM_SDIOEN; 245 246 writel(datactrl, base + MMCIDATACTRL); 247 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 248 mmci_set_mask1(host, irqmask); 249} 250 251static void 252mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 253{ 254 void __iomem *base = host->base; 255 256 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 257 cmd->opcode, cmd->arg, cmd->flags); 258 259 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 260 writel(0, base + MMCICOMMAND); 261 udelay(1); 262 } 263 264 c |= cmd->opcode | MCI_CPSM_ENABLE; 265 if (cmd->flags & MMC_RSP_PRESENT) { 266 if (cmd->flags & MMC_RSP_136) 267 c |= MCI_CPSM_LONGRSP; 268 c |= MCI_CPSM_RESPONSE; 269 } 270 if (/*interrupt*/0) 271 c |= MCI_CPSM_INTERRUPT; 272 273 host->cmd = cmd; 274 275 writel(cmd->arg, base + MMCIARGUMENT); 276 writel(c, base + MMCICOMMAND); 277} 278 279static void 280mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 281 unsigned int status) 282{ 283 /* First check for errors */ 284 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 285 u32 remain, success; 286 287 /* 288 * Calculate how far we are into the transfer. Note that 289 * the data counter gives the number of bytes transferred 290 * on the MMC bus, not on the host side. On reads, this 291 * can be as much as a FIFO-worth of data ahead. This 292 * matters for FIFO overruns only. 293 */ 294 remain = readl(host->base + MMCIDATACNT); 295 success = data->blksz * data->blocks - remain; 296 297 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 298 status, success); 299 if (status & MCI_DATACRCFAIL) { 300 /* Last block was not successful */ 301 success -= 1; 302 data->error = -EILSEQ; 303 } else if (status & MCI_DATATIMEOUT) { 304 data->error = -ETIMEDOUT; 305 } else if (status & MCI_TXUNDERRUN) { 306 data->error = -EIO; 307 } else if (status & MCI_RXOVERRUN) { 308 if (success > host->variant->fifosize) 309 success -= host->variant->fifosize; 310 else 311 success = 0; 312 data->error = -EIO; 313 } 314 host->data_xfered = round_down(success, data->blksz); 315 } 316 317 if (status & MCI_DATABLOCKEND) 318 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 319 320 if (status & MCI_DATAEND || data->error) { 321 mmci_stop_data(host); 322 323 if (!data->error) 324 /* The error clause is handled above, success! */ 325 host->data_xfered += data->blksz * data->blocks; 326 327 if (!data->stop) { 328 mmci_request_end(host, data->mrq); 329 } else { 330 mmci_start_command(host, data->stop, 0); 331 } 332 } 333} 334 335static void 336mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 337 unsigned int status) 338{ 339 void __iomem *base = host->base; 340 341 host->cmd = NULL; 342 343 if (status & MCI_CMDTIMEOUT) { 344 cmd->error = -ETIMEDOUT; 345 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 346 cmd->error = -EILSEQ; 347 } else { 348 cmd->resp[0] = readl(base + MMCIRESPONSE0); 349 cmd->resp[1] = readl(base + MMCIRESPONSE1); 350 cmd->resp[2] = readl(base + MMCIRESPONSE2); 351 cmd->resp[3] = readl(base + MMCIRESPONSE3); 352 } 353 354 if (!cmd->data || cmd->error) { 355 if (host->data) 356 mmci_stop_data(host); 357 mmci_request_end(host, cmd->mrq); 358 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 359 mmci_start_data(host, cmd->data); 360 } 361} 362 363static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 364{ 365 void __iomem *base = host->base; 366 char *ptr = buffer; 367 u32 status; 368 int host_remain = host->size; 369 370 do { 371 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 372 373 if (count > remain) 374 count = remain; 375 376 if (count <= 0) 377 break; 378 379 readsl(base + MMCIFIFO, ptr, count >> 2); 380 381 ptr += count; 382 remain -= count; 383 host_remain -= count; 384 385 if (remain == 0) 386 break; 387 388 status = readl(base + MMCISTATUS); 389 } while (status & MCI_RXDATAAVLBL); 390 391 return ptr - buffer; 392} 393 394static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 395{ 396 struct variant_data *variant = host->variant; 397 void __iomem *base = host->base; 398 char *ptr = buffer; 399 400 do { 401 unsigned int count, maxcnt; 402 403 maxcnt = status & MCI_TXFIFOEMPTY ? 404 variant->fifosize : variant->fifohalfsize; 405 count = min(remain, maxcnt); 406 407 /* 408 * The ST Micro variant for SDIO transfer sizes 409 * less then 8 bytes should have clock H/W flow 410 * control disabled. 411 */ 412 if (variant->sdio && 413 mmc_card_sdio(host->mmc->card)) { 414 if (count < 8) 415 writel(readl(host->base + MMCICLOCK) & 416 ~variant->clkreg_enable, 417 host->base + MMCICLOCK); 418 else 419 writel(readl(host->base + MMCICLOCK) | 420 variant->clkreg_enable, 421 host->base + MMCICLOCK); 422 } 423 424 /* 425 * SDIO especially may want to send something that is 426 * not divisible by 4 (as opposed to card sectors 427 * etc), and the FIFO only accept full 32-bit writes. 428 * So compensate by adding +3 on the count, a single 429 * byte become a 32bit write, 7 bytes will be two 430 * 32bit writes etc. 431 */ 432 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 433 434 ptr += count; 435 remain -= count; 436 437 if (remain == 0) 438 break; 439 440 status = readl(base + MMCISTATUS); 441 } while (status & MCI_TXFIFOHALFEMPTY); 442 443 return ptr - buffer; 444} 445 446/* 447 * PIO data transfer IRQ handler. 448 */ 449static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 450{ 451 struct mmci_host *host = dev_id; 452 struct sg_mapping_iter *sg_miter = &host->sg_miter; 453 struct variant_data *variant = host->variant; 454 void __iomem *base = host->base; 455 unsigned long flags; 456 u32 status; 457 458 status = readl(base + MMCISTATUS); 459 460 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 461 462 local_irq_save(flags); 463 464 do { 465 unsigned int remain, len; 466 char *buffer; 467 468 /* 469 * For write, we only need to test the half-empty flag 470 * here - if the FIFO is completely empty, then by 471 * definition it is more than half empty. 472 * 473 * For read, check for data available. 474 */ 475 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 476 break; 477 478 if (!sg_miter_next(sg_miter)) 479 break; 480 481 buffer = sg_miter->addr; 482 remain = sg_miter->length; 483 484 len = 0; 485 if (status & MCI_RXACTIVE) 486 len = mmci_pio_read(host, buffer, remain); 487 if (status & MCI_TXACTIVE) 488 len = mmci_pio_write(host, buffer, remain, status); 489 490 sg_miter->consumed = len; 491 492 host->size -= len; 493 remain -= len; 494 495 if (remain) 496 break; 497 498 status = readl(base + MMCISTATUS); 499 } while (1); 500 501 sg_miter_stop(sg_miter); 502 503 local_irq_restore(flags); 504 505 /* 506 * If we have less than the fifo 'half-full' threshold to transfer, 507 * trigger a PIO interrupt as soon as any data is available. 508 */ 509 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 510 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 511 512 /* 513 * If we run out of data, disable the data IRQs; this 514 * prevents a race where the FIFO becomes empty before 515 * the chip itself has disabled the data path, and 516 * stops us racing with our data end IRQ. 517 */ 518 if (host->size == 0) { 519 mmci_set_mask1(host, 0); 520 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 521 } 522 523 return IRQ_HANDLED; 524} 525 526/* 527 * Handle completion of command and data transfers. 528 */ 529static irqreturn_t mmci_irq(int irq, void *dev_id) 530{ 531 struct mmci_host *host = dev_id; 532 u32 status; 533 int ret = 0; 534 535 spin_lock(&host->lock); 536 537 do { 538 struct mmc_command *cmd; 539 struct mmc_data *data; 540 541 status = readl(host->base + MMCISTATUS); 542 543 if (host->singleirq) { 544 if (status & readl(host->base + MMCIMASK1)) 545 mmci_pio_irq(irq, dev_id); 546 547 status &= ~MCI_IRQ1MASK; 548 } 549 550 status &= readl(host->base + MMCIMASK0); 551 writel(status, host->base + MMCICLEAR); 552 553 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 554 555 data = host->data; 556 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 557 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 558 mmci_data_irq(host, data, status); 559 560 cmd = host->cmd; 561 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 562 mmci_cmd_irq(host, cmd, status); 563 564 ret = 1; 565 } while (status); 566 567 spin_unlock(&host->lock); 568 569 return IRQ_RETVAL(ret); 570} 571 572static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 573{ 574 struct mmci_host *host = mmc_priv(mmc); 575 unsigned long flags; 576 577 WARN_ON(host->mrq != NULL); 578 579 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 580 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 581 mrq->data->blksz); 582 mrq->cmd->error = -EINVAL; 583 mmc_request_done(mmc, mrq); 584 return; 585 } 586 587 spin_lock_irqsave(&host->lock, flags); 588 589 host->mrq = mrq; 590 591 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 592 mmci_start_data(host, mrq->data); 593 594 mmci_start_command(host, mrq->cmd, 0); 595 596 spin_unlock_irqrestore(&host->lock, flags); 597} 598 599static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 600{ 601 struct mmci_host *host = mmc_priv(mmc); 602 u32 pwr = 0; 603 unsigned long flags; 604 int ret; 605 606 switch (ios->power_mode) { 607 case MMC_POWER_OFF: 608 if (host->vcc) 609 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 610 break; 611 case MMC_POWER_UP: 612 if (host->vcc) { 613 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 614 if (ret) { 615 dev_err(mmc_dev(mmc), "unable to set OCR\n"); 616 /* 617 * The .set_ios() function in the mmc_host_ops 618 * struct return void, and failing to set the 619 * power should be rare so we print an error 620 * and return here. 621 */ 622 return; 623 } 624 } 625 if (host->plat->vdd_handler) 626 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, 627 ios->power_mode); 628 /* The ST version does not have this, fall through to POWER_ON */ 629 if (host->hw_designer != AMBA_VENDOR_ST) { 630 pwr |= MCI_PWR_UP; 631 break; 632 } 633 case MMC_POWER_ON: 634 pwr |= MCI_PWR_ON; 635 break; 636 } 637 638 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 639 if (host->hw_designer != AMBA_VENDOR_ST) 640 pwr |= MCI_ROD; 641 else { 642 /* 643 * The ST Micro variant use the ROD bit for something 644 * else and only has OD (Open Drain). 645 */ 646 pwr |= MCI_OD; 647 } 648 } 649 650 spin_lock_irqsave(&host->lock, flags); 651 652 mmci_set_clkreg(host, ios->clock); 653 654 if (host->pwr != pwr) { 655 host->pwr = pwr; 656 writel(pwr, host->base + MMCIPOWER); 657 } 658 659 spin_unlock_irqrestore(&host->lock, flags); 660} 661 662static int mmci_get_ro(struct mmc_host *mmc) 663{ 664 struct mmci_host *host = mmc_priv(mmc); 665 666 if (host->gpio_wp == -ENOSYS) 667 return -ENOSYS; 668 669 return gpio_get_value_cansleep(host->gpio_wp); 670} 671 672static int mmci_get_cd(struct mmc_host *mmc) 673{ 674 struct mmci_host *host = mmc_priv(mmc); 675 struct mmci_platform_data *plat = host->plat; 676 unsigned int status; 677 678 if (host->gpio_cd == -ENOSYS) { 679 if (!plat->status) 680 return 1; /* Assume always present */ 681 682 status = plat->status(mmc_dev(host->mmc)); 683 } else 684 status = !!gpio_get_value_cansleep(host->gpio_cd) 685 ^ plat->cd_invert; 686 687 /* 688 * Use positive logic throughout - status is zero for no card, 689 * non-zero for card inserted. 690 */ 691 return status; 692} 693 694static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 695{ 696 struct mmci_host *host = dev_id; 697 698 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 699 700 return IRQ_HANDLED; 701} 702 703static const struct mmc_host_ops mmci_ops = { 704 .request = mmci_request, 705 .set_ios = mmci_set_ios, 706 .get_ro = mmci_get_ro, 707 .get_cd = mmci_get_cd, 708}; 709 710static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 711{ 712 struct mmci_platform_data *plat = dev->dev.platform_data; 713 struct variant_data *variant = id->data; 714 struct mmci_host *host; 715 struct mmc_host *mmc; 716 int ret; 717 718 /* must have platform data */ 719 if (!plat) { 720 ret = -EINVAL; 721 goto out; 722 } 723 724 ret = amba_request_regions(dev, DRIVER_NAME); 725 if (ret) 726 goto out; 727 728 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 729 if (!mmc) { 730 ret = -ENOMEM; 731 goto rel_regions; 732 } 733 734 host = mmc_priv(mmc); 735 host->mmc = mmc; 736 737 host->gpio_wp = -ENOSYS; 738 host->gpio_cd = -ENOSYS; 739 host->gpio_cd_irq = -1; 740 741 host->hw_designer = amba_manf(dev); 742 host->hw_revision = amba_rev(dev); 743 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 744 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 745 746 host->clk = clk_get(&dev->dev, NULL); 747 if (IS_ERR(host->clk)) { 748 ret = PTR_ERR(host->clk); 749 host->clk = NULL; 750 goto host_free; 751 } 752 753 ret = clk_enable(host->clk); 754 if (ret) 755 goto clk_free; 756 757 host->plat = plat; 758 host->variant = variant; 759 host->mclk = clk_get_rate(host->clk); 760 /* 761 * According to the spec, mclk is max 100 MHz, 762 * so we try to adjust the clock down to this, 763 * (if possible). 764 */ 765 if (host->mclk > 100000000) { 766 ret = clk_set_rate(host->clk, 100000000); 767 if (ret < 0) 768 goto clk_disable; 769 host->mclk = clk_get_rate(host->clk); 770 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 771 host->mclk); 772 } 773 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 774 if (!host->base) { 775 ret = -ENOMEM; 776 goto clk_disable; 777 } 778 779 mmc->ops = &mmci_ops; 780 mmc->f_min = (host->mclk + 511) / 512; 781 /* 782 * If the platform data supplies a maximum operating 783 * frequency, this takes precedence. Else, we fall back 784 * to using the module parameter, which has a (low) 785 * default value in case it is not specified. Either 786 * value must not exceed the clock rate into the block, 787 * of course. 788 */ 789 if (plat->f_max) 790 mmc->f_max = min(host->mclk, plat->f_max); 791 else 792 mmc->f_max = min(host->mclk, fmax); 793 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 794 795#ifdef CONFIG_REGULATOR 796 /* If we're using the regulator framework, try to fetch a regulator */ 797 host->vcc = regulator_get(&dev->dev, "vmmc"); 798 if (IS_ERR(host->vcc)) 799 host->vcc = NULL; 800 else { 801 int mask = mmc_regulator_get_ocrmask(host->vcc); 802 803 if (mask < 0) 804 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 805 mask); 806 else { 807 host->mmc->ocr_avail = (u32) mask; 808 if (plat->ocr_mask) 809 dev_warn(&dev->dev, 810 "Provided ocr_mask/setpower will not be used " 811 "(using regulator instead)\n"); 812 } 813 } 814#endif 815 /* Fall back to platform data if no regulator is found */ 816 if (host->vcc == NULL) 817 mmc->ocr_avail = plat->ocr_mask; 818 mmc->caps = plat->capabilities; 819 820 /* 821 * We can do SGIO 822 */ 823 mmc->max_segs = NR_SG; 824 825 /* 826 * Since only a certain number of bits are valid in the data length 827 * register, we must ensure that we don't exceed 2^num-1 bytes in a 828 * single request. 829 */ 830 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 831 832 /* 833 * Set the maximum segment size. Since we aren't doing DMA 834 * (yet) we are only limited by the data length register. 835 */ 836 mmc->max_seg_size = mmc->max_req_size; 837 838 /* 839 * Block size can be up to 2048 bytes, but must be a power of two. 840 */ 841 mmc->max_blk_size = 2048; 842 843 /* 844 * No limit on the number of blocks transferred. 845 */ 846 mmc->max_blk_count = mmc->max_req_size; 847 848 spin_lock_init(&host->lock); 849 850 writel(0, host->base + MMCIMASK0); 851 writel(0, host->base + MMCIMASK1); 852 writel(0xfff, host->base + MMCICLEAR); 853 854 if (gpio_is_valid(plat->gpio_cd)) { 855 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 856 if (ret == 0) 857 ret = gpio_direction_input(plat->gpio_cd); 858 if (ret == 0) 859 host->gpio_cd = plat->gpio_cd; 860 else if (ret != -ENOSYS) 861 goto err_gpio_cd; 862 863 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 864 mmci_cd_irq, 0, 865 DRIVER_NAME " (cd)", host); 866 if (ret >= 0) 867 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 868 } 869 if (gpio_is_valid(plat->gpio_wp)) { 870 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 871 if (ret == 0) 872 ret = gpio_direction_input(plat->gpio_wp); 873 if (ret == 0) 874 host->gpio_wp = plat->gpio_wp; 875 else if (ret != -ENOSYS) 876 goto err_gpio_wp; 877 } 878 879 if ((host->plat->status || host->gpio_cd != -ENOSYS) 880 && host->gpio_cd_irq < 0) 881 mmc->caps |= MMC_CAP_NEEDS_POLL; 882 883 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 884 if (ret) 885 goto unmap; 886 887 if (dev->irq[1] == NO_IRQ) 888 host->singleirq = true; 889 else { 890 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 891 DRIVER_NAME " (pio)", host); 892 if (ret) 893 goto irq0_free; 894 } 895 896 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 897 898 amba_set_drvdata(dev, mmc); 899 900 dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n", 901 mmc_hostname(mmc), amba_part(dev), amba_rev(dev), 902 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 903 904 mmc_add_host(mmc); 905 906 return 0; 907 908 irq0_free: 909 free_irq(dev->irq[0], host); 910 unmap: 911 if (host->gpio_wp != -ENOSYS) 912 gpio_free(host->gpio_wp); 913 err_gpio_wp: 914 if (host->gpio_cd_irq >= 0) 915 free_irq(host->gpio_cd_irq, host); 916 if (host->gpio_cd != -ENOSYS) 917 gpio_free(host->gpio_cd); 918 err_gpio_cd: 919 iounmap(host->base); 920 clk_disable: 921 clk_disable(host->clk); 922 clk_free: 923 clk_put(host->clk); 924 host_free: 925 mmc_free_host(mmc); 926 rel_regions: 927 amba_release_regions(dev); 928 out: 929 return ret; 930} 931 932static int __devexit mmci_remove(struct amba_device *dev) 933{ 934 struct mmc_host *mmc = amba_get_drvdata(dev); 935 936 amba_set_drvdata(dev, NULL); 937 938 if (mmc) { 939 struct mmci_host *host = mmc_priv(mmc); 940 941 mmc_remove_host(mmc); 942 943 writel(0, host->base + MMCIMASK0); 944 writel(0, host->base + MMCIMASK1); 945 946 writel(0, host->base + MMCICOMMAND); 947 writel(0, host->base + MMCIDATACTRL); 948 949 free_irq(dev->irq[0], host); 950 if (!host->singleirq) 951 free_irq(dev->irq[1], host); 952 953 if (host->gpio_wp != -ENOSYS) 954 gpio_free(host->gpio_wp); 955 if (host->gpio_cd_irq >= 0) 956 free_irq(host->gpio_cd_irq, host); 957 if (host->gpio_cd != -ENOSYS) 958 gpio_free(host->gpio_cd); 959 960 iounmap(host->base); 961 clk_disable(host->clk); 962 clk_put(host->clk); 963 964 if (host->vcc) 965 mmc_regulator_set_ocr(mmc, host->vcc, 0); 966 regulator_put(host->vcc); 967 968 mmc_free_host(mmc); 969 970 amba_release_regions(dev); 971 } 972 973 return 0; 974} 975 976#ifdef CONFIG_PM 977static int mmci_suspend(struct amba_device *dev, pm_message_t state) 978{ 979 struct mmc_host *mmc = amba_get_drvdata(dev); 980 int ret = 0; 981 982 if (mmc) { 983 struct mmci_host *host = mmc_priv(mmc); 984 985 ret = mmc_suspend_host(mmc); 986 if (ret == 0) 987 writel(0, host->base + MMCIMASK0); 988 } 989 990 return ret; 991} 992 993static int mmci_resume(struct amba_device *dev) 994{ 995 struct mmc_host *mmc = amba_get_drvdata(dev); 996 int ret = 0; 997 998 if (mmc) { 999 struct mmci_host *host = mmc_priv(mmc); 1000 1001 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1002 1003 ret = mmc_resume_host(mmc); 1004 } 1005 1006 return ret; 1007} 1008#else 1009#define mmci_suspend NULL 1010#define mmci_resume NULL 1011#endif 1012 1013static struct amba_id mmci_ids[] = { 1014 { 1015 .id = 0x00041180, 1016 .mask = 0x000fffff, 1017 .data = &variant_arm, 1018 }, 1019 { 1020 .id = 0x00041181, 1021 .mask = 0x000fffff, 1022 .data = &variant_arm, 1023 }, 1024 /* ST Micro variants */ 1025 { 1026 .id = 0x00180180, 1027 .mask = 0x00ffffff, 1028 .data = &variant_u300, 1029 }, 1030 { 1031 .id = 0x00280180, 1032 .mask = 0x00ffffff, 1033 .data = &variant_u300, 1034 }, 1035 { 1036 .id = 0x00480180, 1037 .mask = 0x00ffffff, 1038 .data = &variant_ux500, 1039 }, 1040 { 0, 0 }, 1041}; 1042 1043static struct amba_driver mmci_driver = { 1044 .drv = { 1045 .name = DRIVER_NAME, 1046 }, 1047 .probe = mmci_probe, 1048 .remove = __devexit_p(mmci_remove), 1049 .suspend = mmci_suspend, 1050 .resume = mmci_resume, 1051 .id_table = mmci_ids, 1052}; 1053 1054static int __init mmci_init(void) 1055{ 1056 return amba_driver_register(&mmci_driver); 1057} 1058 1059static void __exit mmci_exit(void) 1060{ 1061 amba_driver_unregister(&mmci_driver); 1062} 1063 1064module_init(mmci_init); 1065module_exit(mmci_exit); 1066module_param(fmax, uint, 0444); 1067 1068MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1069MODULE_LICENSE("GPL"); 1070