mmci.c revision ccff9b51825b7335889b780bdf7de84ca803e291
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson AB. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/delay.h> 18#include <linux/err.h> 19#include <linux/highmem.h> 20#include <linux/log2.h> 21#include <linux/mmc/host.h> 22#include <linux/mmc/card.h> 23#include <linux/amba/bus.h> 24#include <linux/clk.h> 25#include <linux/scatterlist.h> 26#include <linux/gpio.h> 27#include <linux/amba/mmci.h> 28#include <linux/regulator/consumer.h> 29 30#include <asm/div64.h> 31#include <asm/io.h> 32#include <asm/sizes.h> 33 34#include "mmci.h" 35 36#define DRIVER_NAME "mmci-pl18x" 37 38static unsigned int fmax = 515633; 39 40/** 41 * struct variant_data - MMCI variant-specific quirks 42 * @clkreg: default value for MCICLOCK register 43 * @clkreg_enable: enable value for MMCICLOCK register 44 * @datalength_bits: number of bits in the MMCIDATALENGTH register 45 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 46 * is asserted (likewise for RX) 47 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 48 * is asserted (likewise for RX) 49 * @sdio: variant supports SDIO 50 * @st_clkdiv: true if using a ST-specific clock divider algorithm 51 */ 52struct variant_data { 53 unsigned int clkreg; 54 unsigned int clkreg_enable; 55 unsigned int datalength_bits; 56 unsigned int fifosize; 57 unsigned int fifohalfsize; 58 bool sdio; 59 bool st_clkdiv; 60}; 61 62static struct variant_data variant_arm = { 63 .fifosize = 16 * 4, 64 .fifohalfsize = 8 * 4, 65 .datalength_bits = 16, 66}; 67 68static struct variant_data variant_u300 = { 69 .fifosize = 16 * 4, 70 .fifohalfsize = 8 * 4, 71 .clkreg_enable = 1 << 13, /* HWFCEN */ 72 .datalength_bits = 16, 73 .sdio = true, 74}; 75 76static struct variant_data variant_ux500 = { 77 .fifosize = 30 * 4, 78 .fifohalfsize = 8 * 4, 79 .clkreg = MCI_CLK_ENABLE, 80 .clkreg_enable = 1 << 14, /* HWFCEN */ 81 .datalength_bits = 24, 82 .sdio = true, 83 .st_clkdiv = true, 84}; 85 86/* 87 * This must be called with host->lock held 88 */ 89static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 90{ 91 struct variant_data *variant = host->variant; 92 u32 clk = variant->clkreg; 93 94 if (desired) { 95 if (desired >= host->mclk) { 96 clk = MCI_CLK_BYPASS; 97 host->cclk = host->mclk; 98 } else if (variant->st_clkdiv) { 99 /* 100 * DB8500 TRM says f = mclk / (clkdiv + 2) 101 * => clkdiv = (mclk / f) - 2 102 * Round the divider up so we don't exceed the max 103 * frequency 104 */ 105 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 106 if (clk >= 256) 107 clk = 255; 108 host->cclk = host->mclk / (clk + 2); 109 } else { 110 /* 111 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 112 * => clkdiv = mclk / (2 * f) - 1 113 */ 114 clk = host->mclk / (2 * desired) - 1; 115 if (clk >= 256) 116 clk = 255; 117 host->cclk = host->mclk / (2 * (clk + 1)); 118 } 119 120 clk |= variant->clkreg_enable; 121 clk |= MCI_CLK_ENABLE; 122 /* This hasn't proven to be worthwhile */ 123 /* clk |= MCI_CLK_PWRSAVE; */ 124 } 125 126 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 127 clk |= MCI_4BIT_BUS; 128 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 129 clk |= MCI_ST_8BIT_BUS; 130 131 writel(clk, host->base + MMCICLOCK); 132} 133 134static void 135mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 136{ 137 writel(0, host->base + MMCICOMMAND); 138 139 BUG_ON(host->data); 140 141 host->mrq = NULL; 142 host->cmd = NULL; 143 144 if (mrq->data) 145 mrq->data->bytes_xfered = host->data_xfered; 146 147 /* 148 * Need to drop the host lock here; mmc_request_done may call 149 * back into the driver... 150 */ 151 spin_unlock(&host->lock); 152 mmc_request_done(host->mmc, mrq); 153 spin_lock(&host->lock); 154} 155 156static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 157{ 158 void __iomem *base = host->base; 159 160 if (host->singleirq) { 161 unsigned int mask0 = readl(base + MMCIMASK0); 162 163 mask0 &= ~MCI_IRQ1MASK; 164 mask0 |= mask; 165 166 writel(mask0, base + MMCIMASK0); 167 } 168 169 writel(mask, base + MMCIMASK1); 170} 171 172static void mmci_stop_data(struct mmci_host *host) 173{ 174 writel(0, host->base + MMCIDATACTRL); 175 mmci_set_mask1(host, 0); 176 host->data = NULL; 177} 178 179static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 180{ 181 unsigned int flags = SG_MITER_ATOMIC; 182 183 if (data->flags & MMC_DATA_READ) 184 flags |= SG_MITER_TO_SG; 185 else 186 flags |= SG_MITER_FROM_SG; 187 188 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 189} 190 191static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 192{ 193 struct variant_data *variant = host->variant; 194 unsigned int datactrl, timeout, irqmask; 195 unsigned long long clks; 196 void __iomem *base; 197 int blksz_bits; 198 199 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 200 data->blksz, data->blocks, data->flags); 201 202 host->data = data; 203 host->size = data->blksz * data->blocks; 204 host->data_xfered = 0; 205 206 mmci_init_sg(host, data); 207 208 clks = (unsigned long long)data->timeout_ns * host->cclk; 209 do_div(clks, 1000000000UL); 210 211 timeout = data->timeout_clks + (unsigned int)clks; 212 213 base = host->base; 214 writel(timeout, base + MMCIDATATIMER); 215 writel(host->size, base + MMCIDATALENGTH); 216 217 blksz_bits = ffs(data->blksz) - 1; 218 BUG_ON(1 << blksz_bits != data->blksz); 219 220 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 221 if (data->flags & MMC_DATA_READ) { 222 datactrl |= MCI_DPSM_DIRECTION; 223 irqmask = MCI_RXFIFOHALFFULLMASK; 224 225 /* 226 * If we have less than a FIFOSIZE of bytes to transfer, 227 * trigger a PIO interrupt as soon as any data is available. 228 */ 229 if (host->size < variant->fifosize) 230 irqmask |= MCI_RXDATAAVLBLMASK; 231 } else { 232 /* 233 * We don't actually need to include "FIFO empty" here 234 * since its implicit in "FIFO half empty". 235 */ 236 irqmask = MCI_TXFIFOHALFEMPTYMASK; 237 } 238 239 /* The ST Micro variants has a special bit to enable SDIO */ 240 if (variant->sdio && host->mmc->card) 241 if (mmc_card_sdio(host->mmc->card)) 242 datactrl |= MCI_ST_DPSM_SDIOEN; 243 244 writel(datactrl, base + MMCIDATACTRL); 245 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 246 mmci_set_mask1(host, irqmask); 247} 248 249static void 250mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 251{ 252 void __iomem *base = host->base; 253 254 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 255 cmd->opcode, cmd->arg, cmd->flags); 256 257 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 258 writel(0, base + MMCICOMMAND); 259 udelay(1); 260 } 261 262 c |= cmd->opcode | MCI_CPSM_ENABLE; 263 if (cmd->flags & MMC_RSP_PRESENT) { 264 if (cmd->flags & MMC_RSP_136) 265 c |= MCI_CPSM_LONGRSP; 266 c |= MCI_CPSM_RESPONSE; 267 } 268 if (/*interrupt*/0) 269 c |= MCI_CPSM_INTERRUPT; 270 271 host->cmd = cmd; 272 273 writel(cmd->arg, base + MMCIARGUMENT); 274 writel(c, base + MMCICOMMAND); 275} 276 277static void 278mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 279 unsigned int status) 280{ 281 /* First check for errors */ 282 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 283 u32 remain, success; 284 285 /* Calculate how far we are into the transfer */ 286 remain = readl(host->base + MMCIDATACNT); 287 success = data->blksz * data->blocks - remain; 288 289 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); 290 if (status & MCI_DATACRCFAIL) { 291 /* Last block was not successful */ 292 host->data_xfered = ((success - 1) / data->blksz) * data->blksz; 293 data->error = -EILSEQ; 294 } else if (status & MCI_DATATIMEOUT) { 295 host->data_xfered = success; 296 data->error = -ETIMEDOUT; 297 } else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 298 host->data_xfered = success; 299 data->error = -EIO; 300 } 301 302 /* 303 * We hit an error condition. Ensure that any data 304 * partially written to a page is properly coherent. 305 */ 306 if (data->flags & MMC_DATA_READ) { 307 struct sg_mapping_iter *sg_miter = &host->sg_miter; 308 unsigned long flags; 309 310 local_irq_save(flags); 311 if (sg_miter_next(sg_miter)) { 312 flush_dcache_page(sg_miter->page); 313 sg_miter_stop(sg_miter); 314 } 315 local_irq_restore(flags); 316 } 317 } 318 319 if (status & MCI_DATABLOCKEND) 320 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 321 322 if (status & MCI_DATAEND || data->error) { 323 mmci_stop_data(host); 324 325 if (!data->error) 326 /* The error clause is handled above, success! */ 327 host->data_xfered += data->blksz * data->blocks; 328 329 if (!data->stop) { 330 mmci_request_end(host, data->mrq); 331 } else { 332 mmci_start_command(host, data->stop, 0); 333 } 334 } 335} 336 337static void 338mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 339 unsigned int status) 340{ 341 void __iomem *base = host->base; 342 343 host->cmd = NULL; 344 345 if (status & MCI_CMDTIMEOUT) { 346 cmd->error = -ETIMEDOUT; 347 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 348 cmd->error = -EILSEQ; 349 } else { 350 cmd->resp[0] = readl(base + MMCIRESPONSE0); 351 cmd->resp[1] = readl(base + MMCIRESPONSE1); 352 cmd->resp[2] = readl(base + MMCIRESPONSE2); 353 cmd->resp[3] = readl(base + MMCIRESPONSE3); 354 } 355 356 if (!cmd->data || cmd->error) { 357 if (host->data) 358 mmci_stop_data(host); 359 mmci_request_end(host, cmd->mrq); 360 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 361 mmci_start_data(host, cmd->data); 362 } 363} 364 365static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 366{ 367 void __iomem *base = host->base; 368 char *ptr = buffer; 369 u32 status; 370 int host_remain = host->size; 371 372 do { 373 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 374 375 if (count > remain) 376 count = remain; 377 378 if (count <= 0) 379 break; 380 381 readsl(base + MMCIFIFO, ptr, count >> 2); 382 383 ptr += count; 384 remain -= count; 385 host_remain -= count; 386 387 if (remain == 0) 388 break; 389 390 status = readl(base + MMCISTATUS); 391 } while (status & MCI_RXDATAAVLBL); 392 393 return ptr - buffer; 394} 395 396static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 397{ 398 struct variant_data *variant = host->variant; 399 void __iomem *base = host->base; 400 char *ptr = buffer; 401 402 do { 403 unsigned int count, maxcnt; 404 405 maxcnt = status & MCI_TXFIFOEMPTY ? 406 variant->fifosize : variant->fifohalfsize; 407 count = min(remain, maxcnt); 408 409 /* 410 * The ST Micro variant for SDIO transfer sizes 411 * less then 8 bytes should have clock H/W flow 412 * control disabled. 413 */ 414 if (variant->sdio && 415 mmc_card_sdio(host->mmc->card)) { 416 if (count < 8) 417 writel(readl(host->base + MMCICLOCK) & 418 ~variant->clkreg_enable, 419 host->base + MMCICLOCK); 420 else 421 writel(readl(host->base + MMCICLOCK) | 422 variant->clkreg_enable, 423 host->base + MMCICLOCK); 424 } 425 426 /* 427 * SDIO especially may want to send something that is 428 * not divisible by 4 (as opposed to card sectors 429 * etc), and the FIFO only accept full 32-bit writes. 430 * So compensate by adding +3 on the count, a single 431 * byte become a 32bit write, 7 bytes will be two 432 * 32bit writes etc. 433 */ 434 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); 435 436 ptr += count; 437 remain -= count; 438 439 if (remain == 0) 440 break; 441 442 status = readl(base + MMCISTATUS); 443 } while (status & MCI_TXFIFOHALFEMPTY); 444 445 return ptr - buffer; 446} 447 448/* 449 * PIO data transfer IRQ handler. 450 */ 451static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 452{ 453 struct mmci_host *host = dev_id; 454 struct sg_mapping_iter *sg_miter = &host->sg_miter; 455 struct variant_data *variant = host->variant; 456 void __iomem *base = host->base; 457 unsigned long flags; 458 u32 status; 459 460 status = readl(base + MMCISTATUS); 461 462 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 463 464 local_irq_save(flags); 465 466 do { 467 unsigned int remain, len; 468 char *buffer; 469 470 /* 471 * For write, we only need to test the half-empty flag 472 * here - if the FIFO is completely empty, then by 473 * definition it is more than half empty. 474 * 475 * For read, check for data available. 476 */ 477 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 478 break; 479 480 if (!sg_miter_next(sg_miter)) 481 break; 482 483 buffer = sg_miter->addr; 484 remain = sg_miter->length; 485 486 len = 0; 487 if (status & MCI_RXACTIVE) 488 len = mmci_pio_read(host, buffer, remain); 489 if (status & MCI_TXACTIVE) 490 len = mmci_pio_write(host, buffer, remain, status); 491 492 sg_miter->consumed = len; 493 494 host->size -= len; 495 remain -= len; 496 497 if (remain) 498 break; 499 500 if (status & MCI_RXACTIVE) 501 flush_dcache_page(sg_miter->page); 502 503 status = readl(base + MMCISTATUS); 504 } while (1); 505 506 sg_miter_stop(sg_miter); 507 508 local_irq_restore(flags); 509 510 /* 511 * If we're nearing the end of the read, switch to 512 * "any data available" mode. 513 */ 514 if (status & MCI_RXACTIVE && host->size < variant->fifosize) 515 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 516 517 /* 518 * If we run out of data, disable the data IRQs; this 519 * prevents a race where the FIFO becomes empty before 520 * the chip itself has disabled the data path, and 521 * stops us racing with our data end IRQ. 522 */ 523 if (host->size == 0) { 524 mmci_set_mask1(host, 0); 525 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 526 } 527 528 return IRQ_HANDLED; 529} 530 531/* 532 * Handle completion of command and data transfers. 533 */ 534static irqreturn_t mmci_irq(int irq, void *dev_id) 535{ 536 struct mmci_host *host = dev_id; 537 u32 status; 538 int ret = 0; 539 540 spin_lock(&host->lock); 541 542 do { 543 struct mmc_command *cmd; 544 struct mmc_data *data; 545 546 status = readl(host->base + MMCISTATUS); 547 548 if (host->singleirq) { 549 if (status & readl(host->base + MMCIMASK1)) 550 mmci_pio_irq(irq, dev_id); 551 552 status &= ~MCI_IRQ1MASK; 553 } 554 555 status &= readl(host->base + MMCIMASK0); 556 writel(status, host->base + MMCICLEAR); 557 558 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 559 560 data = host->data; 561 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| 562 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) 563 mmci_data_irq(host, data, status); 564 565 cmd = host->cmd; 566 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 567 mmci_cmd_irq(host, cmd, status); 568 569 ret = 1; 570 } while (status); 571 572 spin_unlock(&host->lock); 573 574 return IRQ_RETVAL(ret); 575} 576 577static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 578{ 579 struct mmci_host *host = mmc_priv(mmc); 580 unsigned long flags; 581 582 WARN_ON(host->mrq != NULL); 583 584 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 585 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", 586 mrq->data->blksz); 587 mrq->cmd->error = -EINVAL; 588 mmc_request_done(mmc, mrq); 589 return; 590 } 591 592 spin_lock_irqsave(&host->lock, flags); 593 594 host->mrq = mrq; 595 596 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 597 mmci_start_data(host, mrq->data); 598 599 mmci_start_command(host, mrq->cmd, 0); 600 601 spin_unlock_irqrestore(&host->lock, flags); 602} 603 604static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 605{ 606 struct mmci_host *host = mmc_priv(mmc); 607 u32 pwr = 0; 608 unsigned long flags; 609 int ret; 610 611 switch (ios->power_mode) { 612 case MMC_POWER_OFF: 613 if (host->vcc) 614 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); 615 break; 616 case MMC_POWER_UP: 617 if (host->vcc) { 618 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); 619 if (ret) { 620 dev_err(mmc_dev(mmc), "unable to set OCR\n"); 621 /* 622 * The .set_ios() function in the mmc_host_ops 623 * struct return void, and failing to set the 624 * power should be rare so we print an error 625 * and return here. 626 */ 627 return; 628 } 629 } 630 if (host->plat->vdd_handler) 631 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, 632 ios->power_mode); 633 /* The ST version does not have this, fall through to POWER_ON */ 634 if (host->hw_designer != AMBA_VENDOR_ST) { 635 pwr |= MCI_PWR_UP; 636 break; 637 } 638 case MMC_POWER_ON: 639 pwr |= MCI_PWR_ON; 640 break; 641 } 642 643 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 644 if (host->hw_designer != AMBA_VENDOR_ST) 645 pwr |= MCI_ROD; 646 else { 647 /* 648 * The ST Micro variant use the ROD bit for something 649 * else and only has OD (Open Drain). 650 */ 651 pwr |= MCI_OD; 652 } 653 } 654 655 spin_lock_irqsave(&host->lock, flags); 656 657 mmci_set_clkreg(host, ios->clock); 658 659 if (host->pwr != pwr) { 660 host->pwr = pwr; 661 writel(pwr, host->base + MMCIPOWER); 662 } 663 664 spin_unlock_irqrestore(&host->lock, flags); 665} 666 667static int mmci_get_ro(struct mmc_host *mmc) 668{ 669 struct mmci_host *host = mmc_priv(mmc); 670 671 if (host->gpio_wp == -ENOSYS) 672 return -ENOSYS; 673 674 return gpio_get_value_cansleep(host->gpio_wp); 675} 676 677static int mmci_get_cd(struct mmc_host *mmc) 678{ 679 struct mmci_host *host = mmc_priv(mmc); 680 struct mmci_platform_data *plat = host->plat; 681 unsigned int status; 682 683 if (host->gpio_cd == -ENOSYS) { 684 if (!plat->status) 685 return 1; /* Assume always present */ 686 687 status = plat->status(mmc_dev(host->mmc)); 688 } else 689 status = !!gpio_get_value_cansleep(host->gpio_cd) 690 ^ plat->cd_invert; 691 692 /* 693 * Use positive logic throughout - status is zero for no card, 694 * non-zero for card inserted. 695 */ 696 return status; 697} 698 699static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 700{ 701 struct mmci_host *host = dev_id; 702 703 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 704 705 return IRQ_HANDLED; 706} 707 708static const struct mmc_host_ops mmci_ops = { 709 .request = mmci_request, 710 .set_ios = mmci_set_ios, 711 .get_ro = mmci_get_ro, 712 .get_cd = mmci_get_cd, 713}; 714 715static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) 716{ 717 struct mmci_platform_data *plat = dev->dev.platform_data; 718 struct variant_data *variant = id->data; 719 struct mmci_host *host; 720 struct mmc_host *mmc; 721 int ret; 722 723 /* must have platform data */ 724 if (!plat) { 725 ret = -EINVAL; 726 goto out; 727 } 728 729 ret = amba_request_regions(dev, DRIVER_NAME); 730 if (ret) 731 goto out; 732 733 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 734 if (!mmc) { 735 ret = -ENOMEM; 736 goto rel_regions; 737 } 738 739 host = mmc_priv(mmc); 740 host->mmc = mmc; 741 742 host->gpio_wp = -ENOSYS; 743 host->gpio_cd = -ENOSYS; 744 host->gpio_cd_irq = -1; 745 746 host->hw_designer = amba_manf(dev); 747 host->hw_revision = amba_rev(dev); 748 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 749 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 750 751 host->clk = clk_get(&dev->dev, NULL); 752 if (IS_ERR(host->clk)) { 753 ret = PTR_ERR(host->clk); 754 host->clk = NULL; 755 goto host_free; 756 } 757 758 ret = clk_enable(host->clk); 759 if (ret) 760 goto clk_free; 761 762 host->plat = plat; 763 host->variant = variant; 764 host->mclk = clk_get_rate(host->clk); 765 /* 766 * According to the spec, mclk is max 100 MHz, 767 * so we try to adjust the clock down to this, 768 * (if possible). 769 */ 770 if (host->mclk > 100000000) { 771 ret = clk_set_rate(host->clk, 100000000); 772 if (ret < 0) 773 goto clk_disable; 774 host->mclk = clk_get_rate(host->clk); 775 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 776 host->mclk); 777 } 778 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 779 if (!host->base) { 780 ret = -ENOMEM; 781 goto clk_disable; 782 } 783 784 mmc->ops = &mmci_ops; 785 mmc->f_min = (host->mclk + 511) / 512; 786 /* 787 * If the platform data supplies a maximum operating 788 * frequency, this takes precedence. Else, we fall back 789 * to using the module parameter, which has a (low) 790 * default value in case it is not specified. Either 791 * value must not exceed the clock rate into the block, 792 * of course. 793 */ 794 if (plat->f_max) 795 mmc->f_max = min(host->mclk, plat->f_max); 796 else 797 mmc->f_max = min(host->mclk, fmax); 798 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 799 800#ifdef CONFIG_REGULATOR 801 /* If we're using the regulator framework, try to fetch a regulator */ 802 host->vcc = regulator_get(&dev->dev, "vmmc"); 803 if (IS_ERR(host->vcc)) 804 host->vcc = NULL; 805 else { 806 int mask = mmc_regulator_get_ocrmask(host->vcc); 807 808 if (mask < 0) 809 dev_err(&dev->dev, "error getting OCR mask (%d)\n", 810 mask); 811 else { 812 host->mmc->ocr_avail = (u32) mask; 813 if (plat->ocr_mask) 814 dev_warn(&dev->dev, 815 "Provided ocr_mask/setpower will not be used " 816 "(using regulator instead)\n"); 817 } 818 } 819#endif 820 /* Fall back to platform data if no regulator is found */ 821 if (host->vcc == NULL) 822 mmc->ocr_avail = plat->ocr_mask; 823 mmc->caps = plat->capabilities; 824 825 /* 826 * We can do SGIO 827 */ 828 mmc->max_segs = NR_SG; 829 830 /* 831 * Since only a certain number of bits are valid in the data length 832 * register, we must ensure that we don't exceed 2^num-1 bytes in a 833 * single request. 834 */ 835 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 836 837 /* 838 * Set the maximum segment size. Since we aren't doing DMA 839 * (yet) we are only limited by the data length register. 840 */ 841 mmc->max_seg_size = mmc->max_req_size; 842 843 /* 844 * Block size can be up to 2048 bytes, but must be a power of two. 845 */ 846 mmc->max_blk_size = 2048; 847 848 /* 849 * No limit on the number of blocks transferred. 850 */ 851 mmc->max_blk_count = mmc->max_req_size; 852 853 spin_lock_init(&host->lock); 854 855 writel(0, host->base + MMCIMASK0); 856 writel(0, host->base + MMCIMASK1); 857 writel(0xfff, host->base + MMCICLEAR); 858 859 if (gpio_is_valid(plat->gpio_cd)) { 860 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 861 if (ret == 0) 862 ret = gpio_direction_input(plat->gpio_cd); 863 if (ret == 0) 864 host->gpio_cd = plat->gpio_cd; 865 else if (ret != -ENOSYS) 866 goto err_gpio_cd; 867 868 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 869 mmci_cd_irq, 0, 870 DRIVER_NAME " (cd)", host); 871 if (ret >= 0) 872 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 873 } 874 if (gpio_is_valid(plat->gpio_wp)) { 875 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 876 if (ret == 0) 877 ret = gpio_direction_input(plat->gpio_wp); 878 if (ret == 0) 879 host->gpio_wp = plat->gpio_wp; 880 else if (ret != -ENOSYS) 881 goto err_gpio_wp; 882 } 883 884 if ((host->plat->status || host->gpio_cd != -ENOSYS) 885 && host->gpio_cd_irq < 0) 886 mmc->caps |= MMC_CAP_NEEDS_POLL; 887 888 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 889 if (ret) 890 goto unmap; 891 892 if (dev->irq[1] == NO_IRQ) 893 host->singleirq = true; 894 else { 895 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 896 DRIVER_NAME " (pio)", host); 897 if (ret) 898 goto irq0_free; 899 } 900 901 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 902 903 amba_set_drvdata(dev, mmc); 904 905 dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n", 906 mmc_hostname(mmc), amba_part(dev), amba_rev(dev), 907 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); 908 909 mmc_add_host(mmc); 910 911 return 0; 912 913 irq0_free: 914 free_irq(dev->irq[0], host); 915 unmap: 916 if (host->gpio_wp != -ENOSYS) 917 gpio_free(host->gpio_wp); 918 err_gpio_wp: 919 if (host->gpio_cd_irq >= 0) 920 free_irq(host->gpio_cd_irq, host); 921 if (host->gpio_cd != -ENOSYS) 922 gpio_free(host->gpio_cd); 923 err_gpio_cd: 924 iounmap(host->base); 925 clk_disable: 926 clk_disable(host->clk); 927 clk_free: 928 clk_put(host->clk); 929 host_free: 930 mmc_free_host(mmc); 931 rel_regions: 932 amba_release_regions(dev); 933 out: 934 return ret; 935} 936 937static int __devexit mmci_remove(struct amba_device *dev) 938{ 939 struct mmc_host *mmc = amba_get_drvdata(dev); 940 941 amba_set_drvdata(dev, NULL); 942 943 if (mmc) { 944 struct mmci_host *host = mmc_priv(mmc); 945 946 mmc_remove_host(mmc); 947 948 writel(0, host->base + MMCIMASK0); 949 writel(0, host->base + MMCIMASK1); 950 951 writel(0, host->base + MMCICOMMAND); 952 writel(0, host->base + MMCIDATACTRL); 953 954 free_irq(dev->irq[0], host); 955 if (!host->singleirq) 956 free_irq(dev->irq[1], host); 957 958 if (host->gpio_wp != -ENOSYS) 959 gpio_free(host->gpio_wp); 960 if (host->gpio_cd_irq >= 0) 961 free_irq(host->gpio_cd_irq, host); 962 if (host->gpio_cd != -ENOSYS) 963 gpio_free(host->gpio_cd); 964 965 iounmap(host->base); 966 clk_disable(host->clk); 967 clk_put(host->clk); 968 969 if (host->vcc) 970 mmc_regulator_set_ocr(mmc, host->vcc, 0); 971 regulator_put(host->vcc); 972 973 mmc_free_host(mmc); 974 975 amba_release_regions(dev); 976 } 977 978 return 0; 979} 980 981#ifdef CONFIG_PM 982static int mmci_suspend(struct amba_device *dev, pm_message_t state) 983{ 984 struct mmc_host *mmc = amba_get_drvdata(dev); 985 int ret = 0; 986 987 if (mmc) { 988 struct mmci_host *host = mmc_priv(mmc); 989 990 ret = mmc_suspend_host(mmc); 991 if (ret == 0) 992 writel(0, host->base + MMCIMASK0); 993 } 994 995 return ret; 996} 997 998static int mmci_resume(struct amba_device *dev) 999{ 1000 struct mmc_host *mmc = amba_get_drvdata(dev); 1001 int ret = 0; 1002 1003 if (mmc) { 1004 struct mmci_host *host = mmc_priv(mmc); 1005 1006 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1007 1008 ret = mmc_resume_host(mmc); 1009 } 1010 1011 return ret; 1012} 1013#else 1014#define mmci_suspend NULL 1015#define mmci_resume NULL 1016#endif 1017 1018static struct amba_id mmci_ids[] = { 1019 { 1020 .id = 0x00041180, 1021 .mask = 0x000fffff, 1022 .data = &variant_arm, 1023 }, 1024 { 1025 .id = 0x00041181, 1026 .mask = 0x000fffff, 1027 .data = &variant_arm, 1028 }, 1029 /* ST Micro variants */ 1030 { 1031 .id = 0x00180180, 1032 .mask = 0x00ffffff, 1033 .data = &variant_u300, 1034 }, 1035 { 1036 .id = 0x00280180, 1037 .mask = 0x00ffffff, 1038 .data = &variant_u300, 1039 }, 1040 { 1041 .id = 0x00480180, 1042 .mask = 0x00ffffff, 1043 .data = &variant_ux500, 1044 }, 1045 { 0, 0 }, 1046}; 1047 1048static struct amba_driver mmci_driver = { 1049 .drv = { 1050 .name = DRIVER_NAME, 1051 }, 1052 .probe = mmci_probe, 1053 .remove = __devexit_p(mmci_remove), 1054 .suspend = mmci_suspend, 1055 .resume = mmci_resume, 1056 .id_table = mmci_ids, 1057}; 1058 1059static int __init mmci_init(void) 1060{ 1061 return amba_driver_register(&mmci_driver); 1062} 1063 1064static void __exit mmci_exit(void) 1065{ 1066 amba_driver_unregister(&mmci_driver); 1067} 1068 1069module_init(mmci_init); 1070module_exit(mmci_exit); 1071module_param(fmax, uint, 0444); 1072 1073MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1074MODULE_LICENSE("GPL"); 1075