mmci.c revision e7f3d22289e4307b3071cc18b1d8ecc6598c0be4
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/highmem.h> 22#include <linux/log2.h> 23#include <linux/mmc/pm.h> 24#include <linux/mmc/host.h> 25#include <linux/mmc/card.h> 26#include <linux/amba/bus.h> 27#include <linux/clk.h> 28#include <linux/scatterlist.h> 29#include <linux/gpio.h> 30#include <linux/of_gpio.h> 31#include <linux/regulator/consumer.h> 32#include <linux/dmaengine.h> 33#include <linux/dma-mapping.h> 34#include <linux/amba/mmci.h> 35#include <linux/pm_runtime.h> 36#include <linux/types.h> 37#include <linux/pinctrl/consumer.h> 38 39#include <asm/div64.h> 40#include <asm/io.h> 41#include <asm/sizes.h> 42 43#include "mmci.h" 44 45#define DRIVER_NAME "mmci-pl18x" 46 47static unsigned int fmax = 515633; 48 49/** 50 * struct variant_data - MMCI variant-specific quirks 51 * @clkreg: default value for MCICLOCK register 52 * @clkreg_enable: enable value for MMCICLOCK register 53 * @datalength_bits: number of bits in the MMCIDATALENGTH register 54 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 55 * is asserted (likewise for RX) 56 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 57 * is asserted (likewise for RX) 58 * @sdio: variant supports SDIO 59 * @st_clkdiv: true if using a ST-specific clock divider algorithm 60 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 61 * @pwrreg_powerup: power up value for MMCIPOWER register 62 * @signal_direction: input/out direction of bus signals can be indicated 63 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 64 * @busy_detect: true if busy detection on dat0 is supported 65 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 66 */ 67struct variant_data { 68 unsigned int clkreg; 69 unsigned int clkreg_enable; 70 unsigned int datalength_bits; 71 unsigned int fifosize; 72 unsigned int fifohalfsize; 73 bool sdio; 74 bool st_clkdiv; 75 bool blksz_datactrl16; 76 u32 pwrreg_powerup; 77 bool signal_direction; 78 bool pwrreg_clkgate; 79 bool busy_detect; 80 bool pwrreg_nopower; 81}; 82 83static struct variant_data variant_arm = { 84 .fifosize = 16 * 4, 85 .fifohalfsize = 8 * 4, 86 .datalength_bits = 16, 87 .pwrreg_powerup = MCI_PWR_UP, 88}; 89 90static struct variant_data variant_arm_extended_fifo = { 91 .fifosize = 128 * 4, 92 .fifohalfsize = 64 * 4, 93 .datalength_bits = 16, 94 .pwrreg_powerup = MCI_PWR_UP, 95}; 96 97static struct variant_data variant_arm_extended_fifo_hwfc = { 98 .fifosize = 128 * 4, 99 .fifohalfsize = 64 * 4, 100 .clkreg_enable = MCI_ARM_HWFCEN, 101 .datalength_bits = 16, 102 .pwrreg_powerup = MCI_PWR_UP, 103}; 104 105static struct variant_data variant_u300 = { 106 .fifosize = 16 * 4, 107 .fifohalfsize = 8 * 4, 108 .clkreg_enable = MCI_ST_U300_HWFCEN, 109 .datalength_bits = 16, 110 .sdio = true, 111 .pwrreg_powerup = MCI_PWR_ON, 112 .signal_direction = true, 113 .pwrreg_clkgate = true, 114 .pwrreg_nopower = true, 115}; 116 117static struct variant_data variant_nomadik = { 118 .fifosize = 16 * 4, 119 .fifohalfsize = 8 * 4, 120 .clkreg = MCI_CLK_ENABLE, 121 .datalength_bits = 24, 122 .sdio = true, 123 .st_clkdiv = true, 124 .pwrreg_powerup = MCI_PWR_ON, 125 .signal_direction = true, 126 .pwrreg_clkgate = true, 127 .pwrreg_nopower = true, 128}; 129 130static struct variant_data variant_ux500 = { 131 .fifosize = 30 * 4, 132 .fifohalfsize = 8 * 4, 133 .clkreg = MCI_CLK_ENABLE, 134 .clkreg_enable = MCI_ST_UX500_HWFCEN, 135 .datalength_bits = 24, 136 .sdio = true, 137 .st_clkdiv = true, 138 .pwrreg_powerup = MCI_PWR_ON, 139 .signal_direction = true, 140 .pwrreg_clkgate = true, 141 .busy_detect = true, 142 .pwrreg_nopower = true, 143}; 144 145static struct variant_data variant_ux500v2 = { 146 .fifosize = 30 * 4, 147 .fifohalfsize = 8 * 4, 148 .clkreg = MCI_CLK_ENABLE, 149 .clkreg_enable = MCI_ST_UX500_HWFCEN, 150 .datalength_bits = 24, 151 .sdio = true, 152 .st_clkdiv = true, 153 .blksz_datactrl16 = true, 154 .pwrreg_powerup = MCI_PWR_ON, 155 .signal_direction = true, 156 .pwrreg_clkgate = true, 157 .busy_detect = true, 158 .pwrreg_nopower = true, 159}; 160 161static int mmci_card_busy(struct mmc_host *mmc) 162{ 163 struct mmci_host *host = mmc_priv(mmc); 164 unsigned long flags; 165 int busy = 0; 166 167 pm_runtime_get_sync(mmc_dev(mmc)); 168 169 spin_lock_irqsave(&host->lock, flags); 170 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 171 busy = 1; 172 spin_unlock_irqrestore(&host->lock, flags); 173 174 pm_runtime_mark_last_busy(mmc_dev(mmc)); 175 pm_runtime_put_autosuspend(mmc_dev(mmc)); 176 177 return busy; 178} 179 180/* 181 * Validate mmc prerequisites 182 */ 183static int mmci_validate_data(struct mmci_host *host, 184 struct mmc_data *data) 185{ 186 if (!data) 187 return 0; 188 189 if (!is_power_of_2(data->blksz)) { 190 dev_err(mmc_dev(host->mmc), 191 "unsupported block size (%d bytes)\n", data->blksz); 192 return -EINVAL; 193 } 194 195 return 0; 196} 197 198static void mmci_reg_delay(struct mmci_host *host) 199{ 200 /* 201 * According to the spec, at least three feedback clock cycles 202 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 203 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 204 * Worst delay time during card init is at 100 kHz => 30 us. 205 * Worst delay time when up and running is at 25 MHz => 120 ns. 206 */ 207 if (host->cclk < 25000000) 208 udelay(30); 209 else 210 ndelay(120); 211} 212 213/* 214 * This must be called with host->lock held 215 */ 216static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 217{ 218 if (host->clk_reg != clk) { 219 host->clk_reg = clk; 220 writel(clk, host->base + MMCICLOCK); 221 } 222} 223 224/* 225 * This must be called with host->lock held 226 */ 227static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 228{ 229 if (host->pwr_reg != pwr) { 230 host->pwr_reg = pwr; 231 writel(pwr, host->base + MMCIPOWER); 232 } 233} 234 235/* 236 * This must be called with host->lock held 237 */ 238static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 239{ 240 /* Keep ST Micro busy mode if enabled */ 241 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 242 243 if (host->datactrl_reg != datactrl) { 244 host->datactrl_reg = datactrl; 245 writel(datactrl, host->base + MMCIDATACTRL); 246 } 247} 248 249/* 250 * This must be called with host->lock held 251 */ 252static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 253{ 254 struct variant_data *variant = host->variant; 255 u32 clk = variant->clkreg; 256 257 /* Make sure cclk reflects the current calculated clock */ 258 host->cclk = 0; 259 260 if (desired) { 261 if (desired >= host->mclk) { 262 clk = MCI_CLK_BYPASS; 263 if (variant->st_clkdiv) 264 clk |= MCI_ST_UX500_NEG_EDGE; 265 host->cclk = host->mclk; 266 } else if (variant->st_clkdiv) { 267 /* 268 * DB8500 TRM says f = mclk / (clkdiv + 2) 269 * => clkdiv = (mclk / f) - 2 270 * Round the divider up so we don't exceed the max 271 * frequency 272 */ 273 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 274 if (clk >= 256) 275 clk = 255; 276 host->cclk = host->mclk / (clk + 2); 277 } else { 278 /* 279 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 280 * => clkdiv = mclk / (2 * f) - 1 281 */ 282 clk = host->mclk / (2 * desired) - 1; 283 if (clk >= 256) 284 clk = 255; 285 host->cclk = host->mclk / (2 * (clk + 1)); 286 } 287 288 clk |= variant->clkreg_enable; 289 clk |= MCI_CLK_ENABLE; 290 /* This hasn't proven to be worthwhile */ 291 /* clk |= MCI_CLK_PWRSAVE; */ 292 } 293 294 /* Set actual clock for debug */ 295 host->mmc->actual_clock = host->cclk; 296 297 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 298 clk |= MCI_4BIT_BUS; 299 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 300 clk |= MCI_ST_8BIT_BUS; 301 302 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 303 clk |= MCI_ST_UX500_NEG_EDGE; 304 305 mmci_write_clkreg(host, clk); 306} 307 308static void 309mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 310{ 311 writel(0, host->base + MMCICOMMAND); 312 313 BUG_ON(host->data); 314 315 host->mrq = NULL; 316 host->cmd = NULL; 317 318 mmc_request_done(host->mmc, mrq); 319 320 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 321 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 322} 323 324static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 325{ 326 void __iomem *base = host->base; 327 328 if (host->singleirq) { 329 unsigned int mask0 = readl(base + MMCIMASK0); 330 331 mask0 &= ~MCI_IRQ1MASK; 332 mask0 |= mask; 333 334 writel(mask0, base + MMCIMASK0); 335 } 336 337 writel(mask, base + MMCIMASK1); 338} 339 340static void mmci_stop_data(struct mmci_host *host) 341{ 342 mmci_write_datactrlreg(host, 0); 343 mmci_set_mask1(host, 0); 344 host->data = NULL; 345} 346 347static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 348{ 349 unsigned int flags = SG_MITER_ATOMIC; 350 351 if (data->flags & MMC_DATA_READ) 352 flags |= SG_MITER_TO_SG; 353 else 354 flags |= SG_MITER_FROM_SG; 355 356 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 357} 358 359/* 360 * All the DMA operation mode stuff goes inside this ifdef. 361 * This assumes that you have a generic DMA device interface, 362 * no custom DMA interfaces are supported. 363 */ 364#ifdef CONFIG_DMA_ENGINE 365static void mmci_dma_setup(struct mmci_host *host) 366{ 367 struct mmci_platform_data *plat = host->plat; 368 const char *rxname, *txname; 369 dma_cap_mask_t mask; 370 371 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 372 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 373 374 /* initialize pre request cookie */ 375 host->next_data.cookie = 1; 376 377 /* Try to acquire a generic DMA engine slave channel */ 378 dma_cap_zero(mask); 379 dma_cap_set(DMA_SLAVE, mask); 380 381 if (plat && plat->dma_filter) { 382 if (!host->dma_rx_channel && plat->dma_rx_param) { 383 host->dma_rx_channel = dma_request_channel(mask, 384 plat->dma_filter, 385 plat->dma_rx_param); 386 /* E.g if no DMA hardware is present */ 387 if (!host->dma_rx_channel) 388 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); 389 } 390 391 if (!host->dma_tx_channel && plat->dma_tx_param) { 392 host->dma_tx_channel = dma_request_channel(mask, 393 plat->dma_filter, 394 plat->dma_tx_param); 395 if (!host->dma_tx_channel) 396 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); 397 } 398 } 399 400 /* 401 * If only an RX channel is specified, the driver will 402 * attempt to use it bidirectionally, however if it is 403 * is specified but cannot be located, DMA will be disabled. 404 */ 405 if (host->dma_rx_channel && !host->dma_tx_channel) 406 host->dma_tx_channel = host->dma_rx_channel; 407 408 if (host->dma_rx_channel) 409 rxname = dma_chan_name(host->dma_rx_channel); 410 else 411 rxname = "none"; 412 413 if (host->dma_tx_channel) 414 txname = dma_chan_name(host->dma_tx_channel); 415 else 416 txname = "none"; 417 418 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 419 rxname, txname); 420 421 /* 422 * Limit the maximum segment size in any SG entry according to 423 * the parameters of the DMA engine device. 424 */ 425 if (host->dma_tx_channel) { 426 struct device *dev = host->dma_tx_channel->device->dev; 427 unsigned int max_seg_size = dma_get_max_seg_size(dev); 428 429 if (max_seg_size < host->mmc->max_seg_size) 430 host->mmc->max_seg_size = max_seg_size; 431 } 432 if (host->dma_rx_channel) { 433 struct device *dev = host->dma_rx_channel->device->dev; 434 unsigned int max_seg_size = dma_get_max_seg_size(dev); 435 436 if (max_seg_size < host->mmc->max_seg_size) 437 host->mmc->max_seg_size = max_seg_size; 438 } 439} 440 441/* 442 * This is used in or so inline it 443 * so it can be discarded. 444 */ 445static inline void mmci_dma_release(struct mmci_host *host) 446{ 447 struct mmci_platform_data *plat = host->plat; 448 449 if (host->dma_rx_channel) 450 dma_release_channel(host->dma_rx_channel); 451 if (host->dma_tx_channel && plat->dma_tx_param) 452 dma_release_channel(host->dma_tx_channel); 453 host->dma_rx_channel = host->dma_tx_channel = NULL; 454} 455 456static void mmci_dma_data_error(struct mmci_host *host) 457{ 458 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 459 dmaengine_terminate_all(host->dma_current); 460 host->dma_current = NULL; 461 host->dma_desc_current = NULL; 462 host->data->host_cookie = 0; 463} 464 465static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 466{ 467 struct dma_chan *chan; 468 enum dma_data_direction dir; 469 470 if (data->flags & MMC_DATA_READ) { 471 dir = DMA_FROM_DEVICE; 472 chan = host->dma_rx_channel; 473 } else { 474 dir = DMA_TO_DEVICE; 475 chan = host->dma_tx_channel; 476 } 477 478 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 479} 480 481static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 482{ 483 u32 status; 484 int i; 485 486 /* Wait up to 1ms for the DMA to complete */ 487 for (i = 0; ; i++) { 488 status = readl(host->base + MMCISTATUS); 489 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 490 break; 491 udelay(10); 492 } 493 494 /* 495 * Check to see whether we still have some data left in the FIFO - 496 * this catches DMA controllers which are unable to monitor the 497 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 498 * contiguous buffers. On TX, we'll get a FIFO underrun error. 499 */ 500 if (status & MCI_RXDATAAVLBLMASK) { 501 mmci_dma_data_error(host); 502 if (!data->error) 503 data->error = -EIO; 504 } 505 506 if (!data->host_cookie) 507 mmci_dma_unmap(host, data); 508 509 /* 510 * Use of DMA with scatter-gather is impossible. 511 * Give up with DMA and switch back to PIO mode. 512 */ 513 if (status & MCI_RXDATAAVLBLMASK) { 514 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 515 mmci_dma_release(host); 516 } 517 518 host->dma_current = NULL; 519 host->dma_desc_current = NULL; 520} 521 522/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 523static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 524 struct dma_chan **dma_chan, 525 struct dma_async_tx_descriptor **dma_desc) 526{ 527 struct variant_data *variant = host->variant; 528 struct dma_slave_config conf = { 529 .src_addr = host->phybase + MMCIFIFO, 530 .dst_addr = host->phybase + MMCIFIFO, 531 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 532 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 533 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 534 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 535 .device_fc = false, 536 }; 537 struct dma_chan *chan; 538 struct dma_device *device; 539 struct dma_async_tx_descriptor *desc; 540 enum dma_data_direction buffer_dirn; 541 int nr_sg; 542 543 if (data->flags & MMC_DATA_READ) { 544 conf.direction = DMA_DEV_TO_MEM; 545 buffer_dirn = DMA_FROM_DEVICE; 546 chan = host->dma_rx_channel; 547 } else { 548 conf.direction = DMA_MEM_TO_DEV; 549 buffer_dirn = DMA_TO_DEVICE; 550 chan = host->dma_tx_channel; 551 } 552 553 /* If there's no DMA channel, fall back to PIO */ 554 if (!chan) 555 return -EINVAL; 556 557 /* If less than or equal to the fifo size, don't bother with DMA */ 558 if (data->blksz * data->blocks <= variant->fifosize) 559 return -EINVAL; 560 561 device = chan->device; 562 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 563 if (nr_sg == 0) 564 return -EINVAL; 565 566 dmaengine_slave_config(chan, &conf); 567 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 568 conf.direction, DMA_CTRL_ACK); 569 if (!desc) 570 goto unmap_exit; 571 572 *dma_chan = chan; 573 *dma_desc = desc; 574 575 return 0; 576 577 unmap_exit: 578 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 579 return -ENOMEM; 580} 581 582static inline int mmci_dma_prep_data(struct mmci_host *host, 583 struct mmc_data *data) 584{ 585 /* Check if next job is already prepared. */ 586 if (host->dma_current && host->dma_desc_current) 587 return 0; 588 589 /* No job were prepared thus do it now. */ 590 return __mmci_dma_prep_data(host, data, &host->dma_current, 591 &host->dma_desc_current); 592} 593 594static inline int mmci_dma_prep_next(struct mmci_host *host, 595 struct mmc_data *data) 596{ 597 struct mmci_host_next *nd = &host->next_data; 598 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 599} 600 601static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 602{ 603 int ret; 604 struct mmc_data *data = host->data; 605 606 ret = mmci_dma_prep_data(host, host->data); 607 if (ret) 608 return ret; 609 610 /* Okay, go for it. */ 611 dev_vdbg(mmc_dev(host->mmc), 612 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 613 data->sg_len, data->blksz, data->blocks, data->flags); 614 dmaengine_submit(host->dma_desc_current); 615 dma_async_issue_pending(host->dma_current); 616 617 datactrl |= MCI_DPSM_DMAENABLE; 618 619 /* Trigger the DMA transfer */ 620 mmci_write_datactrlreg(host, datactrl); 621 622 /* 623 * Let the MMCI say when the data is ended and it's time 624 * to fire next DMA request. When that happens, MMCI will 625 * call mmci_data_end() 626 */ 627 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 628 host->base + MMCIMASK0); 629 return 0; 630} 631 632static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 633{ 634 struct mmci_host_next *next = &host->next_data; 635 636 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 637 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 638 639 host->dma_desc_current = next->dma_desc; 640 host->dma_current = next->dma_chan; 641 next->dma_desc = NULL; 642 next->dma_chan = NULL; 643} 644 645static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 646 bool is_first_req) 647{ 648 struct mmci_host *host = mmc_priv(mmc); 649 struct mmc_data *data = mrq->data; 650 struct mmci_host_next *nd = &host->next_data; 651 652 if (!data) 653 return; 654 655 BUG_ON(data->host_cookie); 656 657 if (mmci_validate_data(host, data)) 658 return; 659 660 if (!mmci_dma_prep_next(host, data)) 661 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 662} 663 664static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 665 int err) 666{ 667 struct mmci_host *host = mmc_priv(mmc); 668 struct mmc_data *data = mrq->data; 669 670 if (!data || !data->host_cookie) 671 return; 672 673 mmci_dma_unmap(host, data); 674 675 if (err) { 676 struct mmci_host_next *next = &host->next_data; 677 struct dma_chan *chan; 678 if (data->flags & MMC_DATA_READ) 679 chan = host->dma_rx_channel; 680 else 681 chan = host->dma_tx_channel; 682 dmaengine_terminate_all(chan); 683 684 next->dma_desc = NULL; 685 next->dma_chan = NULL; 686 } 687} 688 689#else 690/* Blank functions if the DMA engine is not available */ 691static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 692{ 693} 694static inline void mmci_dma_setup(struct mmci_host *host) 695{ 696} 697 698static inline void mmci_dma_release(struct mmci_host *host) 699{ 700} 701 702static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 703{ 704} 705 706static inline void mmci_dma_finalize(struct mmci_host *host, 707 struct mmc_data *data) 708{ 709} 710 711static inline void mmci_dma_data_error(struct mmci_host *host) 712{ 713} 714 715static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 716{ 717 return -ENOSYS; 718} 719 720#define mmci_pre_request NULL 721#define mmci_post_request NULL 722 723#endif 724 725static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 726{ 727 struct variant_data *variant = host->variant; 728 unsigned int datactrl, timeout, irqmask; 729 unsigned long long clks; 730 void __iomem *base; 731 int blksz_bits; 732 733 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 734 data->blksz, data->blocks, data->flags); 735 736 host->data = data; 737 host->size = data->blksz * data->blocks; 738 data->bytes_xfered = 0; 739 740 clks = (unsigned long long)data->timeout_ns * host->cclk; 741 do_div(clks, 1000000000UL); 742 743 timeout = data->timeout_clks + (unsigned int)clks; 744 745 base = host->base; 746 writel(timeout, base + MMCIDATATIMER); 747 writel(host->size, base + MMCIDATALENGTH); 748 749 blksz_bits = ffs(data->blksz) - 1; 750 BUG_ON(1 << blksz_bits != data->blksz); 751 752 if (variant->blksz_datactrl16) 753 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 754 else 755 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 756 757 if (data->flags & MMC_DATA_READ) 758 datactrl |= MCI_DPSM_DIRECTION; 759 760 /* The ST Micro variants has a special bit to enable SDIO */ 761 if (variant->sdio && host->mmc->card) 762 if (mmc_card_sdio(host->mmc->card)) { 763 /* 764 * The ST Micro variants has a special bit 765 * to enable SDIO. 766 */ 767 u32 clk; 768 769 datactrl |= MCI_ST_DPSM_SDIOEN; 770 771 /* 772 * The ST Micro variant for SDIO small write transfers 773 * needs to have clock H/W flow control disabled, 774 * otherwise the transfer will not start. The threshold 775 * depends on the rate of MCLK. 776 */ 777 if (data->flags & MMC_DATA_WRITE && 778 (host->size < 8 || 779 (host->size <= 8 && host->mclk > 50000000))) 780 clk = host->clk_reg & ~variant->clkreg_enable; 781 else 782 clk = host->clk_reg | variant->clkreg_enable; 783 784 mmci_write_clkreg(host, clk); 785 } 786 787 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) 788 datactrl |= MCI_ST_DPSM_DDRMODE; 789 790 /* 791 * Attempt to use DMA operation mode, if this 792 * should fail, fall back to PIO mode 793 */ 794 if (!mmci_dma_start_data(host, datactrl)) 795 return; 796 797 /* IRQ mode, map the SG list for CPU reading/writing */ 798 mmci_init_sg(host, data); 799 800 if (data->flags & MMC_DATA_READ) { 801 irqmask = MCI_RXFIFOHALFFULLMASK; 802 803 /* 804 * If we have less than the fifo 'half-full' threshold to 805 * transfer, trigger a PIO interrupt as soon as any data 806 * is available. 807 */ 808 if (host->size < variant->fifohalfsize) 809 irqmask |= MCI_RXDATAAVLBLMASK; 810 } else { 811 /* 812 * We don't actually need to include "FIFO empty" here 813 * since its implicit in "FIFO half empty". 814 */ 815 irqmask = MCI_TXFIFOHALFEMPTYMASK; 816 } 817 818 mmci_write_datactrlreg(host, datactrl); 819 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 820 mmci_set_mask1(host, irqmask); 821} 822 823static void 824mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 825{ 826 void __iomem *base = host->base; 827 828 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 829 cmd->opcode, cmd->arg, cmd->flags); 830 831 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 832 writel(0, base + MMCICOMMAND); 833 udelay(1); 834 } 835 836 c |= cmd->opcode | MCI_CPSM_ENABLE; 837 if (cmd->flags & MMC_RSP_PRESENT) { 838 if (cmd->flags & MMC_RSP_136) 839 c |= MCI_CPSM_LONGRSP; 840 c |= MCI_CPSM_RESPONSE; 841 } 842 if (/*interrupt*/0) 843 c |= MCI_CPSM_INTERRUPT; 844 845 host->cmd = cmd; 846 847 writel(cmd->arg, base + MMCIARGUMENT); 848 writel(c, base + MMCICOMMAND); 849} 850 851static void 852mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 853 unsigned int status) 854{ 855 /* First check for errors */ 856 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 857 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 858 u32 remain, success; 859 860 /* Terminate the DMA transfer */ 861 if (dma_inprogress(host)) { 862 mmci_dma_data_error(host); 863 mmci_dma_unmap(host, data); 864 } 865 866 /* 867 * Calculate how far we are into the transfer. Note that 868 * the data counter gives the number of bytes transferred 869 * on the MMC bus, not on the host side. On reads, this 870 * can be as much as a FIFO-worth of data ahead. This 871 * matters for FIFO overruns only. 872 */ 873 remain = readl(host->base + MMCIDATACNT); 874 success = data->blksz * data->blocks - remain; 875 876 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 877 status, success); 878 if (status & MCI_DATACRCFAIL) { 879 /* Last block was not successful */ 880 success -= 1; 881 data->error = -EILSEQ; 882 } else if (status & MCI_DATATIMEOUT) { 883 data->error = -ETIMEDOUT; 884 } else if (status & MCI_STARTBITERR) { 885 data->error = -ECOMM; 886 } else if (status & MCI_TXUNDERRUN) { 887 data->error = -EIO; 888 } else if (status & MCI_RXOVERRUN) { 889 if (success > host->variant->fifosize) 890 success -= host->variant->fifosize; 891 else 892 success = 0; 893 data->error = -EIO; 894 } 895 data->bytes_xfered = round_down(success, data->blksz); 896 } 897 898 if (status & MCI_DATABLOCKEND) 899 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 900 901 if (status & MCI_DATAEND || data->error) { 902 if (dma_inprogress(host)) 903 mmci_dma_finalize(host, data); 904 mmci_stop_data(host); 905 906 if (!data->error) 907 /* The error clause is handled above, success! */ 908 data->bytes_xfered = data->blksz * data->blocks; 909 910 if (!data->stop || host->mrq->sbc) { 911 mmci_request_end(host, data->mrq); 912 } else { 913 mmci_start_command(host, data->stop, 0); 914 } 915 } 916} 917 918static void 919mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 920 unsigned int status) 921{ 922 void __iomem *base = host->base; 923 bool sbc = (cmd == host->mrq->sbc); 924 925 host->cmd = NULL; 926 927 if (status & MCI_CMDTIMEOUT) { 928 cmd->error = -ETIMEDOUT; 929 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 930 cmd->error = -EILSEQ; 931 } else { 932 cmd->resp[0] = readl(base + MMCIRESPONSE0); 933 cmd->resp[1] = readl(base + MMCIRESPONSE1); 934 cmd->resp[2] = readl(base + MMCIRESPONSE2); 935 cmd->resp[3] = readl(base + MMCIRESPONSE3); 936 } 937 938 if ((!sbc && !cmd->data) || cmd->error) { 939 if (host->data) { 940 /* Terminate the DMA transfer */ 941 if (dma_inprogress(host)) { 942 mmci_dma_data_error(host); 943 mmci_dma_unmap(host, host->data); 944 } 945 mmci_stop_data(host); 946 } 947 mmci_request_end(host, host->mrq); 948 } else if (sbc) { 949 mmci_start_command(host, host->mrq->cmd, 0); 950 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 951 mmci_start_data(host, cmd->data); 952 } 953} 954 955static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 956{ 957 void __iomem *base = host->base; 958 char *ptr = buffer; 959 u32 status; 960 int host_remain = host->size; 961 962 do { 963 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 964 965 if (count > remain) 966 count = remain; 967 968 if (count <= 0) 969 break; 970 971 /* 972 * SDIO especially may want to send something that is 973 * not divisible by 4 (as opposed to card sectors 974 * etc). Therefore make sure to always read the last bytes 975 * while only doing full 32-bit reads towards the FIFO. 976 */ 977 if (unlikely(count & 0x3)) { 978 if (count < 4) { 979 unsigned char buf[4]; 980 ioread32_rep(base + MMCIFIFO, buf, 1); 981 memcpy(ptr, buf, count); 982 } else { 983 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 984 count &= ~0x3; 985 } 986 } else { 987 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 988 } 989 990 ptr += count; 991 remain -= count; 992 host_remain -= count; 993 994 if (remain == 0) 995 break; 996 997 status = readl(base + MMCISTATUS); 998 } while (status & MCI_RXDATAAVLBL); 999 1000 return ptr - buffer; 1001} 1002 1003static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1004{ 1005 struct variant_data *variant = host->variant; 1006 void __iomem *base = host->base; 1007 char *ptr = buffer; 1008 1009 do { 1010 unsigned int count, maxcnt; 1011 1012 maxcnt = status & MCI_TXFIFOEMPTY ? 1013 variant->fifosize : variant->fifohalfsize; 1014 count = min(remain, maxcnt); 1015 1016 /* 1017 * SDIO especially may want to send something that is 1018 * not divisible by 4 (as opposed to card sectors 1019 * etc), and the FIFO only accept full 32-bit writes. 1020 * So compensate by adding +3 on the count, a single 1021 * byte become a 32bit write, 7 bytes will be two 1022 * 32bit writes etc. 1023 */ 1024 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1025 1026 ptr += count; 1027 remain -= count; 1028 1029 if (remain == 0) 1030 break; 1031 1032 status = readl(base + MMCISTATUS); 1033 } while (status & MCI_TXFIFOHALFEMPTY); 1034 1035 return ptr - buffer; 1036} 1037 1038/* 1039 * PIO data transfer IRQ handler. 1040 */ 1041static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1042{ 1043 struct mmci_host *host = dev_id; 1044 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1045 struct variant_data *variant = host->variant; 1046 void __iomem *base = host->base; 1047 unsigned long flags; 1048 u32 status; 1049 1050 status = readl(base + MMCISTATUS); 1051 1052 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1053 1054 local_irq_save(flags); 1055 1056 do { 1057 unsigned int remain, len; 1058 char *buffer; 1059 1060 /* 1061 * For write, we only need to test the half-empty flag 1062 * here - if the FIFO is completely empty, then by 1063 * definition it is more than half empty. 1064 * 1065 * For read, check for data available. 1066 */ 1067 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1068 break; 1069 1070 if (!sg_miter_next(sg_miter)) 1071 break; 1072 1073 buffer = sg_miter->addr; 1074 remain = sg_miter->length; 1075 1076 len = 0; 1077 if (status & MCI_RXACTIVE) 1078 len = mmci_pio_read(host, buffer, remain); 1079 if (status & MCI_TXACTIVE) 1080 len = mmci_pio_write(host, buffer, remain, status); 1081 1082 sg_miter->consumed = len; 1083 1084 host->size -= len; 1085 remain -= len; 1086 1087 if (remain) 1088 break; 1089 1090 status = readl(base + MMCISTATUS); 1091 } while (1); 1092 1093 sg_miter_stop(sg_miter); 1094 1095 local_irq_restore(flags); 1096 1097 /* 1098 * If we have less than the fifo 'half-full' threshold to transfer, 1099 * trigger a PIO interrupt as soon as any data is available. 1100 */ 1101 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1102 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1103 1104 /* 1105 * If we run out of data, disable the data IRQs; this 1106 * prevents a race where the FIFO becomes empty before 1107 * the chip itself has disabled the data path, and 1108 * stops us racing with our data end IRQ. 1109 */ 1110 if (host->size == 0) { 1111 mmci_set_mask1(host, 0); 1112 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1113 } 1114 1115 return IRQ_HANDLED; 1116} 1117 1118/* 1119 * Handle completion of command and data transfers. 1120 */ 1121static irqreturn_t mmci_irq(int irq, void *dev_id) 1122{ 1123 struct mmci_host *host = dev_id; 1124 u32 status; 1125 int ret = 0; 1126 1127 spin_lock(&host->lock); 1128 1129 do { 1130 struct mmc_command *cmd; 1131 struct mmc_data *data; 1132 1133 status = readl(host->base + MMCISTATUS); 1134 1135 if (host->singleirq) { 1136 if (status & readl(host->base + MMCIMASK1)) 1137 mmci_pio_irq(irq, dev_id); 1138 1139 status &= ~MCI_IRQ1MASK; 1140 } 1141 1142 status &= readl(host->base + MMCIMASK0); 1143 writel(status, host->base + MMCICLEAR); 1144 1145 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1146 1147 cmd = host->cmd; 1148 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT| 1149 MCI_CMDRESPEND) && cmd) 1150 mmci_cmd_irq(host, cmd, status); 1151 1152 data = host->data; 1153 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1154 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1155 MCI_DATABLOCKEND) && data) 1156 mmci_data_irq(host, data, status); 1157 1158 ret = 1; 1159 } while (status); 1160 1161 spin_unlock(&host->lock); 1162 1163 return IRQ_RETVAL(ret); 1164} 1165 1166static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1167{ 1168 struct mmci_host *host = mmc_priv(mmc); 1169 unsigned long flags; 1170 1171 WARN_ON(host->mrq != NULL); 1172 1173 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1174 if (mrq->cmd->error) { 1175 mmc_request_done(mmc, mrq); 1176 return; 1177 } 1178 1179 pm_runtime_get_sync(mmc_dev(mmc)); 1180 1181 spin_lock_irqsave(&host->lock, flags); 1182 1183 host->mrq = mrq; 1184 1185 if (mrq->data) 1186 mmci_get_next_data(host, mrq->data); 1187 1188 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1189 mmci_start_data(host, mrq->data); 1190 1191 if (mrq->sbc) 1192 mmci_start_command(host, mrq->sbc, 0); 1193 else 1194 mmci_start_command(host, mrq->cmd, 0); 1195 1196 spin_unlock_irqrestore(&host->lock, flags); 1197} 1198 1199static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1200{ 1201 struct mmci_host *host = mmc_priv(mmc); 1202 struct variant_data *variant = host->variant; 1203 u32 pwr = 0; 1204 unsigned long flags; 1205 int ret; 1206 1207 pm_runtime_get_sync(mmc_dev(mmc)); 1208 1209 if (host->plat->ios_handler && 1210 host->plat->ios_handler(mmc_dev(mmc), ios)) 1211 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1212 1213 switch (ios->power_mode) { 1214 case MMC_POWER_OFF: 1215 if (!IS_ERR(mmc->supply.vmmc)) 1216 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1217 1218 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1219 regulator_disable(mmc->supply.vqmmc); 1220 host->vqmmc_enabled = false; 1221 } 1222 1223 break; 1224 case MMC_POWER_UP: 1225 if (!IS_ERR(mmc->supply.vmmc)) 1226 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1227 1228 /* 1229 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1230 * and instead uses MCI_PWR_ON so apply whatever value is 1231 * configured in the variant data. 1232 */ 1233 pwr |= variant->pwrreg_powerup; 1234 1235 break; 1236 case MMC_POWER_ON: 1237 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1238 ret = regulator_enable(mmc->supply.vqmmc); 1239 if (ret < 0) 1240 dev_err(mmc_dev(mmc), 1241 "failed to enable vqmmc regulator\n"); 1242 else 1243 host->vqmmc_enabled = true; 1244 } 1245 1246 pwr |= MCI_PWR_ON; 1247 break; 1248 } 1249 1250 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1251 /* 1252 * The ST Micro variant has some additional bits 1253 * indicating signal direction for the signals in 1254 * the SD/MMC bus and feedback-clock usage. 1255 */ 1256 pwr |= host->plat->sigdir; 1257 1258 if (ios->bus_width == MMC_BUS_WIDTH_4) 1259 pwr &= ~MCI_ST_DATA74DIREN; 1260 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1261 pwr &= (~MCI_ST_DATA74DIREN & 1262 ~MCI_ST_DATA31DIREN & 1263 ~MCI_ST_DATA2DIREN); 1264 } 1265 1266 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1267 if (host->hw_designer != AMBA_VENDOR_ST) 1268 pwr |= MCI_ROD; 1269 else { 1270 /* 1271 * The ST Micro variant use the ROD bit for something 1272 * else and only has OD (Open Drain). 1273 */ 1274 pwr |= MCI_OD; 1275 } 1276 } 1277 1278 /* 1279 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1280 * gating the clock, the MCI_PWR_ON bit is cleared. 1281 */ 1282 if (!ios->clock && variant->pwrreg_clkgate) 1283 pwr &= ~MCI_PWR_ON; 1284 1285 spin_lock_irqsave(&host->lock, flags); 1286 1287 mmci_set_clkreg(host, ios->clock); 1288 mmci_write_pwrreg(host, pwr); 1289 mmci_reg_delay(host); 1290 1291 spin_unlock_irqrestore(&host->lock, flags); 1292 1293 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1294 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1295} 1296 1297static int mmci_get_ro(struct mmc_host *mmc) 1298{ 1299 struct mmci_host *host = mmc_priv(mmc); 1300 1301 if (host->gpio_wp == -ENOSYS) 1302 return -ENOSYS; 1303 1304 return gpio_get_value_cansleep(host->gpio_wp); 1305} 1306 1307static int mmci_get_cd(struct mmc_host *mmc) 1308{ 1309 struct mmci_host *host = mmc_priv(mmc); 1310 struct mmci_platform_data *plat = host->plat; 1311 unsigned int status; 1312 1313 if (host->gpio_cd == -ENOSYS) { 1314 if (!plat->status) 1315 return 1; /* Assume always present */ 1316 1317 status = plat->status(mmc_dev(host->mmc)); 1318 } else 1319 status = !!gpio_get_value_cansleep(host->gpio_cd) 1320 ^ plat->cd_invert; 1321 1322 /* 1323 * Use positive logic throughout - status is zero for no card, 1324 * non-zero for card inserted. 1325 */ 1326 return status; 1327} 1328 1329static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1330{ 1331 int ret = 0; 1332 1333 if (!IS_ERR(mmc->supply.vqmmc)) { 1334 1335 pm_runtime_get_sync(mmc_dev(mmc)); 1336 1337 switch (ios->signal_voltage) { 1338 case MMC_SIGNAL_VOLTAGE_330: 1339 ret = regulator_set_voltage(mmc->supply.vqmmc, 1340 2700000, 3600000); 1341 break; 1342 case MMC_SIGNAL_VOLTAGE_180: 1343 ret = regulator_set_voltage(mmc->supply.vqmmc, 1344 1700000, 1950000); 1345 break; 1346 case MMC_SIGNAL_VOLTAGE_120: 1347 ret = regulator_set_voltage(mmc->supply.vqmmc, 1348 1100000, 1300000); 1349 break; 1350 } 1351 1352 if (ret) 1353 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1354 1355 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1356 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1357 } 1358 1359 return ret; 1360} 1361 1362static irqreturn_t mmci_cd_irq(int irq, void *dev_id) 1363{ 1364 struct mmci_host *host = dev_id; 1365 1366 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 1367 1368 return IRQ_HANDLED; 1369} 1370 1371static struct mmc_host_ops mmci_ops = { 1372 .request = mmci_request, 1373 .pre_req = mmci_pre_request, 1374 .post_req = mmci_post_request, 1375 .set_ios = mmci_set_ios, 1376 .get_ro = mmci_get_ro, 1377 .get_cd = mmci_get_cd, 1378 .start_signal_voltage_switch = mmci_sig_volt_switch, 1379}; 1380 1381#ifdef CONFIG_OF 1382static void mmci_dt_populate_generic_pdata(struct device_node *np, 1383 struct mmci_platform_data *pdata) 1384{ 1385 int bus_width = 0; 1386 1387 pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1388 pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); 1389 1390 if (of_get_property(np, "cd-inverted", NULL)) 1391 pdata->cd_invert = true; 1392 else 1393 pdata->cd_invert = false; 1394 1395 of_property_read_u32(np, "max-frequency", &pdata->f_max); 1396 if (!pdata->f_max) 1397 pr_warn("%s has no 'max-frequency' property\n", np->full_name); 1398 1399 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1400 pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1401 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1402 pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; 1403 1404 of_property_read_u32(np, "bus-width", &bus_width); 1405 switch (bus_width) { 1406 case 0 : 1407 /* No bus-width supplied. */ 1408 break; 1409 case 4 : 1410 pdata->capabilities |= MMC_CAP_4_BIT_DATA; 1411 break; 1412 case 8 : 1413 pdata->capabilities |= MMC_CAP_8_BIT_DATA; 1414 break; 1415 default : 1416 pr_warn("%s: Unsupported bus width\n", np->full_name); 1417 } 1418} 1419#else 1420static void mmci_dt_populate_generic_pdata(struct device_node *np, 1421 struct mmci_platform_data *pdata) 1422{ 1423 return; 1424} 1425#endif 1426 1427static int mmci_probe(struct amba_device *dev, 1428 const struct amba_id *id) 1429{ 1430 struct mmci_platform_data *plat = dev->dev.platform_data; 1431 struct device_node *np = dev->dev.of_node; 1432 struct variant_data *variant = id->data; 1433 struct mmci_host *host; 1434 struct mmc_host *mmc; 1435 int ret; 1436 1437 /* Must have platform data or Device Tree. */ 1438 if (!plat && !np) { 1439 dev_err(&dev->dev, "No plat data or DT found\n"); 1440 return -EINVAL; 1441 } 1442 1443 if (!plat) { 1444 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1445 if (!plat) 1446 return -ENOMEM; 1447 } 1448 1449 if (np) 1450 mmci_dt_populate_generic_pdata(np, plat); 1451 1452 ret = amba_request_regions(dev, DRIVER_NAME); 1453 if (ret) 1454 goto out; 1455 1456 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1457 if (!mmc) { 1458 ret = -ENOMEM; 1459 goto rel_regions; 1460 } 1461 1462 host = mmc_priv(mmc); 1463 host->mmc = mmc; 1464 1465 host->gpio_wp = -ENOSYS; 1466 host->gpio_cd = -ENOSYS; 1467 host->gpio_cd_irq = -1; 1468 1469 host->hw_designer = amba_manf(dev); 1470 host->hw_revision = amba_rev(dev); 1471 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1472 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1473 1474 host->clk = devm_clk_get(&dev->dev, NULL); 1475 if (IS_ERR(host->clk)) { 1476 ret = PTR_ERR(host->clk); 1477 goto host_free; 1478 } 1479 1480 ret = clk_prepare_enable(host->clk); 1481 if (ret) 1482 goto host_free; 1483 1484 host->plat = plat; 1485 host->variant = variant; 1486 host->mclk = clk_get_rate(host->clk); 1487 /* 1488 * According to the spec, mclk is max 100 MHz, 1489 * so we try to adjust the clock down to this, 1490 * (if possible). 1491 */ 1492 if (host->mclk > 100000000) { 1493 ret = clk_set_rate(host->clk, 100000000); 1494 if (ret < 0) 1495 goto clk_disable; 1496 host->mclk = clk_get_rate(host->clk); 1497 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1498 host->mclk); 1499 } 1500 host->phybase = dev->res.start; 1501 host->base = ioremap(dev->res.start, resource_size(&dev->res)); 1502 if (!host->base) { 1503 ret = -ENOMEM; 1504 goto clk_disable; 1505 } 1506 1507 if (variant->busy_detect) { 1508 mmci_ops.card_busy = mmci_card_busy; 1509 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1510 } 1511 1512 mmc->ops = &mmci_ops; 1513 /* 1514 * The ARM and ST versions of the block have slightly different 1515 * clock divider equations which means that the minimum divider 1516 * differs too. 1517 */ 1518 if (variant->st_clkdiv) 1519 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1520 else 1521 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1522 /* 1523 * If the platform data supplies a maximum operating 1524 * frequency, this takes precedence. Else, we fall back 1525 * to using the module parameter, which has a (low) 1526 * default value in case it is not specified. Either 1527 * value must not exceed the clock rate into the block, 1528 * of course. 1529 */ 1530 if (plat->f_max) 1531 mmc->f_max = min(host->mclk, plat->f_max); 1532 else 1533 mmc->f_max = min(host->mclk, fmax); 1534 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1535 1536 /* Get regulators and the supported OCR mask */ 1537 mmc_regulator_get_supply(mmc); 1538 if (!mmc->ocr_avail) 1539 mmc->ocr_avail = plat->ocr_mask; 1540 else if (plat->ocr_mask) 1541 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1542 1543 mmc->caps = plat->capabilities; 1544 mmc->caps2 = plat->capabilities2; 1545 1546 /* We support these PM capabilities. */ 1547 mmc->pm_caps = MMC_PM_KEEP_POWER; 1548 1549 /* 1550 * We can do SGIO 1551 */ 1552 mmc->max_segs = NR_SG; 1553 1554 /* 1555 * Since only a certain number of bits are valid in the data length 1556 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1557 * single request. 1558 */ 1559 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1560 1561 /* 1562 * Set the maximum segment size. Since we aren't doing DMA 1563 * (yet) we are only limited by the data length register. 1564 */ 1565 mmc->max_seg_size = mmc->max_req_size; 1566 1567 /* 1568 * Block size can be up to 2048 bytes, but must be a power of two. 1569 */ 1570 mmc->max_blk_size = 1 << 11; 1571 1572 /* 1573 * Limit the number of blocks transferred so that we don't overflow 1574 * the maximum request size. 1575 */ 1576 mmc->max_blk_count = mmc->max_req_size >> 11; 1577 1578 spin_lock_init(&host->lock); 1579 1580 writel(0, host->base + MMCIMASK0); 1581 writel(0, host->base + MMCIMASK1); 1582 writel(0xfff, host->base + MMCICLEAR); 1583 1584 if (plat->gpio_cd == -EPROBE_DEFER) { 1585 ret = -EPROBE_DEFER; 1586 goto err_gpio_cd; 1587 } 1588 if (gpio_is_valid(plat->gpio_cd)) { 1589 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); 1590 if (ret == 0) 1591 ret = gpio_direction_input(plat->gpio_cd); 1592 if (ret == 0) 1593 host->gpio_cd = plat->gpio_cd; 1594 else if (ret != -ENOSYS) 1595 goto err_gpio_cd; 1596 1597 /* 1598 * A gpio pin that will detect cards when inserted and removed 1599 * will most likely want to trigger on the edges if it is 1600 * 0 when ejected and 1 when inserted (or mutatis mutandis 1601 * for the inverted case) so we request triggers on both 1602 * edges. 1603 */ 1604 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), 1605 mmci_cd_irq, 1606 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1607 DRIVER_NAME " (cd)", host); 1608 if (ret >= 0) 1609 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); 1610 } 1611 if (plat->gpio_wp == -EPROBE_DEFER) { 1612 ret = -EPROBE_DEFER; 1613 goto err_gpio_wp; 1614 } 1615 if (gpio_is_valid(plat->gpio_wp)) { 1616 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); 1617 if (ret == 0) 1618 ret = gpio_direction_input(plat->gpio_wp); 1619 if (ret == 0) 1620 host->gpio_wp = plat->gpio_wp; 1621 else if (ret != -ENOSYS) 1622 goto err_gpio_wp; 1623 } 1624 1625 if ((host->plat->status || host->gpio_cd != -ENOSYS) 1626 && host->gpio_cd_irq < 0) 1627 mmc->caps |= MMC_CAP_NEEDS_POLL; 1628 1629 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); 1630 if (ret) 1631 goto unmap; 1632 1633 if (!dev->irq[1]) 1634 host->singleirq = true; 1635 else { 1636 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, 1637 DRIVER_NAME " (pio)", host); 1638 if (ret) 1639 goto irq0_free; 1640 } 1641 1642 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1643 1644 amba_set_drvdata(dev, mmc); 1645 1646 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1647 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1648 amba_rev(dev), (unsigned long long)dev->res.start, 1649 dev->irq[0], dev->irq[1]); 1650 1651 mmci_dma_setup(host); 1652 1653 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1654 pm_runtime_use_autosuspend(&dev->dev); 1655 pm_runtime_put(&dev->dev); 1656 1657 mmc_add_host(mmc); 1658 1659 return 0; 1660 1661 irq0_free: 1662 free_irq(dev->irq[0], host); 1663 unmap: 1664 if (host->gpio_wp != -ENOSYS) 1665 gpio_free(host->gpio_wp); 1666 err_gpio_wp: 1667 if (host->gpio_cd_irq >= 0) 1668 free_irq(host->gpio_cd_irq, host); 1669 if (host->gpio_cd != -ENOSYS) 1670 gpio_free(host->gpio_cd); 1671 err_gpio_cd: 1672 iounmap(host->base); 1673 clk_disable: 1674 clk_disable_unprepare(host->clk); 1675 host_free: 1676 mmc_free_host(mmc); 1677 rel_regions: 1678 amba_release_regions(dev); 1679 out: 1680 return ret; 1681} 1682 1683static int mmci_remove(struct amba_device *dev) 1684{ 1685 struct mmc_host *mmc = amba_get_drvdata(dev); 1686 1687 if (mmc) { 1688 struct mmci_host *host = mmc_priv(mmc); 1689 1690 /* 1691 * Undo pm_runtime_put() in probe. We use the _sync 1692 * version here so that we can access the primecell. 1693 */ 1694 pm_runtime_get_sync(&dev->dev); 1695 1696 mmc_remove_host(mmc); 1697 1698 writel(0, host->base + MMCIMASK0); 1699 writel(0, host->base + MMCIMASK1); 1700 1701 writel(0, host->base + MMCICOMMAND); 1702 writel(0, host->base + MMCIDATACTRL); 1703 1704 mmci_dma_release(host); 1705 free_irq(dev->irq[0], host); 1706 if (!host->singleirq) 1707 free_irq(dev->irq[1], host); 1708 1709 if (host->gpio_wp != -ENOSYS) 1710 gpio_free(host->gpio_wp); 1711 if (host->gpio_cd_irq >= 0) 1712 free_irq(host->gpio_cd_irq, host); 1713 if (host->gpio_cd != -ENOSYS) 1714 gpio_free(host->gpio_cd); 1715 1716 iounmap(host->base); 1717 clk_disable_unprepare(host->clk); 1718 1719 mmc_free_host(mmc); 1720 1721 amba_release_regions(dev); 1722 } 1723 1724 return 0; 1725} 1726 1727#ifdef CONFIG_SUSPEND 1728static int mmci_suspend(struct device *dev) 1729{ 1730 struct amba_device *adev = to_amba_device(dev); 1731 struct mmc_host *mmc = amba_get_drvdata(adev); 1732 1733 if (mmc) { 1734 struct mmci_host *host = mmc_priv(mmc); 1735 pm_runtime_get_sync(dev); 1736 writel(0, host->base + MMCIMASK0); 1737 } 1738 1739 return 0; 1740} 1741 1742static int mmci_resume(struct device *dev) 1743{ 1744 struct amba_device *adev = to_amba_device(dev); 1745 struct mmc_host *mmc = amba_get_drvdata(adev); 1746 1747 if (mmc) { 1748 struct mmci_host *host = mmc_priv(mmc); 1749 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1750 pm_runtime_put(dev); 1751 } 1752 1753 return 0; 1754} 1755#endif 1756 1757#ifdef CONFIG_PM_RUNTIME 1758static void mmci_save(struct mmci_host *host) 1759{ 1760 unsigned long flags; 1761 1762 if (host->variant->pwrreg_nopower) { 1763 spin_lock_irqsave(&host->lock, flags); 1764 1765 writel(0, host->base + MMCIMASK0); 1766 writel(0, host->base + MMCIDATACTRL); 1767 writel(0, host->base + MMCIPOWER); 1768 writel(0, host->base + MMCICLOCK); 1769 mmci_reg_delay(host); 1770 1771 spin_unlock_irqrestore(&host->lock, flags); 1772 } 1773 1774} 1775 1776static void mmci_restore(struct mmci_host *host) 1777{ 1778 unsigned long flags; 1779 1780 if (host->variant->pwrreg_nopower) { 1781 spin_lock_irqsave(&host->lock, flags); 1782 1783 writel(host->clk_reg, host->base + MMCICLOCK); 1784 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1785 writel(host->pwr_reg, host->base + MMCIPOWER); 1786 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1787 mmci_reg_delay(host); 1788 1789 spin_unlock_irqrestore(&host->lock, flags); 1790 } 1791} 1792 1793static int mmci_runtime_suspend(struct device *dev) 1794{ 1795 struct amba_device *adev = to_amba_device(dev); 1796 struct mmc_host *mmc = amba_get_drvdata(adev); 1797 1798 if (mmc) { 1799 struct mmci_host *host = mmc_priv(mmc); 1800 pinctrl_pm_select_sleep_state(dev); 1801 mmci_save(host); 1802 clk_disable_unprepare(host->clk); 1803 } 1804 1805 return 0; 1806} 1807 1808static int mmci_runtime_resume(struct device *dev) 1809{ 1810 struct amba_device *adev = to_amba_device(dev); 1811 struct mmc_host *mmc = amba_get_drvdata(adev); 1812 1813 if (mmc) { 1814 struct mmci_host *host = mmc_priv(mmc); 1815 clk_prepare_enable(host->clk); 1816 mmci_restore(host); 1817 pinctrl_pm_select_default_state(dev); 1818 } 1819 1820 return 0; 1821} 1822#endif 1823 1824static const struct dev_pm_ops mmci_dev_pm_ops = { 1825 SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) 1826 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1827}; 1828 1829static struct amba_id mmci_ids[] = { 1830 { 1831 .id = 0x00041180, 1832 .mask = 0xff0fffff, 1833 .data = &variant_arm, 1834 }, 1835 { 1836 .id = 0x01041180, 1837 .mask = 0xff0fffff, 1838 .data = &variant_arm_extended_fifo, 1839 }, 1840 { 1841 .id = 0x02041180, 1842 .mask = 0xff0fffff, 1843 .data = &variant_arm_extended_fifo_hwfc, 1844 }, 1845 { 1846 .id = 0x00041181, 1847 .mask = 0x000fffff, 1848 .data = &variant_arm, 1849 }, 1850 /* ST Micro variants */ 1851 { 1852 .id = 0x00180180, 1853 .mask = 0x00ffffff, 1854 .data = &variant_u300, 1855 }, 1856 { 1857 .id = 0x10180180, 1858 .mask = 0xf0ffffff, 1859 .data = &variant_nomadik, 1860 }, 1861 { 1862 .id = 0x00280180, 1863 .mask = 0x00ffffff, 1864 .data = &variant_u300, 1865 }, 1866 { 1867 .id = 0x00480180, 1868 .mask = 0xf0ffffff, 1869 .data = &variant_ux500, 1870 }, 1871 { 1872 .id = 0x10480180, 1873 .mask = 0xf0ffffff, 1874 .data = &variant_ux500v2, 1875 }, 1876 { 0, 0 }, 1877}; 1878 1879MODULE_DEVICE_TABLE(amba, mmci_ids); 1880 1881static struct amba_driver mmci_driver = { 1882 .drv = { 1883 .name = DRIVER_NAME, 1884 .pm = &mmci_dev_pm_ops, 1885 }, 1886 .probe = mmci_probe, 1887 .remove = mmci_remove, 1888 .id_table = mmci_ids, 1889}; 1890 1891module_amba_driver(mmci_driver); 1892 1893module_param(fmax, uint, 0444); 1894 1895MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1896MODULE_LICENSE("GPL"); 1897