mmci.c revision ff783233cc13eca99a3b59c0609c1ffc6164b7a2
1/* 2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver 3 * 4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5 * Copyright (C) 2010 ST-Ericsson SA 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/moduleparam.h> 13#include <linux/init.h> 14#include <linux/ioport.h> 15#include <linux/device.h> 16#include <linux/io.h> 17#include <linux/interrupt.h> 18#include <linux/kernel.h> 19#include <linux/slab.h> 20#include <linux/delay.h> 21#include <linux/err.h> 22#include <linux/highmem.h> 23#include <linux/log2.h> 24#include <linux/mmc/pm.h> 25#include <linux/mmc/host.h> 26#include <linux/mmc/card.h> 27#include <linux/mmc/slot-gpio.h> 28#include <linux/amba/bus.h> 29#include <linux/clk.h> 30#include <linux/scatterlist.h> 31#include <linux/gpio.h> 32#include <linux/of_gpio.h> 33#include <linux/regulator/consumer.h> 34#include <linux/dmaengine.h> 35#include <linux/dma-mapping.h> 36#include <linux/amba/mmci.h> 37#include <linux/pm_runtime.h> 38#include <linux/types.h> 39#include <linux/pinctrl/consumer.h> 40 41#include <asm/div64.h> 42#include <asm/io.h> 43#include <asm/sizes.h> 44 45#include "mmci.h" 46 47#define DRIVER_NAME "mmci-pl18x" 48 49static unsigned int fmax = 515633; 50 51/** 52 * struct variant_data - MMCI variant-specific quirks 53 * @clkreg: default value for MCICLOCK register 54 * @clkreg_enable: enable value for MMCICLOCK register 55 * @datalength_bits: number of bits in the MMCIDATALENGTH register 56 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY 57 * is asserted (likewise for RX) 58 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY 59 * is asserted (likewise for RX) 60 * @sdio: variant supports SDIO 61 * @st_clkdiv: true if using a ST-specific clock divider algorithm 62 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register 63 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl 64 * register 65 * @pwrreg_powerup: power up value for MMCIPOWER register 66 * @signal_direction: input/out direction of bus signals can be indicated 67 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock 68 * @busy_detect: true if busy detection on dat0 is supported 69 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply 70 */ 71struct variant_data { 72 unsigned int clkreg; 73 unsigned int clkreg_enable; 74 unsigned int datalength_bits; 75 unsigned int fifosize; 76 unsigned int fifohalfsize; 77 bool sdio; 78 bool st_clkdiv; 79 bool blksz_datactrl16; 80 bool blksz_datactrl4; 81 u32 pwrreg_powerup; 82 bool signal_direction; 83 bool pwrreg_clkgate; 84 bool busy_detect; 85 bool pwrreg_nopower; 86}; 87 88static struct variant_data variant_arm = { 89 .fifosize = 16 * 4, 90 .fifohalfsize = 8 * 4, 91 .datalength_bits = 16, 92 .pwrreg_powerup = MCI_PWR_UP, 93}; 94 95static struct variant_data variant_arm_extended_fifo = { 96 .fifosize = 128 * 4, 97 .fifohalfsize = 64 * 4, 98 .datalength_bits = 16, 99 .pwrreg_powerup = MCI_PWR_UP, 100}; 101 102static struct variant_data variant_arm_extended_fifo_hwfc = { 103 .fifosize = 128 * 4, 104 .fifohalfsize = 64 * 4, 105 .clkreg_enable = MCI_ARM_HWFCEN, 106 .datalength_bits = 16, 107 .pwrreg_powerup = MCI_PWR_UP, 108}; 109 110static struct variant_data variant_u300 = { 111 .fifosize = 16 * 4, 112 .fifohalfsize = 8 * 4, 113 .clkreg_enable = MCI_ST_U300_HWFCEN, 114 .datalength_bits = 16, 115 .sdio = true, 116 .pwrreg_powerup = MCI_PWR_ON, 117 .signal_direction = true, 118 .pwrreg_clkgate = true, 119 .pwrreg_nopower = true, 120}; 121 122static struct variant_data variant_nomadik = { 123 .fifosize = 16 * 4, 124 .fifohalfsize = 8 * 4, 125 .clkreg = MCI_CLK_ENABLE, 126 .datalength_bits = 24, 127 .sdio = true, 128 .st_clkdiv = true, 129 .pwrreg_powerup = MCI_PWR_ON, 130 .signal_direction = true, 131 .pwrreg_clkgate = true, 132 .pwrreg_nopower = true, 133}; 134 135static struct variant_data variant_ux500 = { 136 .fifosize = 30 * 4, 137 .fifohalfsize = 8 * 4, 138 .clkreg = MCI_CLK_ENABLE, 139 .clkreg_enable = MCI_ST_UX500_HWFCEN, 140 .datalength_bits = 24, 141 .sdio = true, 142 .st_clkdiv = true, 143 .pwrreg_powerup = MCI_PWR_ON, 144 .signal_direction = true, 145 .pwrreg_clkgate = true, 146 .busy_detect = true, 147 .pwrreg_nopower = true, 148}; 149 150static struct variant_data variant_ux500v2 = { 151 .fifosize = 30 * 4, 152 .fifohalfsize = 8 * 4, 153 .clkreg = MCI_CLK_ENABLE, 154 .clkreg_enable = MCI_ST_UX500_HWFCEN, 155 .datalength_bits = 24, 156 .sdio = true, 157 .st_clkdiv = true, 158 .blksz_datactrl16 = true, 159 .pwrreg_powerup = MCI_PWR_ON, 160 .signal_direction = true, 161 .pwrreg_clkgate = true, 162 .busy_detect = true, 163 .pwrreg_nopower = true, 164}; 165 166static int mmci_card_busy(struct mmc_host *mmc) 167{ 168 struct mmci_host *host = mmc_priv(mmc); 169 unsigned long flags; 170 int busy = 0; 171 172 pm_runtime_get_sync(mmc_dev(mmc)); 173 174 spin_lock_irqsave(&host->lock, flags); 175 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY) 176 busy = 1; 177 spin_unlock_irqrestore(&host->lock, flags); 178 179 pm_runtime_mark_last_busy(mmc_dev(mmc)); 180 pm_runtime_put_autosuspend(mmc_dev(mmc)); 181 182 return busy; 183} 184 185/* 186 * Validate mmc prerequisites 187 */ 188static int mmci_validate_data(struct mmci_host *host, 189 struct mmc_data *data) 190{ 191 if (!data) 192 return 0; 193 194 if (!is_power_of_2(data->blksz)) { 195 dev_err(mmc_dev(host->mmc), 196 "unsupported block size (%d bytes)\n", data->blksz); 197 return -EINVAL; 198 } 199 200 return 0; 201} 202 203static void mmci_reg_delay(struct mmci_host *host) 204{ 205 /* 206 * According to the spec, at least three feedback clock cycles 207 * of max 52 MHz must pass between two writes to the MMCICLOCK reg. 208 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. 209 * Worst delay time during card init is at 100 kHz => 30 us. 210 * Worst delay time when up and running is at 25 MHz => 120 ns. 211 */ 212 if (host->cclk < 25000000) 213 udelay(30); 214 else 215 ndelay(120); 216} 217 218/* 219 * This must be called with host->lock held 220 */ 221static void mmci_write_clkreg(struct mmci_host *host, u32 clk) 222{ 223 if (host->clk_reg != clk) { 224 host->clk_reg = clk; 225 writel(clk, host->base + MMCICLOCK); 226 } 227} 228 229/* 230 * This must be called with host->lock held 231 */ 232static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) 233{ 234 if (host->pwr_reg != pwr) { 235 host->pwr_reg = pwr; 236 writel(pwr, host->base + MMCIPOWER); 237 } 238} 239 240/* 241 * This must be called with host->lock held 242 */ 243static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) 244{ 245 /* Keep ST Micro busy mode if enabled */ 246 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE; 247 248 if (host->datactrl_reg != datactrl) { 249 host->datactrl_reg = datactrl; 250 writel(datactrl, host->base + MMCIDATACTRL); 251 } 252} 253 254/* 255 * This must be called with host->lock held 256 */ 257static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) 258{ 259 struct variant_data *variant = host->variant; 260 u32 clk = variant->clkreg; 261 262 /* Make sure cclk reflects the current calculated clock */ 263 host->cclk = 0; 264 265 if (desired) { 266 if (desired >= host->mclk) { 267 clk = MCI_CLK_BYPASS; 268 if (variant->st_clkdiv) 269 clk |= MCI_ST_UX500_NEG_EDGE; 270 host->cclk = host->mclk; 271 } else if (variant->st_clkdiv) { 272 /* 273 * DB8500 TRM says f = mclk / (clkdiv + 2) 274 * => clkdiv = (mclk / f) - 2 275 * Round the divider up so we don't exceed the max 276 * frequency 277 */ 278 clk = DIV_ROUND_UP(host->mclk, desired) - 2; 279 if (clk >= 256) 280 clk = 255; 281 host->cclk = host->mclk / (clk + 2); 282 } else { 283 /* 284 * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) 285 * => clkdiv = mclk / (2 * f) - 1 286 */ 287 clk = host->mclk / (2 * desired) - 1; 288 if (clk >= 256) 289 clk = 255; 290 host->cclk = host->mclk / (2 * (clk + 1)); 291 } 292 293 clk |= variant->clkreg_enable; 294 clk |= MCI_CLK_ENABLE; 295 /* This hasn't proven to be worthwhile */ 296 /* clk |= MCI_CLK_PWRSAVE; */ 297 } 298 299 /* Set actual clock for debug */ 300 host->mmc->actual_clock = host->cclk; 301 302 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) 303 clk |= MCI_4BIT_BUS; 304 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) 305 clk |= MCI_ST_8BIT_BUS; 306 307 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 308 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 309 clk |= MCI_ST_UX500_NEG_EDGE; 310 311 mmci_write_clkreg(host, clk); 312} 313 314static void 315mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) 316{ 317 writel(0, host->base + MMCICOMMAND); 318 319 BUG_ON(host->data); 320 321 host->mrq = NULL; 322 host->cmd = NULL; 323 324 mmc_request_done(host->mmc, mrq); 325 326 pm_runtime_mark_last_busy(mmc_dev(host->mmc)); 327 pm_runtime_put_autosuspend(mmc_dev(host->mmc)); 328} 329 330static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) 331{ 332 void __iomem *base = host->base; 333 334 if (host->singleirq) { 335 unsigned int mask0 = readl(base + MMCIMASK0); 336 337 mask0 &= ~MCI_IRQ1MASK; 338 mask0 |= mask; 339 340 writel(mask0, base + MMCIMASK0); 341 } 342 343 writel(mask, base + MMCIMASK1); 344} 345 346static void mmci_stop_data(struct mmci_host *host) 347{ 348 mmci_write_datactrlreg(host, 0); 349 mmci_set_mask1(host, 0); 350 host->data = NULL; 351} 352 353static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) 354{ 355 unsigned int flags = SG_MITER_ATOMIC; 356 357 if (data->flags & MMC_DATA_READ) 358 flags |= SG_MITER_TO_SG; 359 else 360 flags |= SG_MITER_FROM_SG; 361 362 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 363} 364 365/* 366 * All the DMA operation mode stuff goes inside this ifdef. 367 * This assumes that you have a generic DMA device interface, 368 * no custom DMA interfaces are supported. 369 */ 370#ifdef CONFIG_DMA_ENGINE 371static void mmci_dma_setup(struct mmci_host *host) 372{ 373 const char *rxname, *txname; 374 dma_cap_mask_t mask; 375 376 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx"); 377 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx"); 378 379 /* initialize pre request cookie */ 380 host->next_data.cookie = 1; 381 382 /* Try to acquire a generic DMA engine slave channel */ 383 dma_cap_zero(mask); 384 dma_cap_set(DMA_SLAVE, mask); 385 386 /* 387 * If only an RX channel is specified, the driver will 388 * attempt to use it bidirectionally, however if it is 389 * is specified but cannot be located, DMA will be disabled. 390 */ 391 if (host->dma_rx_channel && !host->dma_tx_channel) 392 host->dma_tx_channel = host->dma_rx_channel; 393 394 if (host->dma_rx_channel) 395 rxname = dma_chan_name(host->dma_rx_channel); 396 else 397 rxname = "none"; 398 399 if (host->dma_tx_channel) 400 txname = dma_chan_name(host->dma_tx_channel); 401 else 402 txname = "none"; 403 404 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", 405 rxname, txname); 406 407 /* 408 * Limit the maximum segment size in any SG entry according to 409 * the parameters of the DMA engine device. 410 */ 411 if (host->dma_tx_channel) { 412 struct device *dev = host->dma_tx_channel->device->dev; 413 unsigned int max_seg_size = dma_get_max_seg_size(dev); 414 415 if (max_seg_size < host->mmc->max_seg_size) 416 host->mmc->max_seg_size = max_seg_size; 417 } 418 if (host->dma_rx_channel) { 419 struct device *dev = host->dma_rx_channel->device->dev; 420 unsigned int max_seg_size = dma_get_max_seg_size(dev); 421 422 if (max_seg_size < host->mmc->max_seg_size) 423 host->mmc->max_seg_size = max_seg_size; 424 } 425} 426 427/* 428 * This is used in or so inline it 429 * so it can be discarded. 430 */ 431static inline void mmci_dma_release(struct mmci_host *host) 432{ 433 if (host->dma_rx_channel) 434 dma_release_channel(host->dma_rx_channel); 435 if (host->dma_tx_channel) 436 dma_release_channel(host->dma_tx_channel); 437 host->dma_rx_channel = host->dma_tx_channel = NULL; 438} 439 440static void mmci_dma_data_error(struct mmci_host *host) 441{ 442 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); 443 dmaengine_terminate_all(host->dma_current); 444 host->dma_current = NULL; 445 host->dma_desc_current = NULL; 446 host->data->host_cookie = 0; 447} 448 449static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 450{ 451 struct dma_chan *chan; 452 enum dma_data_direction dir; 453 454 if (data->flags & MMC_DATA_READ) { 455 dir = DMA_FROM_DEVICE; 456 chan = host->dma_rx_channel; 457 } else { 458 dir = DMA_TO_DEVICE; 459 chan = host->dma_tx_channel; 460 } 461 462 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); 463} 464 465static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) 466{ 467 u32 status; 468 int i; 469 470 /* Wait up to 1ms for the DMA to complete */ 471 for (i = 0; ; i++) { 472 status = readl(host->base + MMCISTATUS); 473 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) 474 break; 475 udelay(10); 476 } 477 478 /* 479 * Check to see whether we still have some data left in the FIFO - 480 * this catches DMA controllers which are unable to monitor the 481 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- 482 * contiguous buffers. On TX, we'll get a FIFO underrun error. 483 */ 484 if (status & MCI_RXDATAAVLBLMASK) { 485 mmci_dma_data_error(host); 486 if (!data->error) 487 data->error = -EIO; 488 } 489 490 if (!data->host_cookie) 491 mmci_dma_unmap(host, data); 492 493 /* 494 * Use of DMA with scatter-gather is impossible. 495 * Give up with DMA and switch back to PIO mode. 496 */ 497 if (status & MCI_RXDATAAVLBLMASK) { 498 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); 499 mmci_dma_release(host); 500 } 501 502 host->dma_current = NULL; 503 host->dma_desc_current = NULL; 504} 505 506/* prepares DMA channel and DMA descriptor, returns non-zero on failure */ 507static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, 508 struct dma_chan **dma_chan, 509 struct dma_async_tx_descriptor **dma_desc) 510{ 511 struct variant_data *variant = host->variant; 512 struct dma_slave_config conf = { 513 .src_addr = host->phybase + MMCIFIFO, 514 .dst_addr = host->phybase + MMCIFIFO, 515 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 516 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 517 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ 518 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ 519 .device_fc = false, 520 }; 521 struct dma_chan *chan; 522 struct dma_device *device; 523 struct dma_async_tx_descriptor *desc; 524 enum dma_data_direction buffer_dirn; 525 int nr_sg; 526 527 if (data->flags & MMC_DATA_READ) { 528 conf.direction = DMA_DEV_TO_MEM; 529 buffer_dirn = DMA_FROM_DEVICE; 530 chan = host->dma_rx_channel; 531 } else { 532 conf.direction = DMA_MEM_TO_DEV; 533 buffer_dirn = DMA_TO_DEVICE; 534 chan = host->dma_tx_channel; 535 } 536 537 /* If there's no DMA channel, fall back to PIO */ 538 if (!chan) 539 return -EINVAL; 540 541 /* If less than or equal to the fifo size, don't bother with DMA */ 542 if (data->blksz * data->blocks <= variant->fifosize) 543 return -EINVAL; 544 545 device = chan->device; 546 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 547 if (nr_sg == 0) 548 return -EINVAL; 549 550 dmaengine_slave_config(chan, &conf); 551 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, 552 conf.direction, DMA_CTRL_ACK); 553 if (!desc) 554 goto unmap_exit; 555 556 *dma_chan = chan; 557 *dma_desc = desc; 558 559 return 0; 560 561 unmap_exit: 562 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); 563 return -ENOMEM; 564} 565 566static inline int mmci_dma_prep_data(struct mmci_host *host, 567 struct mmc_data *data) 568{ 569 /* Check if next job is already prepared. */ 570 if (host->dma_current && host->dma_desc_current) 571 return 0; 572 573 /* No job were prepared thus do it now. */ 574 return __mmci_dma_prep_data(host, data, &host->dma_current, 575 &host->dma_desc_current); 576} 577 578static inline int mmci_dma_prep_next(struct mmci_host *host, 579 struct mmc_data *data) 580{ 581 struct mmci_host_next *nd = &host->next_data; 582 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc); 583} 584 585static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 586{ 587 int ret; 588 struct mmc_data *data = host->data; 589 590 ret = mmci_dma_prep_data(host, host->data); 591 if (ret) 592 return ret; 593 594 /* Okay, go for it. */ 595 dev_vdbg(mmc_dev(host->mmc), 596 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", 597 data->sg_len, data->blksz, data->blocks, data->flags); 598 dmaengine_submit(host->dma_desc_current); 599 dma_async_issue_pending(host->dma_current); 600 601 datactrl |= MCI_DPSM_DMAENABLE; 602 603 /* Trigger the DMA transfer */ 604 mmci_write_datactrlreg(host, datactrl); 605 606 /* 607 * Let the MMCI say when the data is ended and it's time 608 * to fire next DMA request. When that happens, MMCI will 609 * call mmci_data_end() 610 */ 611 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, 612 host->base + MMCIMASK0); 613 return 0; 614} 615 616static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 617{ 618 struct mmci_host_next *next = &host->next_data; 619 620 WARN_ON(data->host_cookie && data->host_cookie != next->cookie); 621 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan)); 622 623 host->dma_desc_current = next->dma_desc; 624 host->dma_current = next->dma_chan; 625 next->dma_desc = NULL; 626 next->dma_chan = NULL; 627} 628 629static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, 630 bool is_first_req) 631{ 632 struct mmci_host *host = mmc_priv(mmc); 633 struct mmc_data *data = mrq->data; 634 struct mmci_host_next *nd = &host->next_data; 635 636 if (!data) 637 return; 638 639 BUG_ON(data->host_cookie); 640 641 if (mmci_validate_data(host, data)) 642 return; 643 644 if (!mmci_dma_prep_next(host, data)) 645 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; 646} 647 648static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, 649 int err) 650{ 651 struct mmci_host *host = mmc_priv(mmc); 652 struct mmc_data *data = mrq->data; 653 654 if (!data || !data->host_cookie) 655 return; 656 657 mmci_dma_unmap(host, data); 658 659 if (err) { 660 struct mmci_host_next *next = &host->next_data; 661 struct dma_chan *chan; 662 if (data->flags & MMC_DATA_READ) 663 chan = host->dma_rx_channel; 664 else 665 chan = host->dma_tx_channel; 666 dmaengine_terminate_all(chan); 667 668 next->dma_desc = NULL; 669 next->dma_chan = NULL; 670 } 671} 672 673#else 674/* Blank functions if the DMA engine is not available */ 675static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) 676{ 677} 678static inline void mmci_dma_setup(struct mmci_host *host) 679{ 680} 681 682static inline void mmci_dma_release(struct mmci_host *host) 683{ 684} 685 686static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) 687{ 688} 689 690static inline void mmci_dma_finalize(struct mmci_host *host, 691 struct mmc_data *data) 692{ 693} 694 695static inline void mmci_dma_data_error(struct mmci_host *host) 696{ 697} 698 699static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) 700{ 701 return -ENOSYS; 702} 703 704#define mmci_pre_request NULL 705#define mmci_post_request NULL 706 707#endif 708 709static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) 710{ 711 struct variant_data *variant = host->variant; 712 unsigned int datactrl, timeout, irqmask; 713 unsigned long long clks; 714 void __iomem *base; 715 int blksz_bits; 716 717 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", 718 data->blksz, data->blocks, data->flags); 719 720 host->data = data; 721 host->size = data->blksz * data->blocks; 722 data->bytes_xfered = 0; 723 724 clks = (unsigned long long)data->timeout_ns * host->cclk; 725 do_div(clks, NSEC_PER_SEC); 726 727 timeout = data->timeout_clks + (unsigned int)clks; 728 729 base = host->base; 730 writel(timeout, base + MMCIDATATIMER); 731 writel(host->size, base + MMCIDATALENGTH); 732 733 blksz_bits = ffs(data->blksz) - 1; 734 BUG_ON(1 << blksz_bits != data->blksz); 735 736 if (variant->blksz_datactrl16) 737 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); 738 else if (variant->blksz_datactrl4) 739 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); 740 else 741 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; 742 743 if (data->flags & MMC_DATA_READ) 744 datactrl |= MCI_DPSM_DIRECTION; 745 746 /* The ST Micro variants has a special bit to enable SDIO */ 747 if (variant->sdio && host->mmc->card) 748 if (mmc_card_sdio(host->mmc->card)) { 749 /* 750 * The ST Micro variants has a special bit 751 * to enable SDIO. 752 */ 753 u32 clk; 754 755 datactrl |= MCI_ST_DPSM_SDIOEN; 756 757 /* 758 * The ST Micro variant for SDIO small write transfers 759 * needs to have clock H/W flow control disabled, 760 * otherwise the transfer will not start. The threshold 761 * depends on the rate of MCLK. 762 */ 763 if (data->flags & MMC_DATA_WRITE && 764 (host->size < 8 || 765 (host->size <= 8 && host->mclk > 50000000))) 766 clk = host->clk_reg & ~variant->clkreg_enable; 767 else 768 clk = host->clk_reg | variant->clkreg_enable; 769 770 mmci_write_clkreg(host, clk); 771 } 772 773 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || 774 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) 775 datactrl |= MCI_ST_DPSM_DDRMODE; 776 777 /* 778 * Attempt to use DMA operation mode, if this 779 * should fail, fall back to PIO mode 780 */ 781 if (!mmci_dma_start_data(host, datactrl)) 782 return; 783 784 /* IRQ mode, map the SG list for CPU reading/writing */ 785 mmci_init_sg(host, data); 786 787 if (data->flags & MMC_DATA_READ) { 788 irqmask = MCI_RXFIFOHALFFULLMASK; 789 790 /* 791 * If we have less than the fifo 'half-full' threshold to 792 * transfer, trigger a PIO interrupt as soon as any data 793 * is available. 794 */ 795 if (host->size < variant->fifohalfsize) 796 irqmask |= MCI_RXDATAAVLBLMASK; 797 } else { 798 /* 799 * We don't actually need to include "FIFO empty" here 800 * since its implicit in "FIFO half empty". 801 */ 802 irqmask = MCI_TXFIFOHALFEMPTYMASK; 803 } 804 805 mmci_write_datactrlreg(host, datactrl); 806 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); 807 mmci_set_mask1(host, irqmask); 808} 809 810static void 811mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) 812{ 813 void __iomem *base = host->base; 814 815 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", 816 cmd->opcode, cmd->arg, cmd->flags); 817 818 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { 819 writel(0, base + MMCICOMMAND); 820 mmci_reg_delay(host); 821 } 822 823 c |= cmd->opcode | MCI_CPSM_ENABLE; 824 if (cmd->flags & MMC_RSP_PRESENT) { 825 if (cmd->flags & MMC_RSP_136) 826 c |= MCI_CPSM_LONGRSP; 827 c |= MCI_CPSM_RESPONSE; 828 } 829 if (/*interrupt*/0) 830 c |= MCI_CPSM_INTERRUPT; 831 832 host->cmd = cmd; 833 834 writel(cmd->arg, base + MMCIARGUMENT); 835 writel(c, base + MMCICOMMAND); 836} 837 838static void 839mmci_data_irq(struct mmci_host *host, struct mmc_data *data, 840 unsigned int status) 841{ 842 /* First check for errors */ 843 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 844 MCI_TXUNDERRUN|MCI_RXOVERRUN)) { 845 u32 remain, success; 846 847 /* Terminate the DMA transfer */ 848 if (dma_inprogress(host)) { 849 mmci_dma_data_error(host); 850 mmci_dma_unmap(host, data); 851 } 852 853 /* 854 * Calculate how far we are into the transfer. Note that 855 * the data counter gives the number of bytes transferred 856 * on the MMC bus, not on the host side. On reads, this 857 * can be as much as a FIFO-worth of data ahead. This 858 * matters for FIFO overruns only. 859 */ 860 remain = readl(host->base + MMCIDATACNT); 861 success = data->blksz * data->blocks - remain; 862 863 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", 864 status, success); 865 if (status & MCI_DATACRCFAIL) { 866 /* Last block was not successful */ 867 success -= 1; 868 data->error = -EILSEQ; 869 } else if (status & MCI_DATATIMEOUT) { 870 data->error = -ETIMEDOUT; 871 } else if (status & MCI_STARTBITERR) { 872 data->error = -ECOMM; 873 } else if (status & MCI_TXUNDERRUN) { 874 data->error = -EIO; 875 } else if (status & MCI_RXOVERRUN) { 876 if (success > host->variant->fifosize) 877 success -= host->variant->fifosize; 878 else 879 success = 0; 880 data->error = -EIO; 881 } 882 data->bytes_xfered = round_down(success, data->blksz); 883 } 884 885 if (status & MCI_DATABLOCKEND) 886 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); 887 888 if (status & MCI_DATAEND || data->error) { 889 if (dma_inprogress(host)) 890 mmci_dma_finalize(host, data); 891 mmci_stop_data(host); 892 893 if (!data->error) 894 /* The error clause is handled above, success! */ 895 data->bytes_xfered = data->blksz * data->blocks; 896 897 if (!data->stop || host->mrq->sbc) { 898 mmci_request_end(host, data->mrq); 899 } else { 900 mmci_start_command(host, data->stop, 0); 901 } 902 } 903} 904 905static void 906mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, 907 unsigned int status) 908{ 909 void __iomem *base = host->base; 910 bool sbc = (cmd == host->mrq->sbc); 911 bool busy_resp = host->variant->busy_detect && 912 (cmd->flags & MMC_RSP_BUSY); 913 914 /* Check if we need to wait for busy completion. */ 915 if (host->busy_status && (status & MCI_ST_CARDBUSY)) 916 return; 917 918 /* Enable busy completion if needed and supported. */ 919 if (!host->busy_status && busy_resp && 920 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && 921 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) { 922 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND, 923 base + MMCIMASK0); 924 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND); 925 return; 926 } 927 928 /* At busy completion, mask the IRQ and complete the request. */ 929 if (host->busy_status) { 930 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND, 931 base + MMCIMASK0); 932 host->busy_status = 0; 933 } 934 935 host->cmd = NULL; 936 937 if (status & MCI_CMDTIMEOUT) { 938 cmd->error = -ETIMEDOUT; 939 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { 940 cmd->error = -EILSEQ; 941 } else { 942 cmd->resp[0] = readl(base + MMCIRESPONSE0); 943 cmd->resp[1] = readl(base + MMCIRESPONSE1); 944 cmd->resp[2] = readl(base + MMCIRESPONSE2); 945 cmd->resp[3] = readl(base + MMCIRESPONSE3); 946 } 947 948 if ((!sbc && !cmd->data) || cmd->error) { 949 if (host->data) { 950 /* Terminate the DMA transfer */ 951 if (dma_inprogress(host)) { 952 mmci_dma_data_error(host); 953 mmci_dma_unmap(host, host->data); 954 } 955 mmci_stop_data(host); 956 } 957 mmci_request_end(host, host->mrq); 958 } else if (sbc) { 959 mmci_start_command(host, host->mrq->cmd, 0); 960 } else if (!(cmd->data->flags & MMC_DATA_READ)) { 961 mmci_start_data(host, cmd->data); 962 } 963} 964 965static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) 966{ 967 void __iomem *base = host->base; 968 char *ptr = buffer; 969 u32 status; 970 int host_remain = host->size; 971 972 do { 973 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); 974 975 if (count > remain) 976 count = remain; 977 978 if (count <= 0) 979 break; 980 981 /* 982 * SDIO especially may want to send something that is 983 * not divisible by 4 (as opposed to card sectors 984 * etc). Therefore make sure to always read the last bytes 985 * while only doing full 32-bit reads towards the FIFO. 986 */ 987 if (unlikely(count & 0x3)) { 988 if (count < 4) { 989 unsigned char buf[4]; 990 ioread32_rep(base + MMCIFIFO, buf, 1); 991 memcpy(ptr, buf, count); 992 } else { 993 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 994 count &= ~0x3; 995 } 996 } else { 997 ioread32_rep(base + MMCIFIFO, ptr, count >> 2); 998 } 999 1000 ptr += count; 1001 remain -= count; 1002 host_remain -= count; 1003 1004 if (remain == 0) 1005 break; 1006 1007 status = readl(base + MMCISTATUS); 1008 } while (status & MCI_RXDATAAVLBL); 1009 1010 return ptr - buffer; 1011} 1012 1013static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) 1014{ 1015 struct variant_data *variant = host->variant; 1016 void __iomem *base = host->base; 1017 char *ptr = buffer; 1018 1019 do { 1020 unsigned int count, maxcnt; 1021 1022 maxcnt = status & MCI_TXFIFOEMPTY ? 1023 variant->fifosize : variant->fifohalfsize; 1024 count = min(remain, maxcnt); 1025 1026 /* 1027 * SDIO especially may want to send something that is 1028 * not divisible by 4 (as opposed to card sectors 1029 * etc), and the FIFO only accept full 32-bit writes. 1030 * So compensate by adding +3 on the count, a single 1031 * byte become a 32bit write, 7 bytes will be two 1032 * 32bit writes etc. 1033 */ 1034 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); 1035 1036 ptr += count; 1037 remain -= count; 1038 1039 if (remain == 0) 1040 break; 1041 1042 status = readl(base + MMCISTATUS); 1043 } while (status & MCI_TXFIFOHALFEMPTY); 1044 1045 return ptr - buffer; 1046} 1047 1048/* 1049 * PIO data transfer IRQ handler. 1050 */ 1051static irqreturn_t mmci_pio_irq(int irq, void *dev_id) 1052{ 1053 struct mmci_host *host = dev_id; 1054 struct sg_mapping_iter *sg_miter = &host->sg_miter; 1055 struct variant_data *variant = host->variant; 1056 void __iomem *base = host->base; 1057 unsigned long flags; 1058 u32 status; 1059 1060 status = readl(base + MMCISTATUS); 1061 1062 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); 1063 1064 local_irq_save(flags); 1065 1066 do { 1067 unsigned int remain, len; 1068 char *buffer; 1069 1070 /* 1071 * For write, we only need to test the half-empty flag 1072 * here - if the FIFO is completely empty, then by 1073 * definition it is more than half empty. 1074 * 1075 * For read, check for data available. 1076 */ 1077 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) 1078 break; 1079 1080 if (!sg_miter_next(sg_miter)) 1081 break; 1082 1083 buffer = sg_miter->addr; 1084 remain = sg_miter->length; 1085 1086 len = 0; 1087 if (status & MCI_RXACTIVE) 1088 len = mmci_pio_read(host, buffer, remain); 1089 if (status & MCI_TXACTIVE) 1090 len = mmci_pio_write(host, buffer, remain, status); 1091 1092 sg_miter->consumed = len; 1093 1094 host->size -= len; 1095 remain -= len; 1096 1097 if (remain) 1098 break; 1099 1100 status = readl(base + MMCISTATUS); 1101 } while (1); 1102 1103 sg_miter_stop(sg_miter); 1104 1105 local_irq_restore(flags); 1106 1107 /* 1108 * If we have less than the fifo 'half-full' threshold to transfer, 1109 * trigger a PIO interrupt as soon as any data is available. 1110 */ 1111 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) 1112 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); 1113 1114 /* 1115 * If we run out of data, disable the data IRQs; this 1116 * prevents a race where the FIFO becomes empty before 1117 * the chip itself has disabled the data path, and 1118 * stops us racing with our data end IRQ. 1119 */ 1120 if (host->size == 0) { 1121 mmci_set_mask1(host, 0); 1122 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); 1123 } 1124 1125 return IRQ_HANDLED; 1126} 1127 1128/* 1129 * Handle completion of command and data transfers. 1130 */ 1131static irqreturn_t mmci_irq(int irq, void *dev_id) 1132{ 1133 struct mmci_host *host = dev_id; 1134 u32 status; 1135 int ret = 0; 1136 1137 spin_lock(&host->lock); 1138 1139 do { 1140 struct mmc_command *cmd; 1141 struct mmc_data *data; 1142 1143 status = readl(host->base + MMCISTATUS); 1144 1145 if (host->singleirq) { 1146 if (status & readl(host->base + MMCIMASK1)) 1147 mmci_pio_irq(irq, dev_id); 1148 1149 status &= ~MCI_IRQ1MASK; 1150 } 1151 1152 /* 1153 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's 1154 * enabled) since the HW seems to be triggering the IRQ on both 1155 * edges while monitoring DAT0 for busy completion. 1156 */ 1157 status &= readl(host->base + MMCIMASK0); 1158 writel(status, host->base + MMCICLEAR); 1159 1160 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); 1161 1162 cmd = host->cmd; 1163 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT| 1164 MCI_CMDSENT|MCI_CMDRESPEND) && cmd) 1165 mmci_cmd_irq(host, cmd, status); 1166 1167 data = host->data; 1168 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| 1169 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| 1170 MCI_DATABLOCKEND) && data) 1171 mmci_data_irq(host, data, status); 1172 1173 /* Don't poll for busy completion in irq context. */ 1174 if (host->busy_status) 1175 status &= ~MCI_ST_CARDBUSY; 1176 1177 ret = 1; 1178 } while (status); 1179 1180 spin_unlock(&host->lock); 1181 1182 return IRQ_RETVAL(ret); 1183} 1184 1185static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1186{ 1187 struct mmci_host *host = mmc_priv(mmc); 1188 unsigned long flags; 1189 1190 WARN_ON(host->mrq != NULL); 1191 1192 mrq->cmd->error = mmci_validate_data(host, mrq->data); 1193 if (mrq->cmd->error) { 1194 mmc_request_done(mmc, mrq); 1195 return; 1196 } 1197 1198 pm_runtime_get_sync(mmc_dev(mmc)); 1199 1200 spin_lock_irqsave(&host->lock, flags); 1201 1202 host->mrq = mrq; 1203 1204 if (mrq->data) 1205 mmci_get_next_data(host, mrq->data); 1206 1207 if (mrq->data && mrq->data->flags & MMC_DATA_READ) 1208 mmci_start_data(host, mrq->data); 1209 1210 if (mrq->sbc) 1211 mmci_start_command(host, mrq->sbc, 0); 1212 else 1213 mmci_start_command(host, mrq->cmd, 0); 1214 1215 spin_unlock_irqrestore(&host->lock, flags); 1216} 1217 1218static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1219{ 1220 struct mmci_host *host = mmc_priv(mmc); 1221 struct variant_data *variant = host->variant; 1222 u32 pwr = 0; 1223 unsigned long flags; 1224 int ret; 1225 1226 pm_runtime_get_sync(mmc_dev(mmc)); 1227 1228 if (host->plat->ios_handler && 1229 host->plat->ios_handler(mmc_dev(mmc), ios)) 1230 dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); 1231 1232 switch (ios->power_mode) { 1233 case MMC_POWER_OFF: 1234 if (!IS_ERR(mmc->supply.vmmc)) 1235 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1236 1237 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1238 regulator_disable(mmc->supply.vqmmc); 1239 host->vqmmc_enabled = false; 1240 } 1241 1242 break; 1243 case MMC_POWER_UP: 1244 if (!IS_ERR(mmc->supply.vmmc)) 1245 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1246 1247 /* 1248 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP 1249 * and instead uses MCI_PWR_ON so apply whatever value is 1250 * configured in the variant data. 1251 */ 1252 pwr |= variant->pwrreg_powerup; 1253 1254 break; 1255 case MMC_POWER_ON: 1256 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1257 ret = regulator_enable(mmc->supply.vqmmc); 1258 if (ret < 0) 1259 dev_err(mmc_dev(mmc), 1260 "failed to enable vqmmc regulator\n"); 1261 else 1262 host->vqmmc_enabled = true; 1263 } 1264 1265 pwr |= MCI_PWR_ON; 1266 break; 1267 } 1268 1269 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { 1270 /* 1271 * The ST Micro variant has some additional bits 1272 * indicating signal direction for the signals in 1273 * the SD/MMC bus and feedback-clock usage. 1274 */ 1275 pwr |= host->pwr_reg_add; 1276 1277 if (ios->bus_width == MMC_BUS_WIDTH_4) 1278 pwr &= ~MCI_ST_DATA74DIREN; 1279 else if (ios->bus_width == MMC_BUS_WIDTH_1) 1280 pwr &= (~MCI_ST_DATA74DIREN & 1281 ~MCI_ST_DATA31DIREN & 1282 ~MCI_ST_DATA2DIREN); 1283 } 1284 1285 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { 1286 if (host->hw_designer != AMBA_VENDOR_ST) 1287 pwr |= MCI_ROD; 1288 else { 1289 /* 1290 * The ST Micro variant use the ROD bit for something 1291 * else and only has OD (Open Drain). 1292 */ 1293 pwr |= MCI_OD; 1294 } 1295 } 1296 1297 /* 1298 * If clock = 0 and the variant requires the MMCIPOWER to be used for 1299 * gating the clock, the MCI_PWR_ON bit is cleared. 1300 */ 1301 if (!ios->clock && variant->pwrreg_clkgate) 1302 pwr &= ~MCI_PWR_ON; 1303 1304 spin_lock_irqsave(&host->lock, flags); 1305 1306 mmci_set_clkreg(host, ios->clock); 1307 mmci_write_pwrreg(host, pwr); 1308 mmci_reg_delay(host); 1309 1310 spin_unlock_irqrestore(&host->lock, flags); 1311 1312 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1313 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1314} 1315 1316static int mmci_get_cd(struct mmc_host *mmc) 1317{ 1318 struct mmci_host *host = mmc_priv(mmc); 1319 struct mmci_platform_data *plat = host->plat; 1320 unsigned int status = mmc_gpio_get_cd(mmc); 1321 1322 if (status == -ENOSYS) { 1323 if (!plat->status) 1324 return 1; /* Assume always present */ 1325 1326 status = plat->status(mmc_dev(host->mmc)); 1327 } 1328 return status; 1329} 1330 1331static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 1332{ 1333 int ret = 0; 1334 1335 if (!IS_ERR(mmc->supply.vqmmc)) { 1336 1337 pm_runtime_get_sync(mmc_dev(mmc)); 1338 1339 switch (ios->signal_voltage) { 1340 case MMC_SIGNAL_VOLTAGE_330: 1341 ret = regulator_set_voltage(mmc->supply.vqmmc, 1342 2700000, 3600000); 1343 break; 1344 case MMC_SIGNAL_VOLTAGE_180: 1345 ret = regulator_set_voltage(mmc->supply.vqmmc, 1346 1700000, 1950000); 1347 break; 1348 case MMC_SIGNAL_VOLTAGE_120: 1349 ret = regulator_set_voltage(mmc->supply.vqmmc, 1350 1100000, 1300000); 1351 break; 1352 } 1353 1354 if (ret) 1355 dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); 1356 1357 pm_runtime_mark_last_busy(mmc_dev(mmc)); 1358 pm_runtime_put_autosuspend(mmc_dev(mmc)); 1359 } 1360 1361 return ret; 1362} 1363 1364static struct mmc_host_ops mmci_ops = { 1365 .request = mmci_request, 1366 .pre_req = mmci_pre_request, 1367 .post_req = mmci_post_request, 1368 .set_ios = mmci_set_ios, 1369 .get_ro = mmc_gpio_get_ro, 1370 .get_cd = mmci_get_cd, 1371 .start_signal_voltage_switch = mmci_sig_volt_switch, 1372}; 1373 1374static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) 1375{ 1376 struct mmci_host *host = mmc_priv(mmc); 1377 int ret = mmc_of_parse(mmc); 1378 1379 if (ret) 1380 return ret; 1381 1382 if (of_get_property(np, "st,sig-dir-dat0", NULL)) 1383 host->pwr_reg_add |= MCI_ST_DATA0DIREN; 1384 if (of_get_property(np, "st,sig-dir-dat2", NULL)) 1385 host->pwr_reg_add |= MCI_ST_DATA2DIREN; 1386 if (of_get_property(np, "st,sig-dir-dat31", NULL)) 1387 host->pwr_reg_add |= MCI_ST_DATA31DIREN; 1388 if (of_get_property(np, "st,sig-dir-dat74", NULL)) 1389 host->pwr_reg_add |= MCI_ST_DATA74DIREN; 1390 if (of_get_property(np, "st,sig-dir-cmd", NULL)) 1391 host->pwr_reg_add |= MCI_ST_CMDDIREN; 1392 if (of_get_property(np, "st,sig-pin-fbclk", NULL)) 1393 host->pwr_reg_add |= MCI_ST_FBCLKEN; 1394 1395 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) 1396 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; 1397 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) 1398 mmc->caps |= MMC_CAP_SD_HIGHSPEED; 1399 1400 return 0; 1401} 1402 1403static int mmci_probe(struct amba_device *dev, 1404 const struct amba_id *id) 1405{ 1406 struct mmci_platform_data *plat = dev->dev.platform_data; 1407 struct device_node *np = dev->dev.of_node; 1408 struct variant_data *variant = id->data; 1409 struct mmci_host *host; 1410 struct mmc_host *mmc; 1411 int ret; 1412 1413 /* Must have platform data or Device Tree. */ 1414 if (!plat && !np) { 1415 dev_err(&dev->dev, "No plat data or DT found\n"); 1416 return -EINVAL; 1417 } 1418 1419 if (!plat) { 1420 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); 1421 if (!plat) 1422 return -ENOMEM; 1423 } 1424 1425 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); 1426 if (!mmc) 1427 return -ENOMEM; 1428 1429 ret = mmci_of_parse(np, mmc); 1430 if (ret) 1431 goto host_free; 1432 1433 host = mmc_priv(mmc); 1434 host->mmc = mmc; 1435 1436 host->hw_designer = amba_manf(dev); 1437 host->hw_revision = amba_rev(dev); 1438 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); 1439 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); 1440 1441 host->clk = devm_clk_get(&dev->dev, NULL); 1442 if (IS_ERR(host->clk)) { 1443 ret = PTR_ERR(host->clk); 1444 goto host_free; 1445 } 1446 1447 ret = clk_prepare_enable(host->clk); 1448 if (ret) 1449 goto host_free; 1450 1451 host->plat = plat; 1452 host->variant = variant; 1453 host->mclk = clk_get_rate(host->clk); 1454 /* 1455 * According to the spec, mclk is max 100 MHz, 1456 * so we try to adjust the clock down to this, 1457 * (if possible). 1458 */ 1459 if (host->mclk > 100000000) { 1460 ret = clk_set_rate(host->clk, 100000000); 1461 if (ret < 0) 1462 goto clk_disable; 1463 host->mclk = clk_get_rate(host->clk); 1464 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", 1465 host->mclk); 1466 } 1467 1468 host->phybase = dev->res.start; 1469 host->base = devm_ioremap_resource(&dev->dev, &dev->res); 1470 if (IS_ERR(host->base)) { 1471 ret = PTR_ERR(host->base); 1472 goto clk_disable; 1473 } 1474 1475 /* 1476 * The ARM and ST versions of the block have slightly different 1477 * clock divider equations which means that the minimum divider 1478 * differs too. 1479 */ 1480 if (variant->st_clkdiv) 1481 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); 1482 else 1483 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); 1484 /* 1485 * If no maximum operating frequency is supplied, fall back to use 1486 * the module parameter, which has a (low) default value in case it 1487 * is not specified. Either value must not exceed the clock rate into 1488 * the block, of course. 1489 */ 1490 if (mmc->f_max) 1491 mmc->f_max = min(host->mclk, mmc->f_max); 1492 else 1493 mmc->f_max = min(host->mclk, fmax); 1494 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); 1495 1496 /* Get regulators and the supported OCR mask */ 1497 mmc_regulator_get_supply(mmc); 1498 if (!mmc->ocr_avail) 1499 mmc->ocr_avail = plat->ocr_mask; 1500 else if (plat->ocr_mask) 1501 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1502 1503 /* DT takes precedence over platform data. */ 1504 if (!np) { 1505 if (!plat->cd_invert) 1506 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; 1507 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1508 } 1509 1510 /* We support these capabilities. */ 1511 mmc->caps |= MMC_CAP_CMD23; 1512 1513 if (variant->busy_detect) { 1514 mmci_ops.card_busy = mmci_card_busy; 1515 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE); 1516 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1517 mmc->max_busy_timeout = 0; 1518 } 1519 1520 mmc->ops = &mmci_ops; 1521 1522 /* We support these PM capabilities. */ 1523 mmc->pm_caps |= MMC_PM_KEEP_POWER; 1524 1525 /* 1526 * We can do SGIO 1527 */ 1528 mmc->max_segs = NR_SG; 1529 1530 /* 1531 * Since only a certain number of bits are valid in the data length 1532 * register, we must ensure that we don't exceed 2^num-1 bytes in a 1533 * single request. 1534 */ 1535 mmc->max_req_size = (1 << variant->datalength_bits) - 1; 1536 1537 /* 1538 * Set the maximum segment size. Since we aren't doing DMA 1539 * (yet) we are only limited by the data length register. 1540 */ 1541 mmc->max_seg_size = mmc->max_req_size; 1542 1543 /* 1544 * Block size can be up to 2048 bytes, but must be a power of two. 1545 */ 1546 mmc->max_blk_size = 1 << 11; 1547 1548 /* 1549 * Limit the number of blocks transferred so that we don't overflow 1550 * the maximum request size. 1551 */ 1552 mmc->max_blk_count = mmc->max_req_size >> 11; 1553 1554 spin_lock_init(&host->lock); 1555 1556 writel(0, host->base + MMCIMASK0); 1557 writel(0, host->base + MMCIMASK1); 1558 writel(0xfff, host->base + MMCICLEAR); 1559 1560 /* If DT, cd/wp gpios must be supplied through it. */ 1561 if (!np && gpio_is_valid(plat->gpio_cd)) { 1562 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0); 1563 if (ret) 1564 goto clk_disable; 1565 } 1566 if (!np && gpio_is_valid(plat->gpio_wp)) { 1567 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp); 1568 if (ret) 1569 goto clk_disable; 1570 } 1571 1572 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, 1573 DRIVER_NAME " (cmd)", host); 1574 if (ret) 1575 goto clk_disable; 1576 1577 if (!dev->irq[1]) 1578 host->singleirq = true; 1579 else { 1580 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, 1581 IRQF_SHARED, DRIVER_NAME " (pio)", host); 1582 if (ret) 1583 goto clk_disable; 1584 } 1585 1586 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1587 1588 amba_set_drvdata(dev, mmc); 1589 1590 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", 1591 mmc_hostname(mmc), amba_part(dev), amba_manf(dev), 1592 amba_rev(dev), (unsigned long long)dev->res.start, 1593 dev->irq[0], dev->irq[1]); 1594 1595 mmci_dma_setup(host); 1596 1597 pm_runtime_set_autosuspend_delay(&dev->dev, 50); 1598 pm_runtime_use_autosuspend(&dev->dev); 1599 pm_runtime_put(&dev->dev); 1600 1601 mmc_add_host(mmc); 1602 1603 return 0; 1604 1605 clk_disable: 1606 clk_disable_unprepare(host->clk); 1607 host_free: 1608 mmc_free_host(mmc); 1609 return ret; 1610} 1611 1612static int mmci_remove(struct amba_device *dev) 1613{ 1614 struct mmc_host *mmc = amba_get_drvdata(dev); 1615 1616 if (mmc) { 1617 struct mmci_host *host = mmc_priv(mmc); 1618 1619 /* 1620 * Undo pm_runtime_put() in probe. We use the _sync 1621 * version here so that we can access the primecell. 1622 */ 1623 pm_runtime_get_sync(&dev->dev); 1624 1625 mmc_remove_host(mmc); 1626 1627 writel(0, host->base + MMCIMASK0); 1628 writel(0, host->base + MMCIMASK1); 1629 1630 writel(0, host->base + MMCICOMMAND); 1631 writel(0, host->base + MMCIDATACTRL); 1632 1633 mmci_dma_release(host); 1634 clk_disable_unprepare(host->clk); 1635 mmc_free_host(mmc); 1636 } 1637 1638 return 0; 1639} 1640 1641#ifdef CONFIG_PM 1642static void mmci_save(struct mmci_host *host) 1643{ 1644 unsigned long flags; 1645 1646 spin_lock_irqsave(&host->lock, flags); 1647 1648 writel(0, host->base + MMCIMASK0); 1649 if (host->variant->pwrreg_nopower) { 1650 writel(0, host->base + MMCIDATACTRL); 1651 writel(0, host->base + MMCIPOWER); 1652 writel(0, host->base + MMCICLOCK); 1653 } 1654 mmci_reg_delay(host); 1655 1656 spin_unlock_irqrestore(&host->lock, flags); 1657} 1658 1659static void mmci_restore(struct mmci_host *host) 1660{ 1661 unsigned long flags; 1662 1663 spin_lock_irqsave(&host->lock, flags); 1664 1665 if (host->variant->pwrreg_nopower) { 1666 writel(host->clk_reg, host->base + MMCICLOCK); 1667 writel(host->datactrl_reg, host->base + MMCIDATACTRL); 1668 writel(host->pwr_reg, host->base + MMCIPOWER); 1669 } 1670 writel(MCI_IRQENABLE, host->base + MMCIMASK0); 1671 mmci_reg_delay(host); 1672 1673 spin_unlock_irqrestore(&host->lock, flags); 1674} 1675 1676static int mmci_runtime_suspend(struct device *dev) 1677{ 1678 struct amba_device *adev = to_amba_device(dev); 1679 struct mmc_host *mmc = amba_get_drvdata(adev); 1680 1681 if (mmc) { 1682 struct mmci_host *host = mmc_priv(mmc); 1683 pinctrl_pm_select_sleep_state(dev); 1684 mmci_save(host); 1685 clk_disable_unprepare(host->clk); 1686 } 1687 1688 return 0; 1689} 1690 1691static int mmci_runtime_resume(struct device *dev) 1692{ 1693 struct amba_device *adev = to_amba_device(dev); 1694 struct mmc_host *mmc = amba_get_drvdata(adev); 1695 1696 if (mmc) { 1697 struct mmci_host *host = mmc_priv(mmc); 1698 clk_prepare_enable(host->clk); 1699 mmci_restore(host); 1700 pinctrl_pm_select_default_state(dev); 1701 } 1702 1703 return 0; 1704} 1705#endif 1706 1707static const struct dev_pm_ops mmci_dev_pm_ops = { 1708 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1709 pm_runtime_force_resume) 1710 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) 1711}; 1712 1713static struct amba_id mmci_ids[] = { 1714 { 1715 .id = 0x00041180, 1716 .mask = 0xff0fffff, 1717 .data = &variant_arm, 1718 }, 1719 { 1720 .id = 0x01041180, 1721 .mask = 0xff0fffff, 1722 .data = &variant_arm_extended_fifo, 1723 }, 1724 { 1725 .id = 0x02041180, 1726 .mask = 0xff0fffff, 1727 .data = &variant_arm_extended_fifo_hwfc, 1728 }, 1729 { 1730 .id = 0x00041181, 1731 .mask = 0x000fffff, 1732 .data = &variant_arm, 1733 }, 1734 /* ST Micro variants */ 1735 { 1736 .id = 0x00180180, 1737 .mask = 0x00ffffff, 1738 .data = &variant_u300, 1739 }, 1740 { 1741 .id = 0x10180180, 1742 .mask = 0xf0ffffff, 1743 .data = &variant_nomadik, 1744 }, 1745 { 1746 .id = 0x00280180, 1747 .mask = 0x00ffffff, 1748 .data = &variant_u300, 1749 }, 1750 { 1751 .id = 0x00480180, 1752 .mask = 0xf0ffffff, 1753 .data = &variant_ux500, 1754 }, 1755 { 1756 .id = 0x10480180, 1757 .mask = 0xf0ffffff, 1758 .data = &variant_ux500v2, 1759 }, 1760 { 0, 0 }, 1761}; 1762 1763MODULE_DEVICE_TABLE(amba, mmci_ids); 1764 1765static struct amba_driver mmci_driver = { 1766 .drv = { 1767 .name = DRIVER_NAME, 1768 .pm = &mmci_dev_pm_ops, 1769 }, 1770 .probe = mmci_probe, 1771 .remove = mmci_remove, 1772 .id_table = mmci_ids, 1773}; 1774 1775module_amba_driver(mmci_driver); 1776 1777module_param(fmax, uint, 0444); 1778 1779MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); 1780MODULE_LICENSE("GPL"); 1781