s3cmci.c revision 26f14947dbf31d60d1a67eee837a6d28c1e8830d
1/* 2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver 3 * 4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de> 5 * 6 * Current driver maintained by Ben Dooks and Simtec Electronics 7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#include <linux/module.h> 15#include <linux/dma-mapping.h> 16#include <linux/clk.h> 17#include <linux/mmc/host.h> 18#include <linux/platform_device.h> 19#include <linux/cpufreq.h> 20#include <linux/debugfs.h> 21#include <linux/seq_file.h> 22#include <linux/gpio.h> 23#include <linux/irq.h> 24#include <linux/io.h> 25 26#include <mach/dma.h> 27 28#include <mach/regs-sdi.h> 29#include <mach/regs-gpio.h> 30 31#include <plat/mci.h> 32 33#include "s3cmci.h" 34 35#define DRIVER_NAME "s3c-mci" 36 37enum dbg_channels { 38 dbg_err = (1 << 0), 39 dbg_debug = (1 << 1), 40 dbg_info = (1 << 2), 41 dbg_irq = (1 << 3), 42 dbg_sg = (1 << 4), 43 dbg_dma = (1 << 5), 44 dbg_pio = (1 << 6), 45 dbg_fail = (1 << 7), 46 dbg_conf = (1 << 8), 47}; 48 49static const int dbgmap_err = dbg_fail; 50static const int dbgmap_info = dbg_info | dbg_conf; 51static const int dbgmap_debug = dbg_err | dbg_debug; 52 53#define dbg(host, channels, args...) \ 54 do { \ 55 if (dbgmap_err & channels) \ 56 dev_err(&host->pdev->dev, args); \ 57 else if (dbgmap_info & channels) \ 58 dev_info(&host->pdev->dev, args); \ 59 else if (dbgmap_debug & channels) \ 60 dev_dbg(&host->pdev->dev, args); \ 61 } while (0) 62 63static struct s3c2410_dma_client s3cmci_dma_client = { 64 .name = "s3c-mci", 65}; 66 67static void finalize_request(struct s3cmci_host *host); 68static void s3cmci_send_request(struct mmc_host *mmc); 69static void s3cmci_reset(struct s3cmci_host *host); 70 71#ifdef CONFIG_MMC_DEBUG 72 73static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) 74{ 75 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize; 76 u32 datcon, datcnt, datsta, fsta, imask; 77 78 con = readl(host->base + S3C2410_SDICON); 79 pre = readl(host->base + S3C2410_SDIPRE); 80 cmdarg = readl(host->base + S3C2410_SDICMDARG); 81 cmdcon = readl(host->base + S3C2410_SDICMDCON); 82 cmdsta = readl(host->base + S3C2410_SDICMDSTAT); 83 r0 = readl(host->base + S3C2410_SDIRSP0); 84 r1 = readl(host->base + S3C2410_SDIRSP1); 85 r2 = readl(host->base + S3C2410_SDIRSP2); 86 r3 = readl(host->base + S3C2410_SDIRSP3); 87 timer = readl(host->base + S3C2410_SDITIMER); 88 bsize = readl(host->base + S3C2410_SDIBSIZE); 89 datcon = readl(host->base + S3C2410_SDIDCON); 90 datcnt = readl(host->base + S3C2410_SDIDCNT); 91 datsta = readl(host->base + S3C2410_SDIDSTA); 92 fsta = readl(host->base + S3C2410_SDIFSTA); 93 imask = readl(host->base + host->sdiimsk); 94 95 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n", 96 prefix, con, pre, timer); 97 98 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n", 99 prefix, cmdcon, cmdarg, cmdsta); 100 101 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]" 102 " DSTA:[%08x] DCNT:[%08x]\n", 103 prefix, datcon, fsta, datsta, datcnt); 104 105 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]" 106 " R2:[%08x] R3:[%08x]\n", 107 prefix, r0, r1, r2, r3); 108} 109 110static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, 111 int stop) 112{ 113 snprintf(host->dbgmsg_cmd, 300, 114 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u", 115 host->ccnt, (stop ? " (STOP)" : ""), 116 cmd->opcode, cmd->arg, cmd->flags, cmd->retries); 117 118 if (cmd->data) { 119 snprintf(host->dbgmsg_dat, 300, 120 "#%u bsize:%u blocks:%u bytes:%u", 121 host->dcnt, cmd->data->blksz, 122 cmd->data->blocks, 123 cmd->data->blocks * cmd->data->blksz); 124 } else { 125 host->dbgmsg_dat[0] = '\0'; 126 } 127} 128 129static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd, 130 int fail) 131{ 132 unsigned int dbglvl = fail ? dbg_fail : dbg_debug; 133 134 if (!cmd) 135 return; 136 137 if (cmd->error == 0) { 138 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n", 139 host->dbgmsg_cmd, cmd->resp[0]); 140 } else { 141 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n", 142 cmd->error, host->dbgmsg_cmd, host->status); 143 } 144 145 if (!cmd->data) 146 return; 147 148 if (cmd->data->error == 0) { 149 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat); 150 } else { 151 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n", 152 cmd->data->error, host->dbgmsg_dat, 153 readl(host->base + S3C2410_SDIDCNT)); 154 } 155} 156#else 157static void dbg_dumpcmd(struct s3cmci_host *host, 158 struct mmc_command *cmd, int fail) { } 159 160static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd, 161 int stop) { } 162 163static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { } 164 165#endif /* CONFIG_MMC_DEBUG */ 166 167/** 168 * s3cmci_host_usedma - return whether the host is using dma or pio 169 * @host: The host state 170 * 171 * Return true if the host is using DMA to transfer data, else false 172 * to use PIO mode. Will return static data depending on the driver 173 * configuration. 174 */ 175static inline bool s3cmci_host_usedma(struct s3cmci_host *host) 176{ 177#ifdef CONFIG_MMC_S3C_PIO 178 return false; 179#elif defined(CONFIG_MMC_S3C_DMA) 180 return true; 181#else 182 return host->dodma; 183#endif 184} 185 186static inline u32 enable_imask(struct s3cmci_host *host, u32 imask) 187{ 188 u32 newmask; 189 190 newmask = readl(host->base + host->sdiimsk); 191 newmask |= imask; 192 193 writel(newmask, host->base + host->sdiimsk); 194 195 return newmask; 196} 197 198static inline u32 disable_imask(struct s3cmci_host *host, u32 imask) 199{ 200 u32 newmask; 201 202 newmask = readl(host->base + host->sdiimsk); 203 newmask &= ~imask; 204 205 writel(newmask, host->base + host->sdiimsk); 206 207 return newmask; 208} 209 210static inline void clear_imask(struct s3cmci_host *host) 211{ 212 u32 mask = readl(host->base + host->sdiimsk); 213 214 /* preserve the SDIO IRQ mask state */ 215 mask &= S3C2410_SDIIMSK_SDIOIRQ; 216 writel(mask, host->base + host->sdiimsk); 217} 218 219/** 220 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled 221 * @host: The host to check. 222 * 223 * Test to see if the SDIO interrupt is being signalled in case the 224 * controller has failed to re-detect a card interrupt. Read GPE8 and 225 * see if it is low and if so, signal a SDIO interrupt. 226 * 227 * This is currently called if a request is finished (we assume that the 228 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is 229 * already being indicated. 230*/ 231static void s3cmci_check_sdio_irq(struct s3cmci_host *host) 232{ 233 if (host->sdio_irqen) { 234 if (gpio_get_value(S3C2410_GPE(8)) == 0) { 235 printk(KERN_DEBUG "%s: signalling irq\n", __func__); 236 mmc_signal_sdio_irq(host->mmc); 237 } 238 } 239} 240 241static inline int get_data_buffer(struct s3cmci_host *host, 242 u32 *bytes, u32 **pointer) 243{ 244 struct scatterlist *sg; 245 246 if (host->pio_active == XFER_NONE) 247 return -EINVAL; 248 249 if ((!host->mrq) || (!host->mrq->data)) 250 return -EINVAL; 251 252 if (host->pio_sgptr >= host->mrq->data->sg_len) { 253 dbg(host, dbg_debug, "no more buffers (%i/%i)\n", 254 host->pio_sgptr, host->mrq->data->sg_len); 255 return -EBUSY; 256 } 257 sg = &host->mrq->data->sg[host->pio_sgptr]; 258 259 *bytes = sg->length; 260 *pointer = sg_virt(sg); 261 262 host->pio_sgptr++; 263 264 dbg(host, dbg_sg, "new buffer (%i/%i)\n", 265 host->pio_sgptr, host->mrq->data->sg_len); 266 267 return 0; 268} 269 270static inline u32 fifo_count(struct s3cmci_host *host) 271{ 272 u32 fifostat = readl(host->base + S3C2410_SDIFSTA); 273 274 fifostat &= S3C2410_SDIFSTA_COUNTMASK; 275 return fifostat; 276} 277 278static inline u32 fifo_free(struct s3cmci_host *host) 279{ 280 u32 fifostat = readl(host->base + S3C2410_SDIFSTA); 281 282 fifostat &= S3C2410_SDIFSTA_COUNTMASK; 283 return 63 - fifostat; 284} 285 286/** 287 * s3cmci_enable_irq - enable IRQ, after having disabled it. 288 * @host: The device state. 289 * @more: True if more IRQs are expected from transfer. 290 * 291 * Enable the main IRQ if needed after it has been disabled. 292 * 293 * The IRQ can be one of the following states: 294 * - disabled during IDLE 295 * - disabled whilst processing data 296 * - enabled during transfer 297 * - enabled whilst awaiting SDIO interrupt detection 298 */ 299static void s3cmci_enable_irq(struct s3cmci_host *host, bool more) 300{ 301 unsigned long flags; 302 bool enable = false; 303 304 local_irq_save(flags); 305 306 host->irq_enabled = more; 307 host->irq_disabled = false; 308 309 enable = more | host->sdio_irqen; 310 311 if (host->irq_state != enable) { 312 host->irq_state = enable; 313 314 if (enable) 315 enable_irq(host->irq); 316 else 317 disable_irq(host->irq); 318 } 319 320 local_irq_restore(flags); 321} 322 323/** 324 * 325 */ 326static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer) 327{ 328 unsigned long flags; 329 330 local_irq_save(flags); 331 332 //printk(KERN_DEBUG "%s: transfer %d\n", __func__, transfer); 333 334 host->irq_disabled = transfer; 335 336 if (transfer && host->irq_state) { 337 host->irq_state = false; 338 disable_irq(host->irq); 339 } 340 341 local_irq_restore(flags); 342} 343 344static void do_pio_read(struct s3cmci_host *host) 345{ 346 int res; 347 u32 fifo; 348 u32 *ptr; 349 u32 fifo_words; 350 void __iomem *from_ptr; 351 352 /* write real prescaler to host, it might be set slow to fix */ 353 writel(host->prescaler, host->base + S3C2410_SDIPRE); 354 355 from_ptr = host->base + host->sdidata; 356 357 while ((fifo = fifo_count(host))) { 358 if (!host->pio_bytes) { 359 res = get_data_buffer(host, &host->pio_bytes, 360 &host->pio_ptr); 361 if (res) { 362 host->pio_active = XFER_NONE; 363 host->complete_what = COMPLETION_FINALIZE; 364 365 dbg(host, dbg_pio, "pio_read(): " 366 "complete (no more data).\n"); 367 return; 368 } 369 370 dbg(host, dbg_pio, 371 "pio_read(): new target: [%i]@[%p]\n", 372 host->pio_bytes, host->pio_ptr); 373 } 374 375 dbg(host, dbg_pio, 376 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n", 377 fifo, host->pio_bytes, 378 readl(host->base + S3C2410_SDIDCNT)); 379 380 /* If we have reached the end of the block, we can 381 * read a word and get 1 to 3 bytes. If we in the 382 * middle of the block, we have to read full words, 383 * otherwise we will write garbage, so round down to 384 * an even multiple of 4. */ 385 if (fifo >= host->pio_bytes) 386 fifo = host->pio_bytes; 387 else 388 fifo -= fifo & 3; 389 390 host->pio_bytes -= fifo; 391 host->pio_count += fifo; 392 393 fifo_words = fifo >> 2; 394 ptr = host->pio_ptr; 395 while (fifo_words--) 396 *ptr++ = readl(from_ptr); 397 host->pio_ptr = ptr; 398 399 if (fifo & 3) { 400 u32 n = fifo & 3; 401 u32 data = readl(from_ptr); 402 u8 *p = (u8 *)host->pio_ptr; 403 404 while (n--) { 405 *p++ = data; 406 data >>= 8; 407 } 408 } 409 } 410 411 if (!host->pio_bytes) { 412 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr); 413 if (res) { 414 dbg(host, dbg_pio, 415 "pio_read(): complete (no more buffers).\n"); 416 host->pio_active = XFER_NONE; 417 host->complete_what = COMPLETION_FINALIZE; 418 419 return; 420 } 421 } 422 423 enable_imask(host, 424 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST); 425} 426 427static void do_pio_write(struct s3cmci_host *host) 428{ 429 void __iomem *to_ptr; 430 int res; 431 u32 fifo; 432 u32 *ptr; 433 434 to_ptr = host->base + host->sdidata; 435 436 while ((fifo = fifo_free(host)) > 3) { 437 if (!host->pio_bytes) { 438 res = get_data_buffer(host, &host->pio_bytes, 439 &host->pio_ptr); 440 if (res) { 441 dbg(host, dbg_pio, 442 "pio_write(): complete (no more data).\n"); 443 host->pio_active = XFER_NONE; 444 445 return; 446 } 447 448 dbg(host, dbg_pio, 449 "pio_write(): new source: [%i]@[%p]\n", 450 host->pio_bytes, host->pio_ptr); 451 452 } 453 454 /* If we have reached the end of the block, we have to 455 * write exactly the remaining number of bytes. If we 456 * in the middle of the block, we have to write full 457 * words, so round down to an even multiple of 4. */ 458 if (fifo >= host->pio_bytes) 459 fifo = host->pio_bytes; 460 else 461 fifo -= fifo & 3; 462 463 host->pio_bytes -= fifo; 464 host->pio_count += fifo; 465 466 fifo = (fifo + 3) >> 2; 467 ptr = host->pio_ptr; 468 while (fifo--) 469 writel(*ptr++, to_ptr); 470 host->pio_ptr = ptr; 471 } 472 473 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); 474} 475 476static void pio_tasklet(unsigned long data) 477{ 478 struct s3cmci_host *host = (struct s3cmci_host *) data; 479 480 s3cmci_disable_irq(host, true); 481 482 if (host->pio_active == XFER_WRITE) 483 do_pio_write(host); 484 485 if (host->pio_active == XFER_READ) 486 do_pio_read(host); 487 488 if (host->complete_what == COMPLETION_FINALIZE) { 489 clear_imask(host); 490 if (host->pio_active != XFER_NONE) { 491 dbg(host, dbg_err, "unfinished %s " 492 "- pio_count:[%u] pio_bytes:[%u]\n", 493 (host->pio_active == XFER_READ) ? "read" : "write", 494 host->pio_count, host->pio_bytes); 495 496 if (host->mrq->data) 497 host->mrq->data->error = -EINVAL; 498 } 499 500 s3cmci_enable_irq(host, false); 501 finalize_request(host); 502 } else 503 s3cmci_enable_irq(host, true); 504} 505 506/* 507 * ISR for SDI Interface IRQ 508 * Communication between driver and ISR works as follows: 509 * host->mrq points to current request 510 * host->complete_what Indicates when the request is considered done 511 * COMPLETION_CMDSENT when the command was sent 512 * COMPLETION_RSPFIN when a response was received 513 * COMPLETION_XFERFINISH when the data transfer is finished 514 * COMPLETION_XFERFINISH_RSPFIN both of the above. 515 * host->complete_request is the completion-object the driver waits for 516 * 517 * 1) Driver sets up host->mrq and host->complete_what 518 * 2) Driver prepares the transfer 519 * 3) Driver enables interrupts 520 * 4) Driver starts transfer 521 * 5) Driver waits for host->complete_rquest 522 * 6) ISR checks for request status (errors and success) 523 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error 524 * 7) ISR completes host->complete_request 525 * 8) ISR disables interrupts 526 * 9) Driver wakes up and takes care of the request 527 * 528 * Note: "->error"-fields are expected to be set to 0 before the request 529 * was issued by mmc.c - therefore they are only set, when an error 530 * contition comes up 531 */ 532 533static irqreturn_t s3cmci_irq(int irq, void *dev_id) 534{ 535 struct s3cmci_host *host = dev_id; 536 struct mmc_command *cmd; 537 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk; 538 u32 mci_cclear = 0, mci_dclear; 539 unsigned long iflags; 540 541 mci_dsta = readl(host->base + S3C2410_SDIDSTA); 542 mci_imsk = readl(host->base + host->sdiimsk); 543 544 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) { 545 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) { 546 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT; 547 writel(mci_dclear, host->base + S3C2410_SDIDSTA); 548 549 mmc_signal_sdio_irq(host->mmc); 550 return IRQ_HANDLED; 551 } 552 } 553 554 spin_lock_irqsave(&host->complete_lock, iflags); 555 556 mci_csta = readl(host->base + S3C2410_SDICMDSTAT); 557 mci_dcnt = readl(host->base + S3C2410_SDIDCNT); 558 mci_fsta = readl(host->base + S3C2410_SDIFSTA); 559 mci_dclear = 0; 560 561 if ((host->complete_what == COMPLETION_NONE) || 562 (host->complete_what == COMPLETION_FINALIZE)) { 563 host->status = "nothing to complete"; 564 clear_imask(host); 565 goto irq_out; 566 } 567 568 if (!host->mrq) { 569 host->status = "no active mrq"; 570 clear_imask(host); 571 goto irq_out; 572 } 573 574 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd; 575 576 if (!cmd) { 577 host->status = "no active cmd"; 578 clear_imask(host); 579 goto irq_out; 580 } 581 582 if (!s3cmci_host_usedma(host)) { 583 if ((host->pio_active == XFER_WRITE) && 584 (mci_fsta & S3C2410_SDIFSTA_TFDET)) { 585 586 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); 587 tasklet_schedule(&host->pio_tasklet); 588 host->status = "pio tx"; 589 } 590 591 if ((host->pio_active == XFER_READ) && 592 (mci_fsta & S3C2410_SDIFSTA_RFDET)) { 593 594 disable_imask(host, 595 S3C2410_SDIIMSK_RXFIFOHALF | 596 S3C2410_SDIIMSK_RXFIFOLAST); 597 598 tasklet_schedule(&host->pio_tasklet); 599 host->status = "pio rx"; 600 } 601 } 602 603 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) { 604 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n"); 605 cmd->error = -ETIMEDOUT; 606 host->status = "error: command timeout"; 607 goto fail_transfer; 608 } 609 610 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) { 611 if (host->complete_what == COMPLETION_CMDSENT) { 612 host->status = "ok: command sent"; 613 goto close_transfer; 614 } 615 616 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT; 617 } 618 619 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) { 620 if (cmd->flags & MMC_RSP_CRC) { 621 if (host->mrq->cmd->flags & MMC_RSP_136) { 622 dbg(host, dbg_irq, 623 "fixup: ignore CRC fail with long rsp\n"); 624 } else { 625 /* note, we used to fail the transfer 626 * here, but it seems that this is just 627 * the hardware getting it wrong. 628 * 629 * cmd->error = -EILSEQ; 630 * host->status = "error: bad command crc"; 631 * goto fail_transfer; 632 */ 633 } 634 } 635 636 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL; 637 } 638 639 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) { 640 if (host->complete_what == COMPLETION_RSPFIN) { 641 host->status = "ok: command response received"; 642 goto close_transfer; 643 } 644 645 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) 646 host->complete_what = COMPLETION_XFERFINISH; 647 648 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN; 649 } 650 651 /* errors handled after this point are only relevant 652 when a data transfer is in progress */ 653 654 if (!cmd->data) 655 goto clear_status_bits; 656 657 /* Check for FIFO failure */ 658 if (host->is2440) { 659 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) { 660 dbg(host, dbg_err, "FIFO failure\n"); 661 host->mrq->data->error = -EILSEQ; 662 host->status = "error: 2440 fifo failure"; 663 goto fail_transfer; 664 } 665 } else { 666 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) { 667 dbg(host, dbg_err, "FIFO failure\n"); 668 cmd->data->error = -EILSEQ; 669 host->status = "error: fifo failure"; 670 goto fail_transfer; 671 } 672 } 673 674 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) { 675 dbg(host, dbg_err, "bad data crc (outgoing)\n"); 676 cmd->data->error = -EILSEQ; 677 host->status = "error: bad data crc (outgoing)"; 678 goto fail_transfer; 679 } 680 681 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) { 682 dbg(host, dbg_err, "bad data crc (incoming)\n"); 683 cmd->data->error = -EILSEQ; 684 host->status = "error: bad data crc (incoming)"; 685 goto fail_transfer; 686 } 687 688 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) { 689 dbg(host, dbg_err, "data timeout\n"); 690 cmd->data->error = -ETIMEDOUT; 691 host->status = "error: data timeout"; 692 goto fail_transfer; 693 } 694 695 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) { 696 if (host->complete_what == COMPLETION_XFERFINISH) { 697 host->status = "ok: data transfer completed"; 698 goto close_transfer; 699 } 700 701 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN) 702 host->complete_what = COMPLETION_RSPFIN; 703 704 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH; 705 } 706 707clear_status_bits: 708 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT); 709 writel(mci_dclear, host->base + S3C2410_SDIDSTA); 710 711 goto irq_out; 712 713fail_transfer: 714 host->pio_active = XFER_NONE; 715 716close_transfer: 717 host->complete_what = COMPLETION_FINALIZE; 718 719 clear_imask(host); 720 tasklet_schedule(&host->pio_tasklet); 721 722 goto irq_out; 723 724irq_out: 725 dbg(host, dbg_irq, 726 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n", 727 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status); 728 729 spin_unlock_irqrestore(&host->complete_lock, iflags); 730 return IRQ_HANDLED; 731 732} 733 734/* 735 * ISR for the CardDetect Pin 736*/ 737 738static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id) 739{ 740 struct s3cmci_host *host = (struct s3cmci_host *)dev_id; 741 742 dbg(host, dbg_irq, "card detect\n"); 743 744 mmc_detect_change(host->mmc, msecs_to_jiffies(500)); 745 746 return IRQ_HANDLED; 747} 748 749static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch, 750 void *buf_id, int size, 751 enum s3c2410_dma_buffresult result) 752{ 753 struct s3cmci_host *host = buf_id; 754 unsigned long iflags; 755 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt; 756 757 mci_csta = readl(host->base + S3C2410_SDICMDSTAT); 758 mci_dsta = readl(host->base + S3C2410_SDIDSTA); 759 mci_fsta = readl(host->base + S3C2410_SDIFSTA); 760 mci_dcnt = readl(host->base + S3C2410_SDIDCNT); 761 762 BUG_ON(!host->mrq); 763 BUG_ON(!host->mrq->data); 764 BUG_ON(!host->dmatogo); 765 766 spin_lock_irqsave(&host->complete_lock, iflags); 767 768 if (result != S3C2410_RES_OK) { 769 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x " 770 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n", 771 mci_csta, mci_dsta, mci_fsta, 772 mci_dcnt, result, host->dmatogo); 773 774 goto fail_request; 775 } 776 777 host->dmatogo--; 778 if (host->dmatogo) { 779 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] " 780 "DCNT:[%08x] toGo:%u\n", 781 size, mci_dsta, mci_dcnt, host->dmatogo); 782 783 goto out; 784 } 785 786 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n", 787 size, mci_dsta, mci_dcnt); 788 789 host->complete_what = COMPLETION_FINALIZE; 790 791out: 792 tasklet_schedule(&host->pio_tasklet); 793 spin_unlock_irqrestore(&host->complete_lock, iflags); 794 return; 795 796fail_request: 797 host->mrq->data->error = -EINVAL; 798 host->complete_what = COMPLETION_FINALIZE; 799 clear_imask(host); 800 801 goto out; 802} 803 804static void finalize_request(struct s3cmci_host *host) 805{ 806 struct mmc_request *mrq = host->mrq; 807 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 808 int debug_as_failure = 0; 809 810 if (host->complete_what != COMPLETION_FINALIZE) 811 return; 812 813 if (!mrq) 814 return; 815 816 if (cmd->data && (cmd->error == 0) && 817 (cmd->data->error == 0)) { 818 if (s3cmci_host_usedma(host) && (!host->dma_complete)) { 819 dbg(host, dbg_dma, "DMA Missing!\n"); 820 return; 821 } 822 } 823 824 /* Read response from controller. */ 825 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0); 826 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1); 827 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2); 828 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3); 829 830 writel(host->prescaler, host->base + S3C2410_SDIPRE); 831 832 if (cmd->error) 833 debug_as_failure = 1; 834 835 if (cmd->data && cmd->data->error) 836 debug_as_failure = 1; 837 838 dbg_dumpcmd(host, cmd, debug_as_failure); 839 840 /* Cleanup controller */ 841 writel(0, host->base + S3C2410_SDICMDARG); 842 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); 843 writel(0, host->base + S3C2410_SDICMDCON); 844 clear_imask(host); 845 846 if (cmd->data && cmd->error) 847 cmd->data->error = cmd->error; 848 849 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) { 850 host->cmd_is_stop = 1; 851 s3cmci_send_request(host->mmc); 852 return; 853 } 854 855 /* If we have no data transfer we are finished here */ 856 if (!mrq->data) 857 goto request_done; 858 859 /* Calulate the amout of bytes transfer if there was no error */ 860 if (mrq->data->error == 0) { 861 mrq->data->bytes_xfered = 862 (mrq->data->blocks * mrq->data->blksz); 863 } else { 864 mrq->data->bytes_xfered = 0; 865 } 866 867 /* If we had an error while transfering data we flush the 868 * DMA channel and the fifo to clear out any garbage. */ 869 if (mrq->data->error != 0) { 870 if (s3cmci_host_usedma(host)) 871 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); 872 873 if (host->is2440) { 874 /* Clear failure register and reset fifo. */ 875 writel(S3C2440_SDIFSTA_FIFORESET | 876 S3C2440_SDIFSTA_FIFOFAIL, 877 host->base + S3C2410_SDIFSTA); 878 } else { 879 u32 mci_con; 880 881 /* reset fifo */ 882 mci_con = readl(host->base + S3C2410_SDICON); 883 mci_con |= S3C2410_SDICON_FIFORESET; 884 885 writel(mci_con, host->base + S3C2410_SDICON); 886 } 887 } 888 889request_done: 890 host->complete_what = COMPLETION_NONE; 891 host->mrq = NULL; 892 893 s3cmci_check_sdio_irq(host); 894 mmc_request_done(host->mmc, mrq); 895} 896 897static void s3cmci_dma_setup(struct s3cmci_host *host, 898 enum s3c2410_dmasrc source) 899{ 900 static enum s3c2410_dmasrc last_source = -1; 901 static int setup_ok; 902 903 if (last_source == source) 904 return; 905 906 last_source = source; 907 908 s3c2410_dma_devconfig(host->dma, source, 909 host->mem->start + host->sdidata); 910 911 if (!setup_ok) { 912 s3c2410_dma_config(host->dma, 4); 913 s3c2410_dma_set_buffdone_fn(host->dma, 914 s3cmci_dma_done_callback); 915 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); 916 setup_ok = 1; 917 } 918} 919 920static void s3cmci_send_command(struct s3cmci_host *host, 921 struct mmc_command *cmd) 922{ 923 u32 ccon, imsk; 924 925 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT | 926 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT | 927 S3C2410_SDIIMSK_RESPONSECRC; 928 929 enable_imask(host, imsk); 930 931 if (cmd->data) 932 host->complete_what = COMPLETION_XFERFINISH_RSPFIN; 933 else if (cmd->flags & MMC_RSP_PRESENT) 934 host->complete_what = COMPLETION_RSPFIN; 935 else 936 host->complete_what = COMPLETION_CMDSENT; 937 938 writel(cmd->arg, host->base + S3C2410_SDICMDARG); 939 940 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX; 941 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART; 942 943 if (cmd->flags & MMC_RSP_PRESENT) 944 ccon |= S3C2410_SDICMDCON_WAITRSP; 945 946 if (cmd->flags & MMC_RSP_136) 947 ccon |= S3C2410_SDICMDCON_LONGRSP; 948 949 writel(ccon, host->base + S3C2410_SDICMDCON); 950} 951 952static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data) 953{ 954 u32 dcon, imsk, stoptries = 3; 955 956 /* write DCON register */ 957 958 if (!data) { 959 writel(0, host->base + S3C2410_SDIDCON); 960 return 0; 961 } 962 963 if ((data->blksz & 3) != 0) { 964 /* We cannot deal with unaligned blocks with more than 965 * one block being transfered. */ 966 967 if (data->blocks > 1) { 968 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz); 969 return -EINVAL; 970 } 971 } 972 973 while (readl(host->base + S3C2410_SDIDSTA) & 974 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) { 975 976 dbg(host, dbg_err, 977 "mci_setup_data() transfer stillin progress.\n"); 978 979 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON); 980 s3cmci_reset(host); 981 982 if ((stoptries--) == 0) { 983 dbg_dumpregs(host, "DRF"); 984 return -EINVAL; 985 } 986 } 987 988 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK; 989 990 if (s3cmci_host_usedma(host)) 991 dcon |= S3C2410_SDIDCON_DMAEN; 992 993 if (host->bus_width == MMC_BUS_WIDTH_4) 994 dcon |= S3C2410_SDIDCON_WIDEBUS; 995 996 if (!(data->flags & MMC_DATA_STREAM)) 997 dcon |= S3C2410_SDIDCON_BLOCKMODE; 998 999 if (data->flags & MMC_DATA_WRITE) { 1000 dcon |= S3C2410_SDIDCON_TXAFTERRESP; 1001 dcon |= S3C2410_SDIDCON_XFER_TXSTART; 1002 } 1003 1004 if (data->flags & MMC_DATA_READ) { 1005 dcon |= S3C2410_SDIDCON_RXAFTERCMD; 1006 dcon |= S3C2410_SDIDCON_XFER_RXSTART; 1007 } 1008 1009 if (host->is2440) { 1010 dcon |= S3C2440_SDIDCON_DS_WORD; 1011 dcon |= S3C2440_SDIDCON_DATSTART; 1012 } 1013 1014 writel(dcon, host->base + S3C2410_SDIDCON); 1015 1016 /* write BSIZE register */ 1017 1018 writel(data->blksz, host->base + S3C2410_SDIBSIZE); 1019 1020 /* add to IMASK register */ 1021 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC | 1022 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH; 1023 1024 enable_imask(host, imsk); 1025 1026 /* write TIMER register */ 1027 1028 if (host->is2440) { 1029 writel(0x007FFFFF, host->base + S3C2410_SDITIMER); 1030 } else { 1031 writel(0x0000FFFF, host->base + S3C2410_SDITIMER); 1032 1033 /* FIX: set slow clock to prevent timeouts on read */ 1034 if (data->flags & MMC_DATA_READ) 1035 writel(0xFF, host->base + S3C2410_SDIPRE); 1036 } 1037 1038 return 0; 1039} 1040 1041#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ) 1042 1043static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data) 1044{ 1045 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; 1046 1047 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); 1048 1049 host->pio_sgptr = 0; 1050 host->pio_bytes = 0; 1051 host->pio_count = 0; 1052 host->pio_active = rw ? XFER_WRITE : XFER_READ; 1053 1054 if (rw) { 1055 do_pio_write(host); 1056 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF); 1057 } else { 1058 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF 1059 | S3C2410_SDIIMSK_RXFIFOLAST); 1060 } 1061 1062 return 0; 1063} 1064 1065static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data) 1066{ 1067 int dma_len, i; 1068 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0; 1069 1070 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR); 1071 1072 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW); 1073 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); 1074 1075 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 1076 (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); 1077 1078 if (dma_len == 0) 1079 return -ENOMEM; 1080 1081 host->dma_complete = 0; 1082 host->dmatogo = dma_len; 1083 1084 for (i = 0; i < dma_len; i++) { 1085 int res; 1086 1087 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i, 1088 sg_dma_address(&data->sg[i]), 1089 sg_dma_len(&data->sg[i])); 1090 1091 res = s3c2410_dma_enqueue(host->dma, (void *) host, 1092 sg_dma_address(&data->sg[i]), 1093 sg_dma_len(&data->sg[i])); 1094 1095 if (res) { 1096 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH); 1097 return -EBUSY; 1098 } 1099 } 1100 1101 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START); 1102 1103 return 0; 1104} 1105 1106static void s3cmci_send_request(struct mmc_host *mmc) 1107{ 1108 struct s3cmci_host *host = mmc_priv(mmc); 1109 struct mmc_request *mrq = host->mrq; 1110 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd; 1111 1112 host->ccnt++; 1113 prepare_dbgmsg(host, cmd, host->cmd_is_stop); 1114 1115 /* Clear command, data and fifo status registers 1116 Fifo clear only necessary on 2440, but doesn't hurt on 2410 1117 */ 1118 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT); 1119 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA); 1120 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA); 1121 1122 if (cmd->data) { 1123 int res = s3cmci_setup_data(host, cmd->data); 1124 1125 host->dcnt++; 1126 1127 if (res) { 1128 dbg(host, dbg_err, "setup data error %d\n", res); 1129 cmd->error = res; 1130 cmd->data->error = res; 1131 1132 mmc_request_done(mmc, mrq); 1133 return; 1134 } 1135 1136 if (s3cmci_host_usedma(host)) 1137 res = s3cmci_prepare_dma(host, cmd->data); 1138 else 1139 res = s3cmci_prepare_pio(host, cmd->data); 1140 1141 if (res) { 1142 dbg(host, dbg_err, "data prepare error %d\n", res); 1143 cmd->error = res; 1144 cmd->data->error = res; 1145 1146 mmc_request_done(mmc, mrq); 1147 return; 1148 } 1149 } 1150 1151 /* Send command */ 1152 s3cmci_send_command(host, cmd); 1153 1154 /* Enable Interrupt */ 1155 s3cmci_enable_irq(host, true); 1156} 1157 1158static int s3cmci_card_present(struct mmc_host *mmc) 1159{ 1160 struct s3cmci_host *host = mmc_priv(mmc); 1161 struct s3c24xx_mci_pdata *pdata = host->pdata; 1162 int ret; 1163 1164 if (pdata->gpio_detect == 0) 1165 return -ENOSYS; 1166 1167 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1; 1168 return ret ^ pdata->detect_invert; 1169} 1170 1171static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq) 1172{ 1173 struct s3cmci_host *host = mmc_priv(mmc); 1174 1175 host->status = "mmc request"; 1176 host->cmd_is_stop = 0; 1177 host->mrq = mrq; 1178 1179 if (s3cmci_card_present(mmc) == 0) { 1180 dbg(host, dbg_err, "%s: no medium present\n", __func__); 1181 host->mrq->cmd->error = -ENOMEDIUM; 1182 mmc_request_done(mmc, mrq); 1183 } else 1184 s3cmci_send_request(mmc); 1185} 1186 1187static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios) 1188{ 1189 u32 mci_psc; 1190 1191 /* Set clock */ 1192 for (mci_psc = 0; mci_psc < 255; mci_psc++) { 1193 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1)); 1194 1195 if (host->real_rate <= ios->clock) 1196 break; 1197 } 1198 1199 if (mci_psc > 255) 1200 mci_psc = 255; 1201 1202 host->prescaler = mci_psc; 1203 writel(host->prescaler, host->base + S3C2410_SDIPRE); 1204 1205 /* If requested clock is 0, real_rate will be 0, too */ 1206 if (ios->clock == 0) 1207 host->real_rate = 0; 1208} 1209 1210static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1211{ 1212 struct s3cmci_host *host = mmc_priv(mmc); 1213 u32 mci_con; 1214 1215 /* Set the power state */ 1216 1217 mci_con = readl(host->base + S3C2410_SDICON); 1218 1219 switch (ios->power_mode) { 1220 case MMC_POWER_ON: 1221 case MMC_POWER_UP: 1222 s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK); 1223 s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD); 1224 s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0); 1225 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); 1226 s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2); 1227 s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3); 1228 1229 if (host->pdata->set_power) 1230 host->pdata->set_power(ios->power_mode, ios->vdd); 1231 1232 if (!host->is2440) 1233 mci_con |= S3C2410_SDICON_FIFORESET; 1234 1235 break; 1236 1237 case MMC_POWER_OFF: 1238 default: 1239 gpio_direction_output(S3C2410_GPE(5), 0); 1240 1241 if (host->is2440) 1242 mci_con |= S3C2440_SDICON_SDRESET; 1243 1244 if (host->pdata->set_power) 1245 host->pdata->set_power(ios->power_mode, ios->vdd); 1246 1247 break; 1248 } 1249 1250 s3cmci_set_clk(host, ios); 1251 1252 /* Set CLOCK_ENABLE */ 1253 if (ios->clock) 1254 mci_con |= S3C2410_SDICON_CLOCKTYPE; 1255 else 1256 mci_con &= ~S3C2410_SDICON_CLOCKTYPE; 1257 1258 writel(mci_con, host->base + S3C2410_SDICON); 1259 1260 if ((ios->power_mode == MMC_POWER_ON) || 1261 (ios->power_mode == MMC_POWER_UP)) { 1262 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n", 1263 host->real_rate/1000, ios->clock/1000); 1264 } else { 1265 dbg(host, dbg_conf, "powered down.\n"); 1266 } 1267 1268 host->bus_width = ios->bus_width; 1269} 1270 1271static void s3cmci_reset(struct s3cmci_host *host) 1272{ 1273 u32 con = readl(host->base + S3C2410_SDICON); 1274 1275 con |= S3C2440_SDICON_SDRESET; 1276 writel(con, host->base + S3C2410_SDICON); 1277} 1278 1279static int s3cmci_get_ro(struct mmc_host *mmc) 1280{ 1281 struct s3cmci_host *host = mmc_priv(mmc); 1282 struct s3c24xx_mci_pdata *pdata = host->pdata; 1283 int ret; 1284 1285 if (pdata->gpio_wprotect == 0) 1286 return 0; 1287 1288 ret = s3c2410_gpio_getpin(pdata->gpio_wprotect); 1289 1290 if (pdata->wprotect_invert) 1291 ret = !ret; 1292 1293 return ret; 1294} 1295 1296static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 1297{ 1298 struct s3cmci_host *host = mmc_priv(mmc); 1299 unsigned long flags; 1300 u32 con; 1301 1302 local_irq_save(flags); 1303 1304 con = readl(host->base + S3C2410_SDICON); 1305 host->sdio_irqen = enable; 1306 1307 if (enable == host->sdio_irqen) 1308 goto same_state; 1309 1310 if (enable) { 1311 con |= S3C2410_SDICON_SDIOIRQ; 1312 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); 1313 1314 if (!host->irq_state && !host->irq_disabled) { 1315 host->irq_state = true; 1316 enable_irq(host->irq); 1317 } 1318 } else { 1319 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ); 1320 con &= ~S3C2410_SDICON_SDIOIRQ; 1321 1322 if (!host->irq_enabled && host->irq_state) { 1323 disable_irq_nosync(host->irq); 1324 host->irq_state = false; 1325 } 1326 } 1327 1328 writel(con, host->base + S3C2410_SDICON); 1329 1330 same_state: 1331 local_irq_restore(flags); 1332 1333 s3cmci_check_sdio_irq(host); 1334} 1335 1336static struct mmc_host_ops s3cmci_ops = { 1337 .request = s3cmci_request, 1338 .set_ios = s3cmci_set_ios, 1339 .get_ro = s3cmci_get_ro, 1340 .get_cd = s3cmci_card_present, 1341 .enable_sdio_irq = s3cmci_enable_sdio_irq, 1342}; 1343 1344static struct s3c24xx_mci_pdata s3cmci_def_pdata = { 1345 /* This is currently here to avoid a number of if (host->pdata) 1346 * checks. Any zero fields to ensure reaonable defaults are picked. */ 1347}; 1348 1349#ifdef CONFIG_CPU_FREQ 1350 1351static int s3cmci_cpufreq_transition(struct notifier_block *nb, 1352 unsigned long val, void *data) 1353{ 1354 struct s3cmci_host *host; 1355 struct mmc_host *mmc; 1356 unsigned long newclk; 1357 unsigned long flags; 1358 1359 host = container_of(nb, struct s3cmci_host, freq_transition); 1360 newclk = clk_get_rate(host->clk); 1361 mmc = host->mmc; 1362 1363 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) || 1364 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) { 1365 spin_lock_irqsave(&mmc->lock, flags); 1366 1367 host->clk_rate = newclk; 1368 1369 if (mmc->ios.power_mode != MMC_POWER_OFF && 1370 mmc->ios.clock != 0) 1371 s3cmci_set_clk(host, &mmc->ios); 1372 1373 spin_unlock_irqrestore(&mmc->lock, flags); 1374 } 1375 1376 return 0; 1377} 1378 1379static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) 1380{ 1381 host->freq_transition.notifier_call = s3cmci_cpufreq_transition; 1382 1383 return cpufreq_register_notifier(&host->freq_transition, 1384 CPUFREQ_TRANSITION_NOTIFIER); 1385} 1386 1387static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) 1388{ 1389 cpufreq_unregister_notifier(&host->freq_transition, 1390 CPUFREQ_TRANSITION_NOTIFIER); 1391} 1392 1393#else 1394static inline int s3cmci_cpufreq_register(struct s3cmci_host *host) 1395{ 1396 return 0; 1397} 1398 1399static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host) 1400{ 1401} 1402#endif 1403 1404 1405#ifdef CONFIG_DEBUG_FS 1406 1407static int s3cmci_state_show(struct seq_file *seq, void *v) 1408{ 1409 struct s3cmci_host *host = seq->private; 1410 1411 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base); 1412 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate); 1413 seq_printf(seq, "Prescale = %d\n", host->prescaler); 1414 seq_printf(seq, "is2440 = %d\n", host->is2440); 1415 seq_printf(seq, "IRQ = %d\n", host->irq); 1416 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled); 1417 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled); 1418 seq_printf(seq, "IRQ state = %d\n", host->irq_state); 1419 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd); 1420 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host)); 1421 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk); 1422 seq_printf(seq, "SDIDATA at %d\n", host->sdidata); 1423 1424 return 0; 1425} 1426 1427static int s3cmci_state_open(struct inode *inode, struct file *file) 1428{ 1429 return single_open(file, s3cmci_state_show, inode->i_private); 1430} 1431 1432static const struct file_operations s3cmci_fops_state = { 1433 .owner = THIS_MODULE, 1434 .open = s3cmci_state_open, 1435 .read = seq_read, 1436 .llseek = seq_lseek, 1437 .release = single_release, 1438}; 1439 1440#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r } 1441 1442struct s3cmci_reg { 1443 unsigned short addr; 1444 unsigned char *name; 1445} debug_regs[] = { 1446 DBG_REG(CON), 1447 DBG_REG(PRE), 1448 DBG_REG(CMDARG), 1449 DBG_REG(CMDCON), 1450 DBG_REG(CMDSTAT), 1451 DBG_REG(RSP0), 1452 DBG_REG(RSP1), 1453 DBG_REG(RSP2), 1454 DBG_REG(RSP3), 1455 DBG_REG(TIMER), 1456 DBG_REG(BSIZE), 1457 DBG_REG(DCON), 1458 DBG_REG(DCNT), 1459 DBG_REG(DSTA), 1460 DBG_REG(FSTA), 1461 {} 1462}; 1463 1464static int s3cmci_regs_show(struct seq_file *seq, void *v) 1465{ 1466 struct s3cmci_host *host = seq->private; 1467 struct s3cmci_reg *rptr = debug_regs; 1468 1469 for (; rptr->name; rptr++) 1470 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name, 1471 readl(host->base + rptr->addr)); 1472 1473 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk)); 1474 1475 return 0; 1476} 1477 1478static int s3cmci_regs_open(struct inode *inode, struct file *file) 1479{ 1480 return single_open(file, s3cmci_regs_show, inode->i_private); 1481} 1482 1483static const struct file_operations s3cmci_fops_regs = { 1484 .owner = THIS_MODULE, 1485 .open = s3cmci_regs_open, 1486 .read = seq_read, 1487 .llseek = seq_lseek, 1488 .release = single_release, 1489}; 1490 1491static void s3cmci_debugfs_attach(struct s3cmci_host *host) 1492{ 1493 struct device *dev = &host->pdev->dev; 1494 1495 host->debug_root = debugfs_create_dir(dev_name(dev), NULL); 1496 if (IS_ERR(host->debug_root)) { 1497 dev_err(dev, "failed to create debugfs root\n"); 1498 return; 1499 } 1500 1501 host->debug_state = debugfs_create_file("state", 0444, 1502 host->debug_root, host, 1503 &s3cmci_fops_state); 1504 1505 if (IS_ERR(host->debug_state)) 1506 dev_err(dev, "failed to create debug state file\n"); 1507 1508 host->debug_regs = debugfs_create_file("regs", 0444, 1509 host->debug_root, host, 1510 &s3cmci_fops_regs); 1511 1512 if (IS_ERR(host->debug_regs)) 1513 dev_err(dev, "failed to create debug regs file\n"); 1514} 1515 1516static void s3cmci_debugfs_remove(struct s3cmci_host *host) 1517{ 1518 debugfs_remove(host->debug_regs); 1519 debugfs_remove(host->debug_state); 1520 debugfs_remove(host->debug_root); 1521} 1522 1523#else 1524static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { } 1525static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { } 1526 1527#endif /* CONFIG_DEBUG_FS */ 1528 1529static int __devinit s3cmci_probe(struct platform_device *pdev) 1530{ 1531 struct s3cmci_host *host; 1532 struct mmc_host *mmc; 1533 int ret; 1534 int is2440; 1535 int i; 1536 1537 is2440 = platform_get_device_id(pdev)->driver_data; 1538 1539 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev); 1540 if (!mmc) { 1541 ret = -ENOMEM; 1542 goto probe_out; 1543 } 1544 1545 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) { 1546 ret = gpio_request(i, dev_name(&pdev->dev)); 1547 if (ret) { 1548 dev_err(&pdev->dev, "failed to get gpio %d\n", i); 1549 1550 for (i--; i >= S3C2410_GPE(5); i--) 1551 gpio_free(i); 1552 1553 goto probe_free_host; 1554 } 1555 } 1556 1557 host = mmc_priv(mmc); 1558 host->mmc = mmc; 1559 host->pdev = pdev; 1560 host->is2440 = is2440; 1561 1562 host->pdata = pdev->dev.platform_data; 1563 if (!host->pdata) { 1564 pdev->dev.platform_data = &s3cmci_def_pdata; 1565 host->pdata = &s3cmci_def_pdata; 1566 } 1567 1568 spin_lock_init(&host->complete_lock); 1569 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host); 1570 1571 if (is2440) { 1572 host->sdiimsk = S3C2440_SDIIMSK; 1573 host->sdidata = S3C2440_SDIDATA; 1574 host->clk_div = 1; 1575 } else { 1576 host->sdiimsk = S3C2410_SDIIMSK; 1577 host->sdidata = S3C2410_SDIDATA; 1578 host->clk_div = 2; 1579 } 1580 1581 host->complete_what = COMPLETION_NONE; 1582 host->pio_active = XFER_NONE; 1583 1584 host->dma = S3CMCI_DMA; 1585 1586#ifdef CONFIG_MMC_S3C_PIODMA 1587 host->dodma = host->pdata->dma; 1588#endif 1589 1590 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1591 if (!host->mem) { 1592 dev_err(&pdev->dev, 1593 "failed to get io memory region resouce.\n"); 1594 1595 ret = -ENOENT; 1596 goto probe_free_gpio; 1597 } 1598 1599 host->mem = request_mem_region(host->mem->start, 1600 resource_size(host->mem), pdev->name); 1601 1602 if (!host->mem) { 1603 dev_err(&pdev->dev, "failed to request io memory region.\n"); 1604 ret = -ENOENT; 1605 goto probe_free_gpio; 1606 } 1607 1608 host->base = ioremap(host->mem->start, resource_size(host->mem)); 1609 if (!host->base) { 1610 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n"); 1611 ret = -EINVAL; 1612 goto probe_free_mem_region; 1613 } 1614 1615 host->irq = platform_get_irq(pdev, 0); 1616 if (host->irq == 0) { 1617 dev_err(&pdev->dev, "failed to get interrupt resouce.\n"); 1618 ret = -EINVAL; 1619 goto probe_iounmap; 1620 } 1621 1622 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) { 1623 dev_err(&pdev->dev, "failed to request mci interrupt.\n"); 1624 ret = -ENOENT; 1625 goto probe_iounmap; 1626 } 1627 1628 /* We get spurious interrupts even when we have set the IMSK 1629 * register to ignore everything, so use disable_irq() to make 1630 * ensure we don't lock the system with un-serviceable requests. */ 1631 1632 disable_irq(host->irq); 1633 host->irq_state = false; 1634 1635 if (host->pdata->gpio_detect) { 1636 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect"); 1637 if (ret) { 1638 dev_err(&pdev->dev, "failed to get detect gpio\n"); 1639 goto probe_free_irq; 1640 } 1641 } 1642 1643 host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect); 1644 1645 if (host->irq_cd >= 0) { 1646 if (request_irq(host->irq_cd, s3cmci_irq_cd, 1647 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, 1648 DRIVER_NAME, host)) { 1649 dev_err(&pdev->dev, "can't get card detect irq.\n"); 1650 ret = -ENOENT; 1651 goto probe_free_gpio_cd; 1652 } 1653 } else { 1654 dev_warn(&pdev->dev, "host detect has no irq available\n"); 1655 gpio_direction_input(host->pdata->gpio_detect); 1656 } 1657 1658 if (host->pdata->gpio_wprotect) { 1659 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp"); 1660 if (ret) { 1661 dev_err(&pdev->dev, "failed to get writeprotect\n"); 1662 goto probe_free_irq_cd; 1663 } 1664 1665 gpio_direction_input(host->pdata->gpio_wprotect); 1666 } 1667 1668 if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) { 1669 dev_err(&pdev->dev, "unable to get DMA channel.\n"); 1670 ret = -EBUSY; 1671 goto probe_free_gpio_wp; 1672 } 1673 1674 host->clk = clk_get(&pdev->dev, "sdi"); 1675 if (IS_ERR(host->clk)) { 1676 dev_err(&pdev->dev, "failed to find clock source.\n"); 1677 ret = PTR_ERR(host->clk); 1678 host->clk = NULL; 1679 goto probe_free_host; 1680 } 1681 1682 ret = clk_enable(host->clk); 1683 if (ret) { 1684 dev_err(&pdev->dev, "failed to enable clock source.\n"); 1685 goto clk_free; 1686 } 1687 1688 host->clk_rate = clk_get_rate(host->clk); 1689 1690 mmc->ops = &s3cmci_ops; 1691 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1692 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1693 mmc->f_min = host->clk_rate / (host->clk_div * 256); 1694 mmc->f_max = host->clk_rate / host->clk_div; 1695 1696 if (host->pdata->ocr_avail) 1697 mmc->ocr_avail = host->pdata->ocr_avail; 1698 1699 mmc->max_blk_count = 4095; 1700 mmc->max_blk_size = 4095; 1701 mmc->max_req_size = 4095 * 512; 1702 mmc->max_seg_size = mmc->max_req_size; 1703 1704 mmc->max_phys_segs = 128; 1705 mmc->max_hw_segs = 128; 1706 1707 dbg(host, dbg_debug, 1708 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n", 1709 (host->is2440?"2440":""), 1710 host->base, host->irq, host->irq_cd, host->dma); 1711 1712 ret = s3cmci_cpufreq_register(host); 1713 if (ret) { 1714 dev_err(&pdev->dev, "failed to register cpufreq\n"); 1715 goto free_dmabuf; 1716 } 1717 1718 ret = mmc_add_host(mmc); 1719 if (ret) { 1720 dev_err(&pdev->dev, "failed to add mmc host.\n"); 1721 goto free_cpufreq; 1722 } 1723 1724 s3cmci_debugfs_attach(host); 1725 1726 platform_set_drvdata(pdev, mmc); 1727 dev_info(&pdev->dev, "%s - using %s\n", mmc_hostname(mmc), 1728 s3cmci_host_usedma(host) ? "dma" : "pio"); 1729 1730 return 0; 1731 1732 free_cpufreq: 1733 s3cmci_cpufreq_deregister(host); 1734 1735 free_dmabuf: 1736 clk_disable(host->clk); 1737 1738 clk_free: 1739 clk_put(host->clk); 1740 1741 probe_free_gpio_wp: 1742 if (host->pdata->gpio_wprotect) 1743 gpio_free(host->pdata->gpio_wprotect); 1744 1745 probe_free_gpio_cd: 1746 if (host->pdata->gpio_detect) 1747 gpio_free(host->pdata->gpio_detect); 1748 1749 probe_free_irq_cd: 1750 if (host->irq_cd >= 0) 1751 free_irq(host->irq_cd, host); 1752 1753 probe_free_irq: 1754 free_irq(host->irq, host); 1755 1756 probe_iounmap: 1757 iounmap(host->base); 1758 1759 probe_free_mem_region: 1760 release_mem_region(host->mem->start, resource_size(host->mem)); 1761 1762 probe_free_gpio: 1763 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) 1764 gpio_free(i); 1765 1766 probe_free_host: 1767 mmc_free_host(mmc); 1768 1769 probe_out: 1770 return ret; 1771} 1772 1773static void s3cmci_shutdown(struct platform_device *pdev) 1774{ 1775 struct mmc_host *mmc = platform_get_drvdata(pdev); 1776 struct s3cmci_host *host = mmc_priv(mmc); 1777 1778 if (host->irq_cd >= 0) 1779 free_irq(host->irq_cd, host); 1780 1781 s3cmci_debugfs_remove(host); 1782 s3cmci_cpufreq_deregister(host); 1783 mmc_remove_host(mmc); 1784 clk_disable(host->clk); 1785} 1786 1787static int __devexit s3cmci_remove(struct platform_device *pdev) 1788{ 1789 struct mmc_host *mmc = platform_get_drvdata(pdev); 1790 struct s3cmci_host *host = mmc_priv(mmc); 1791 struct s3c24xx_mci_pdata *pd = host->pdata; 1792 int i; 1793 1794 s3cmci_shutdown(pdev); 1795 1796 clk_put(host->clk); 1797 1798 tasklet_disable(&host->pio_tasklet); 1799 s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client); 1800 1801 free_irq(host->irq, host); 1802 1803 if (pd->gpio_wprotect) 1804 gpio_free(pd->gpio_wprotect); 1805 1806 if (pd->gpio_detect) 1807 gpio_free(pd->gpio_detect); 1808 1809 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) 1810 gpio_free(i); 1811 1812 1813 iounmap(host->base); 1814 release_mem_region(host->mem->start, resource_size(host->mem)); 1815 1816 mmc_free_host(mmc); 1817 return 0; 1818} 1819 1820static struct platform_device_id s3cmci_driver_ids[] = { 1821 { 1822 .name = "s3c2410-sdi", 1823 .driver_data = 0, 1824 }, { 1825 .name = "s3c2412-sdi", 1826 .driver_data = 1, 1827 }, { 1828 .name = "s3c2440-sdi", 1829 .driver_data = 1, 1830 }, 1831 { } 1832}; 1833 1834MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids); 1835 1836 1837#ifdef CONFIG_PM 1838 1839static int s3cmci_suspend(struct device *dev) 1840{ 1841 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev)); 1842 struct pm_message event = { PM_EVENT_SUSPEND }; 1843 1844 return mmc_suspend_host(mmc, event); 1845} 1846 1847static int s3cmci_resume(struct device *dev) 1848{ 1849 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev)); 1850 1851 return mmc_resume_host(mmc); 1852} 1853 1854static struct dev_pm_ops s3cmci_pm = { 1855 .suspend = s3cmci_suspend, 1856 .resume = s3cmci_resume, 1857}; 1858 1859#define s3cmci_pm_ops &s3cmci_pm 1860#else /* CONFIG_PM */ 1861#define s3cmci_pm_ops NULL 1862#endif /* CONFIG_PM */ 1863 1864 1865static struct platform_driver s3cmci_driver = { 1866 .driver = { 1867 .name = "s3c-sdi", 1868 .owner = THIS_MODULE, 1869 .pm = s3cmci_pm_ops, 1870 }, 1871 .id_table = s3cmci_driver_ids, 1872 .probe = s3cmci_probe, 1873 .remove = __devexit_p(s3cmci_remove), 1874 .shutdown = s3cmci_shutdown, 1875}; 1876 1877static int __init s3cmci_init(void) 1878{ 1879 return platform_driver_register(&s3cmci_driver); 1880} 1881 1882static void __exit s3cmci_exit(void) 1883{ 1884 platform_driver_unregister(&s3cmci_driver); 1885} 1886 1887module_init(s3cmci_init); 1888module_exit(s3cmci_exit); 1889 1890MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver"); 1891MODULE_LICENSE("GPL v2"); 1892MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>"); 1893