sdhci-s3c.c revision 3beef62479bef4309a220f7ca5415d9a66c0b0cb
1/* linux/drivers/mmc/host/sdhci-s3c.c 2 * 3 * Copyright 2008 Openmoko Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * SDHCI (HSMMC) support for Samsung SoC 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include <linux/delay.h> 16#include <linux/dma-mapping.h> 17#include <linux/platform_device.h> 18#include <linux/platform_data/mmc-sdhci-s3c.h> 19#include <linux/slab.h> 20#include <linux/clk.h> 21#include <linux/io.h> 22#include <linux/gpio.h> 23#include <linux/module.h> 24#include <linux/of.h> 25#include <linux/of_gpio.h> 26#include <linux/pm.h> 27#include <linux/pm_runtime.h> 28 29#include <linux/mmc/host.h> 30 31#include "sdhci-s3c-regs.h" 32#include "sdhci.h" 33 34#define MAX_BUS_CLK (4) 35 36/** 37 * struct sdhci_s3c - S3C SDHCI instance 38 * @host: The SDHCI host created 39 * @pdev: The platform device we where created from. 40 * @ioarea: The resource created when we claimed the IO area. 41 * @pdata: The platform data for this controller. 42 * @cur_clk: The index of the current bus clock. 43 * @clk_io: The clock for the internal bus interface. 44 * @clk_bus: The clocks that are available for the SD/MMC bus clock. 45 */ 46struct sdhci_s3c { 47 struct sdhci_host *host; 48 struct platform_device *pdev; 49 struct resource *ioarea; 50 struct s3c_sdhci_platdata *pdata; 51 int cur_clk; 52 int ext_cd_irq; 53 int ext_cd_gpio; 54 55 struct clk *clk_io; 56 struct clk *clk_bus[MAX_BUS_CLK]; 57 unsigned long clk_rates[MAX_BUS_CLK]; 58}; 59 60/** 61 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data 62 * @sdhci_quirks: sdhci host specific quirks. 63 * 64 * Specifies platform specific configuration of sdhci controller. 65 * Note: A structure for driver specific platform data is used for future 66 * expansion of its usage. 67 */ 68struct sdhci_s3c_drv_data { 69 unsigned int sdhci_quirks; 70}; 71 72static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) 73{ 74 return sdhci_priv(host); 75} 76 77/** 78 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. 79 * @host: The SDHCI host instance. 80 * 81 * Callback to return the maximum clock rate acheivable by the controller. 82*/ 83static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) 84{ 85 struct sdhci_s3c *ourhost = to_s3c(host); 86 unsigned long rate, max = 0; 87 int src; 88 89 for (src = 0; src < MAX_BUS_CLK; src++) { 90 rate = ourhost->clk_rates[src]; 91 if (rate > max) 92 max = rate; 93 } 94 95 return max; 96} 97 98/** 99 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting 100 * @ourhost: Our SDHCI instance. 101 * @src: The source clock index. 102 * @wanted: The clock frequency wanted. 103 */ 104static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, 105 unsigned int src, 106 unsigned int wanted) 107{ 108 unsigned long rate; 109 struct clk *clksrc = ourhost->clk_bus[src]; 110 int shift; 111 112 if (IS_ERR(clksrc)) 113 return UINT_MAX; 114 115 /* 116 * If controller uses a non-standard clock division, find the best clock 117 * speed possible with selected clock source and skip the division. 118 */ 119 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 120 rate = clk_round_rate(clksrc, wanted); 121 return wanted - rate; 122 } 123 124 rate = ourhost->clk_rates[src]; 125 126 for (shift = 0; shift <= 8; ++shift) { 127 if ((rate >> shift) <= wanted) 128 break; 129 } 130 131 if (shift > 8) { 132 dev_dbg(&ourhost->pdev->dev, 133 "clk %d: rate %ld, min rate %lu > wanted %u\n", 134 src, rate, rate / 256, wanted); 135 return UINT_MAX; 136 } 137 138 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", 139 src, rate, wanted, rate >> shift); 140 141 return wanted - (rate >> shift); 142} 143 144/** 145 * sdhci_s3c_set_clock - callback on clock change 146 * @host: The SDHCI host being changed 147 * @clock: The clock rate being requested. 148 * 149 * When the card's clock is going to be changed, look at the new frequency 150 * and find the best clock source to go with it. 151*/ 152static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) 153{ 154 struct sdhci_s3c *ourhost = to_s3c(host); 155 unsigned int best = UINT_MAX; 156 unsigned int delta; 157 int best_src = 0; 158 int src; 159 u32 ctrl; 160 161 /* don't bother if the clock is going off. */ 162 if (clock == 0) 163 return; 164 165 for (src = 0; src < MAX_BUS_CLK; src++) { 166 delta = sdhci_s3c_consider_clock(ourhost, src, clock); 167 if (delta < best) { 168 best = delta; 169 best_src = src; 170 } 171 } 172 173 dev_dbg(&ourhost->pdev->dev, 174 "selected source %d, clock %d, delta %d\n", 175 best_src, clock, best); 176 177 /* select the new clock source */ 178 if (ourhost->cur_clk != best_src) { 179 struct clk *clk = ourhost->clk_bus[best_src]; 180 181 clk_prepare_enable(clk); 182 if (ourhost->cur_clk >= 0) 183 clk_disable_unprepare( 184 ourhost->clk_bus[ourhost->cur_clk]); 185 186 ourhost->cur_clk = best_src; 187 host->max_clk = ourhost->clk_rates[best_src]; 188 } 189 190 /* turn clock off to card before changing clock source */ 191 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 192 193 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 194 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 195 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 196 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 197 198 /* reprogram default hardware configuration */ 199 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, 200 host->ioaddr + S3C64XX_SDHCI_CONTROL4); 201 202 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 203 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | 204 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | 205 S3C_SDHCI_CTRL2_ENFBCLKRX | 206 S3C_SDHCI_CTRL2_DFCNT_NONE | 207 S3C_SDHCI_CTRL2_ENCLKOUTHOLD); 208 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 209 210 /* reconfigure the controller for new clock rate */ 211 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); 212 if (clock < 25 * 1000000) 213 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); 214 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); 215} 216 217/** 218 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value 219 * @host: The SDHCI host being queried 220 * 221 * To init mmc host properly a minimal clock value is needed. For high system 222 * bus clock's values the standard formula gives values out of allowed range. 223 * The clock still can be set to lower values, if clock source other then 224 * system bus is selected. 225*/ 226static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) 227{ 228 struct sdhci_s3c *ourhost = to_s3c(host); 229 unsigned long rate, min = ULONG_MAX; 230 int src; 231 232 for (src = 0; src < MAX_BUS_CLK; src++) { 233 rate = ourhost->clk_rates[src] / 256; 234 if (!rate) 235 continue; 236 if (rate < min) 237 min = rate; 238 } 239 240 return min; 241} 242 243/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ 244static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) 245{ 246 struct sdhci_s3c *ourhost = to_s3c(host); 247 unsigned long rate, max = 0; 248 int src; 249 250 for (src = 0; src < MAX_BUS_CLK; src++) { 251 struct clk *clk; 252 253 clk = ourhost->clk_bus[src]; 254 if (IS_ERR(clk)) 255 continue; 256 257 rate = clk_round_rate(clk, ULONG_MAX); 258 if (rate > max) 259 max = rate; 260 } 261 262 return max; 263} 264 265/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ 266static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) 267{ 268 struct sdhci_s3c *ourhost = to_s3c(host); 269 unsigned long rate, min = ULONG_MAX; 270 int src; 271 272 for (src = 0; src < MAX_BUS_CLK; src++) { 273 struct clk *clk; 274 275 clk = ourhost->clk_bus[src]; 276 if (IS_ERR(clk)) 277 continue; 278 279 rate = clk_round_rate(clk, 0); 280 if (rate < min) 281 min = rate; 282 } 283 284 return min; 285} 286 287/* sdhci_cmu_set_clock - callback on clock change.*/ 288static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) 289{ 290 struct sdhci_s3c *ourhost = to_s3c(host); 291 struct device *dev = &ourhost->pdev->dev; 292 unsigned long timeout; 293 u16 clk = 0; 294 295 /* If the clock is going off, set to 0 at clock control register */ 296 if (clock == 0) { 297 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 298 host->clock = clock; 299 return; 300 } 301 302 sdhci_s3c_set_clock(host, clock); 303 304 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); 305 306 host->clock = clock; 307 308 clk = SDHCI_CLOCK_INT_EN; 309 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 310 311 /* Wait max 20 ms */ 312 timeout = 20; 313 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 314 & SDHCI_CLOCK_INT_STABLE)) { 315 if (timeout == 0) { 316 dev_err(dev, "%s: Internal clock never stabilised.\n", 317 mmc_hostname(host->mmc)); 318 return; 319 } 320 timeout--; 321 mdelay(1); 322 } 323 324 clk |= SDHCI_CLOCK_CARD_EN; 325 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 326} 327 328/** 329 * sdhci_s3c_platform_bus_width - support 8bit buswidth 330 * @host: The SDHCI host being queried 331 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested 332 * 333 * We have 8-bit width support but is not a v3 controller. 334 * So we add platform_bus_width() and support 8bit width. 335 */ 336static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width) 337{ 338 u8 ctrl; 339 340 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 341 342 switch (width) { 343 case MMC_BUS_WIDTH_8: 344 ctrl |= SDHCI_CTRL_8BITBUS; 345 ctrl &= ~SDHCI_CTRL_4BITBUS; 346 break; 347 case MMC_BUS_WIDTH_4: 348 ctrl |= SDHCI_CTRL_4BITBUS; 349 ctrl &= ~SDHCI_CTRL_8BITBUS; 350 break; 351 default: 352 ctrl &= ~SDHCI_CTRL_4BITBUS; 353 ctrl &= ~SDHCI_CTRL_8BITBUS; 354 break; 355 } 356 357 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 358 359 return 0; 360} 361 362static struct sdhci_ops sdhci_s3c_ops = { 363 .get_max_clock = sdhci_s3c_get_max_clk, 364 .set_clock = sdhci_s3c_set_clock, 365 .get_min_clock = sdhci_s3c_get_min_clock, 366 .platform_bus_width = sdhci_s3c_platform_bus_width, 367}; 368 369static void sdhci_s3c_notify_change(struct platform_device *dev, int state) 370{ 371 struct sdhci_host *host = platform_get_drvdata(dev); 372#ifdef CONFIG_PM_RUNTIME 373 struct sdhci_s3c *sc = sdhci_priv(host); 374#endif 375 unsigned long flags; 376 377 if (host) { 378 spin_lock_irqsave(&host->lock, flags); 379 if (state) { 380 dev_dbg(&dev->dev, "card inserted.\n"); 381#ifdef CONFIG_PM_RUNTIME 382 clk_prepare_enable(sc->clk_io); 383#endif 384 host->flags &= ~SDHCI_DEVICE_DEAD; 385 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 386 } else { 387 dev_dbg(&dev->dev, "card removed.\n"); 388 host->flags |= SDHCI_DEVICE_DEAD; 389 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 390#ifdef CONFIG_PM_RUNTIME 391 clk_disable_unprepare(sc->clk_io); 392#endif 393 } 394 tasklet_schedule(&host->card_tasklet); 395 spin_unlock_irqrestore(&host->lock, flags); 396 } 397} 398 399static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) 400{ 401 struct sdhci_s3c *sc = dev_id; 402 int status = gpio_get_value(sc->ext_cd_gpio); 403 if (sc->pdata->ext_cd_gpio_invert) 404 status = !status; 405 sdhci_s3c_notify_change(sc->pdev, status); 406 return IRQ_HANDLED; 407} 408 409static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) 410{ 411 struct s3c_sdhci_platdata *pdata = sc->pdata; 412 struct device *dev = &sc->pdev->dev; 413 414 if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { 415 sc->ext_cd_gpio = pdata->ext_cd_gpio; 416 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); 417 if (sc->ext_cd_irq && 418 request_threaded_irq(sc->ext_cd_irq, NULL, 419 sdhci_s3c_gpio_card_detect_thread, 420 IRQF_TRIGGER_RISING | 421 IRQF_TRIGGER_FALLING | 422 IRQF_ONESHOT, 423 dev_name(dev), sc) == 0) { 424 int status = gpio_get_value(sc->ext_cd_gpio); 425 if (pdata->ext_cd_gpio_invert) 426 status = !status; 427 sdhci_s3c_notify_change(sc->pdev, status); 428 } else { 429 dev_warn(dev, "cannot request irq for card detect\n"); 430 sc->ext_cd_irq = 0; 431 } 432 } else { 433 dev_err(dev, "cannot request gpio for card detect\n"); 434 } 435} 436 437#ifdef CONFIG_OF 438static int sdhci_s3c_parse_dt(struct device *dev, 439 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 440{ 441 struct device_node *node = dev->of_node; 442 struct sdhci_s3c *ourhost = to_s3c(host); 443 u32 max_width; 444 int gpio; 445 446 /* if the bus-width property is not specified, assume width as 1 */ 447 if (of_property_read_u32(node, "bus-width", &max_width)) 448 max_width = 1; 449 pdata->max_width = max_width; 450 451 /* get the card detection method */ 452 if (of_get_property(node, "broken-cd", NULL)) { 453 pdata->cd_type = S3C_SDHCI_CD_NONE; 454 return 0; 455 } 456 457 if (of_get_property(node, "non-removable", NULL)) { 458 pdata->cd_type = S3C_SDHCI_CD_PERMANENT; 459 return 0; 460 } 461 462 gpio = of_get_named_gpio(node, "cd-gpios", 0); 463 if (gpio_is_valid(gpio)) { 464 pdata->cd_type = S3C_SDHCI_CD_GPIO; 465 pdata->ext_cd_gpio = gpio; 466 ourhost->ext_cd_gpio = -1; 467 if (of_get_property(node, "cd-inverted", NULL)) 468 pdata->ext_cd_gpio_invert = 1; 469 return 0; 470 } else if (gpio != -ENOENT) { 471 dev_err(dev, "invalid card detect gpio specified\n"); 472 return -EINVAL; 473 } 474 475 /* assuming internal card detect that will be configured by pinctrl */ 476 pdata->cd_type = S3C_SDHCI_CD_INTERNAL; 477 return 0; 478} 479#else 480static int sdhci_s3c_parse_dt(struct device *dev, 481 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 482{ 483 return -EINVAL; 484} 485#endif 486 487static const struct of_device_id sdhci_s3c_dt_match[]; 488 489static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( 490 struct platform_device *pdev) 491{ 492#ifdef CONFIG_OF 493 if (pdev->dev.of_node) { 494 const struct of_device_id *match; 495 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); 496 return (struct sdhci_s3c_drv_data *)match->data; 497 } 498#endif 499 return (struct sdhci_s3c_drv_data *) 500 platform_get_device_id(pdev)->driver_data; 501} 502 503static int sdhci_s3c_probe(struct platform_device *pdev) 504{ 505 struct s3c_sdhci_platdata *pdata; 506 struct sdhci_s3c_drv_data *drv_data; 507 struct device *dev = &pdev->dev; 508 struct sdhci_host *host; 509 struct sdhci_s3c *sc; 510 struct resource *res; 511 int ret, irq, ptr, clks; 512 513 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 514 dev_err(dev, "no device data specified\n"); 515 return -ENOENT; 516 } 517 518 irq = platform_get_irq(pdev, 0); 519 if (irq < 0) { 520 dev_err(dev, "no irq specified\n"); 521 return irq; 522 } 523 524 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 525 if (IS_ERR(host)) { 526 dev_err(dev, "sdhci_alloc_host() failed\n"); 527 return PTR_ERR(host); 528 } 529 sc = sdhci_priv(host); 530 531 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 532 if (!pdata) { 533 ret = -ENOMEM; 534 goto err_pdata_io_clk; 535 } 536 537 if (pdev->dev.of_node) { 538 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); 539 if (ret) 540 goto err_pdata_io_clk; 541 } else { 542 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 543 sc->ext_cd_gpio = -1; /* invalid gpio number */ 544 } 545 546 drv_data = sdhci_s3c_get_driver_data(pdev); 547 548 sc->host = host; 549 sc->pdev = pdev; 550 sc->pdata = pdata; 551 sc->cur_clk = -1; 552 553 platform_set_drvdata(pdev, host); 554 555 sc->clk_io = devm_clk_get(dev, "hsmmc"); 556 if (IS_ERR(sc->clk_io)) { 557 dev_err(dev, "failed to get io clock\n"); 558 ret = PTR_ERR(sc->clk_io); 559 goto err_pdata_io_clk; 560 } 561 562 /* enable the local io clock and keep it running for the moment. */ 563 clk_prepare_enable(sc->clk_io); 564 565 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 566 char name[14]; 567 568 snprintf(name, 14, "mmc_busclk.%d", ptr); 569 sc->clk_bus[ptr] = devm_clk_get(dev, name); 570 if (IS_ERR(sc->clk_bus[ptr])) 571 continue; 572 573 clks++; 574 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); 575 576 dev_info(dev, "clock source %d: %s (%ld Hz)\n", 577 ptr, name, sc->clk_rates[ptr]); 578 } 579 580 if (clks == 0) { 581 dev_err(dev, "failed to find any bus clocks\n"); 582 ret = -ENOENT; 583 goto err_no_busclks; 584 } 585 586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 587 host->ioaddr = devm_ioremap_resource(&pdev->dev, res); 588 if (IS_ERR(host->ioaddr)) { 589 ret = PTR_ERR(host->ioaddr); 590 goto err_req_regs; 591 } 592 593 /* Ensure we have minimal gpio selected CMD/CLK/Detect */ 594 if (pdata->cfg_gpio) 595 pdata->cfg_gpio(pdev, pdata->max_width); 596 597 host->hw_name = "samsung-hsmmc"; 598 host->ops = &sdhci_s3c_ops; 599 host->quirks = 0; 600 host->quirks2 = 0; 601 host->irq = irq; 602 603 /* Setup quirks for the controller */ 604 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; 605 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 606 if (drv_data) 607 host->quirks |= drv_data->sdhci_quirks; 608 609#ifndef CONFIG_MMC_SDHCI_S3C_DMA 610 611 /* we currently see overruns on errors, so disable the SDMA 612 * support as well. */ 613 host->quirks |= SDHCI_QUIRK_BROKEN_DMA; 614 615#endif /* CONFIG_MMC_SDHCI_S3C_DMA */ 616 617 /* It seems we do not get an DATA transfer complete on non-busy 618 * transfers, not sure if this is a problem with this specific 619 * SDHCI block, or a missing configuration that needs to be set. */ 620 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; 621 622 /* This host supports the Auto CMD12 */ 623 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 624 625 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ 626 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; 627 628 if (pdata->cd_type == S3C_SDHCI_CD_NONE || 629 pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 630 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 631 632 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 633 host->mmc->caps = MMC_CAP_NONREMOVABLE; 634 635 switch (pdata->max_width) { 636 case 8: 637 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 638 case 4: 639 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 640 break; 641 } 642 643 if (pdata->pm_caps) 644 host->mmc->pm_caps |= pdata->pm_caps; 645 646 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | 647 SDHCI_QUIRK_32BIT_DMA_SIZE); 648 649 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 650 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 651 652 /* 653 * If controller does not have internal clock divider, 654 * we can use overriding functions instead of default. 655 */ 656 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 657 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 658 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 659 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 660 } 661 662 /* It supports additional host capabilities if needed */ 663 if (pdata->host_caps) 664 host->mmc->caps |= pdata->host_caps; 665 666 if (pdata->host_caps2) 667 host->mmc->caps2 |= pdata->host_caps2; 668 669 pm_runtime_enable(&pdev->dev); 670 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 671 pm_runtime_use_autosuspend(&pdev->dev); 672 pm_suspend_ignore_children(&pdev->dev, 1); 673 674 ret = sdhci_add_host(host); 675 if (ret) { 676 dev_err(dev, "sdhci_add_host() failed\n"); 677 pm_runtime_forbid(&pdev->dev); 678 pm_runtime_get_noresume(&pdev->dev); 679 goto err_req_regs; 680 } 681 682 /* The following two methods of card detection might call 683 sdhci_s3c_notify_change() immediately, so they can be called 684 only after sdhci_add_host(). Setup errors are ignored. */ 685 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) 686 pdata->ext_cd_init(&sdhci_s3c_notify_change); 687 if (pdata->cd_type == S3C_SDHCI_CD_GPIO && 688 gpio_is_valid(pdata->ext_cd_gpio)) 689 sdhci_s3c_setup_card_detect_gpio(sc); 690 691#ifdef CONFIG_PM_RUNTIME 692 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 693 clk_disable_unprepare(sc->clk_io); 694#endif 695 return 0; 696 697 err_req_regs: 698 err_no_busclks: 699 clk_disable_unprepare(sc->clk_io); 700 701 err_pdata_io_clk: 702 sdhci_free_host(host); 703 704 return ret; 705} 706 707static int sdhci_s3c_remove(struct platform_device *pdev) 708{ 709 struct sdhci_host *host = platform_get_drvdata(pdev); 710 struct sdhci_s3c *sc = sdhci_priv(host); 711 struct s3c_sdhci_platdata *pdata = sc->pdata; 712 713 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) 714 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); 715 716 if (sc->ext_cd_irq) 717 free_irq(sc->ext_cd_irq, sc); 718 719#ifdef CONFIG_PM_RUNTIME 720 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 721 clk_prepare_enable(sc->clk_io); 722#endif 723 sdhci_remove_host(host, 1); 724 725 pm_runtime_dont_use_autosuspend(&pdev->dev); 726 pm_runtime_disable(&pdev->dev); 727 728 clk_disable_unprepare(sc->clk_io); 729 730 sdhci_free_host(host); 731 732 return 0; 733} 734 735#ifdef CONFIG_PM_SLEEP 736static int sdhci_s3c_suspend(struct device *dev) 737{ 738 struct sdhci_host *host = dev_get_drvdata(dev); 739 740 return sdhci_suspend_host(host); 741} 742 743static int sdhci_s3c_resume(struct device *dev) 744{ 745 struct sdhci_host *host = dev_get_drvdata(dev); 746 747 return sdhci_resume_host(host); 748} 749#endif 750 751#ifdef CONFIG_PM_RUNTIME 752static int sdhci_s3c_runtime_suspend(struct device *dev) 753{ 754 struct sdhci_host *host = dev_get_drvdata(dev); 755 struct sdhci_s3c *ourhost = to_s3c(host); 756 struct clk *busclk = ourhost->clk_io; 757 int ret; 758 759 ret = sdhci_runtime_suspend_host(host); 760 761 if (ourhost->cur_clk >= 0) 762 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 763 clk_disable_unprepare(busclk); 764 return ret; 765} 766 767static int sdhci_s3c_runtime_resume(struct device *dev) 768{ 769 struct sdhci_host *host = dev_get_drvdata(dev); 770 struct sdhci_s3c *ourhost = to_s3c(host); 771 struct clk *busclk = ourhost->clk_io; 772 int ret; 773 774 clk_prepare_enable(busclk); 775 if (ourhost->cur_clk >= 0) 776 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); 777 ret = sdhci_runtime_resume_host(host); 778 return ret; 779} 780#endif 781 782#ifdef CONFIG_PM 783static const struct dev_pm_ops sdhci_s3c_pmops = { 784 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 785 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 786 NULL) 787}; 788 789#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) 790 791#else 792#define SDHCI_S3C_PMOPS NULL 793#endif 794 795#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 796static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 797 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, 798}; 799#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) 800#else 801#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) 802#endif 803 804static struct platform_device_id sdhci_s3c_driver_ids[] = { 805 { 806 .name = "s3c-sdhci", 807 .driver_data = (kernel_ulong_t)NULL, 808 }, { 809 .name = "exynos4-sdhci", 810 .driver_data = EXYNOS4_SDHCI_DRV_DATA, 811 }, 812 { } 813}; 814MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); 815 816#ifdef CONFIG_OF 817static const struct of_device_id sdhci_s3c_dt_match[] = { 818 { .compatible = "samsung,s3c6410-sdhci", }, 819 { .compatible = "samsung,exynos4210-sdhci", 820 .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, 821 {}, 822}; 823MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); 824#endif 825 826static struct platform_driver sdhci_s3c_driver = { 827 .probe = sdhci_s3c_probe, 828 .remove = sdhci_s3c_remove, 829 .id_table = sdhci_s3c_driver_ids, 830 .driver = { 831 .owner = THIS_MODULE, 832 .name = "s3c-sdhci", 833 .of_match_table = of_match_ptr(sdhci_s3c_dt_match), 834 .pm = SDHCI_S3C_PMOPS, 835 }, 836}; 837 838module_platform_driver(sdhci_s3c_driver); 839 840MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); 841MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 842MODULE_LICENSE("GPL v2"); 843MODULE_ALIAS("platform:s3c-sdhci"); 844