sdhci-s3c.c revision b1b8fea94f4c71b5503b7e29974635121f44b302
1/* linux/drivers/mmc/host/sdhci-s3c.c 2 * 3 * Copyright 2008 Openmoko Inc. 4 * Copyright 2008 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * http://armlinux.simtec.co.uk/ 7 * 8 * SDHCI (HSMMC) support for Samsung SoC 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include <linux/delay.h> 16#include <linux/dma-mapping.h> 17#include <linux/platform_device.h> 18#include <linux/slab.h> 19#include <linux/clk.h> 20#include <linux/io.h> 21#include <linux/gpio.h> 22#include <linux/module.h> 23#include <linux/of.h> 24#include <linux/of_gpio.h> 25#include <linux/pm.h> 26#include <linux/pm_runtime.h> 27 28#include <linux/mmc/host.h> 29 30#include <plat/sdhci.h> 31#include <plat/regs-sdhci.h> 32 33#include "sdhci.h" 34 35#define MAX_BUS_CLK (4) 36 37/* Number of gpio's used is max data bus width + command and clock lines */ 38#define NUM_GPIOS(x) (x + 2) 39 40/** 41 * struct sdhci_s3c - S3C SDHCI instance 42 * @host: The SDHCI host created 43 * @pdev: The platform device we where created from. 44 * @ioarea: The resource created when we claimed the IO area. 45 * @pdata: The platform data for this controller. 46 * @cur_clk: The index of the current bus clock. 47 * @gpios: List of gpio numbers parsed from device tree. 48 * @clk_io: The clock for the internal bus interface. 49 * @clk_bus: The clocks that are available for the SD/MMC bus clock. 50 */ 51struct sdhci_s3c { 52 struct sdhci_host *host; 53 struct platform_device *pdev; 54 struct resource *ioarea; 55 struct s3c_sdhci_platdata *pdata; 56 unsigned int cur_clk; 57 int ext_cd_irq; 58 int ext_cd_gpio; 59 int *gpios; 60 61 struct clk *clk_io; 62 struct clk *clk_bus[MAX_BUS_CLK]; 63}; 64 65/** 66 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data 67 * @sdhci_quirks: sdhci host specific quirks. 68 * 69 * Specifies platform specific configuration of sdhci controller. 70 * Note: A structure for driver specific platform data is used for future 71 * expansion of its usage. 72 */ 73struct sdhci_s3c_drv_data { 74 unsigned int sdhci_quirks; 75}; 76 77static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) 78{ 79 return sdhci_priv(host); 80} 81 82/** 83 * get_curclk - convert ctrl2 register to clock source number 84 * @ctrl2: Control2 register value. 85 */ 86static u32 get_curclk(u32 ctrl2) 87{ 88 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; 89 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 90 91 return ctrl2; 92} 93 94static void sdhci_s3c_check_sclk(struct sdhci_host *host) 95{ 96 struct sdhci_s3c *ourhost = to_s3c(host); 97 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 98 99 if (get_curclk(tmp) != ourhost->cur_clk) { 100 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n"); 101 102 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 103 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 104 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2); 105 } 106} 107 108/** 109 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. 110 * @host: The SDHCI host instance. 111 * 112 * Callback to return the maximum clock rate acheivable by the controller. 113*/ 114static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) 115{ 116 struct sdhci_s3c *ourhost = to_s3c(host); 117 struct clk *busclk; 118 unsigned int rate, max; 119 int clk; 120 121 /* note, a reset will reset the clock source */ 122 123 sdhci_s3c_check_sclk(host); 124 125 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) { 126 busclk = ourhost->clk_bus[clk]; 127 if (!busclk) 128 continue; 129 130 rate = clk_get_rate(busclk); 131 if (rate > max) 132 max = rate; 133 } 134 135 return max; 136} 137 138/** 139 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting 140 * @ourhost: Our SDHCI instance. 141 * @src: The source clock index. 142 * @wanted: The clock frequency wanted. 143 */ 144static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, 145 unsigned int src, 146 unsigned int wanted) 147{ 148 unsigned long rate; 149 struct clk *clksrc = ourhost->clk_bus[src]; 150 int div; 151 152 if (!clksrc) 153 return UINT_MAX; 154 155 /* 156 * If controller uses a non-standard clock division, find the best clock 157 * speed possible with selected clock source and skip the division. 158 */ 159 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 160 rate = clk_round_rate(clksrc, wanted); 161 return wanted - rate; 162 } 163 164 rate = clk_get_rate(clksrc); 165 166 for (div = 1; div < 256; div *= 2) { 167 if ((rate / div) <= wanted) 168 break; 169 } 170 171 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", 172 src, rate, wanted, rate / div); 173 174 return wanted - (rate / div); 175} 176 177/** 178 * sdhci_s3c_set_clock - callback on clock change 179 * @host: The SDHCI host being changed 180 * @clock: The clock rate being requested. 181 * 182 * When the card's clock is going to be changed, look at the new frequency 183 * and find the best clock source to go with it. 184*/ 185static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) 186{ 187 struct sdhci_s3c *ourhost = to_s3c(host); 188 unsigned int best = UINT_MAX; 189 unsigned int delta; 190 int best_src = 0; 191 int src; 192 u32 ctrl; 193 194 /* don't bother if the clock is going off. */ 195 if (clock == 0) 196 return; 197 198 for (src = 0; src < MAX_BUS_CLK; src++) { 199 delta = sdhci_s3c_consider_clock(ourhost, src, clock); 200 if (delta < best) { 201 best = delta; 202 best_src = src; 203 } 204 } 205 206 dev_dbg(&ourhost->pdev->dev, 207 "selected source %d, clock %d, delta %d\n", 208 best_src, clock, best); 209 210 /* select the new clock source */ 211 if (ourhost->cur_clk != best_src) { 212 struct clk *clk = ourhost->clk_bus[best_src]; 213 214 clk_prepare_enable(clk); 215 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 216 217 /* turn clock off to card before changing clock source */ 218 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); 219 220 ourhost->cur_clk = best_src; 221 host->max_clk = clk_get_rate(clk); 222 223 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 224 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; 225 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; 226 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 227 } 228 229 /* reprogram default hardware configuration */ 230 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, 231 host->ioaddr + S3C64XX_SDHCI_CONTROL4); 232 233 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); 234 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | 235 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | 236 S3C_SDHCI_CTRL2_ENFBCLKRX | 237 S3C_SDHCI_CTRL2_DFCNT_NONE | 238 S3C_SDHCI_CTRL2_ENCLKOUTHOLD); 239 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); 240 241 /* reconfigure the controller for new clock rate */ 242 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); 243 if (clock < 25 * 1000000) 244 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); 245 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); 246} 247 248/** 249 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value 250 * @host: The SDHCI host being queried 251 * 252 * To init mmc host properly a minimal clock value is needed. For high system 253 * bus clock's values the standard formula gives values out of allowed range. 254 * The clock still can be set to lower values, if clock source other then 255 * system bus is selected. 256*/ 257static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) 258{ 259 struct sdhci_s3c *ourhost = to_s3c(host); 260 unsigned int delta, min = UINT_MAX; 261 int src; 262 263 for (src = 0; src < MAX_BUS_CLK; src++) { 264 delta = sdhci_s3c_consider_clock(ourhost, src, 0); 265 if (delta == UINT_MAX) 266 continue; 267 /* delta is a negative value in this case */ 268 if (-delta < min) 269 min = -delta; 270 } 271 return min; 272} 273 274/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ 275static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) 276{ 277 struct sdhci_s3c *ourhost = to_s3c(host); 278 279 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX); 280} 281 282/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ 283static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) 284{ 285 struct sdhci_s3c *ourhost = to_s3c(host); 286 287 /* 288 * initial clock can be in the frequency range of 289 * 100KHz-400KHz, so we set it as max value. 290 */ 291 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000); 292} 293 294/* sdhci_cmu_set_clock - callback on clock change.*/ 295static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) 296{ 297 struct sdhci_s3c *ourhost = to_s3c(host); 298 struct device *dev = &ourhost->pdev->dev; 299 unsigned long timeout; 300 u16 clk = 0; 301 302 /* don't bother if the clock is going off */ 303 if (clock == 0) 304 return; 305 306 sdhci_s3c_set_clock(host, clock); 307 308 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); 309 310 host->clock = clock; 311 312 clk = SDHCI_CLOCK_INT_EN; 313 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 314 315 /* Wait max 20 ms */ 316 timeout = 20; 317 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 318 & SDHCI_CLOCK_INT_STABLE)) { 319 if (timeout == 0) { 320 dev_err(dev, "%s: Internal clock never stabilised.\n", 321 mmc_hostname(host->mmc)); 322 return; 323 } 324 timeout--; 325 mdelay(1); 326 } 327 328 clk |= SDHCI_CLOCK_CARD_EN; 329 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 330} 331 332/** 333 * sdhci_s3c_platform_8bit_width - support 8bit buswidth 334 * @host: The SDHCI host being queried 335 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested 336 * 337 * We have 8-bit width support but is not a v3 controller. 338 * So we add platform_8bit_width() and support 8bit width. 339 */ 340static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width) 341{ 342 u8 ctrl; 343 344 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 345 346 switch (width) { 347 case MMC_BUS_WIDTH_8: 348 ctrl |= SDHCI_CTRL_8BITBUS; 349 ctrl &= ~SDHCI_CTRL_4BITBUS; 350 break; 351 case MMC_BUS_WIDTH_4: 352 ctrl |= SDHCI_CTRL_4BITBUS; 353 ctrl &= ~SDHCI_CTRL_8BITBUS; 354 break; 355 default: 356 ctrl &= ~SDHCI_CTRL_4BITBUS; 357 ctrl &= ~SDHCI_CTRL_8BITBUS; 358 break; 359 } 360 361 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 362 363 return 0; 364} 365 366static struct sdhci_ops sdhci_s3c_ops = { 367 .get_max_clock = sdhci_s3c_get_max_clk, 368 .set_clock = sdhci_s3c_set_clock, 369 .get_min_clock = sdhci_s3c_get_min_clock, 370 .platform_8bit_width = sdhci_s3c_platform_8bit_width, 371}; 372 373static void sdhci_s3c_notify_change(struct platform_device *dev, int state) 374{ 375 struct sdhci_host *host = platform_get_drvdata(dev); 376 struct sdhci_s3c *sc = sdhci_priv(host); 377 unsigned long flags; 378 379 if (host) { 380 spin_lock_irqsave(&host->lock, flags); 381 if (state) { 382 dev_dbg(&dev->dev, "card inserted.\n"); 383#ifdef CONFIG_PM_RUNTIME 384 clk_prepare_enable(sc->clk_io); 385#endif 386 host->flags &= ~SDHCI_DEVICE_DEAD; 387 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 388 } else { 389 dev_dbg(&dev->dev, "card removed.\n"); 390 host->flags |= SDHCI_DEVICE_DEAD; 391 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 392#ifdef CONFIG_PM_RUNTIME 393 clk_disable_unprepare(sc->clk_io); 394#endif 395 } 396 tasklet_schedule(&host->card_tasklet); 397 spin_unlock_irqrestore(&host->lock, flags); 398 } 399} 400 401static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) 402{ 403 struct sdhci_s3c *sc = dev_id; 404 int status = gpio_get_value(sc->ext_cd_gpio); 405 if (sc->pdata->ext_cd_gpio_invert) 406 status = !status; 407 sdhci_s3c_notify_change(sc->pdev, status); 408 return IRQ_HANDLED; 409} 410 411static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) 412{ 413 struct s3c_sdhci_platdata *pdata = sc->pdata; 414 struct device *dev = &sc->pdev->dev; 415 416 if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { 417 sc->ext_cd_gpio = pdata->ext_cd_gpio; 418 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); 419 if (sc->ext_cd_irq && 420 request_threaded_irq(sc->ext_cd_irq, NULL, 421 sdhci_s3c_gpio_card_detect_thread, 422 IRQF_TRIGGER_RISING | 423 IRQF_TRIGGER_FALLING | 424 IRQF_ONESHOT, 425 dev_name(dev), sc) == 0) { 426 int status = gpio_get_value(sc->ext_cd_gpio); 427 if (pdata->ext_cd_gpio_invert) 428 status = !status; 429 sdhci_s3c_notify_change(sc->pdev, status); 430 } else { 431 dev_warn(dev, "cannot request irq for card detect\n"); 432 sc->ext_cd_irq = 0; 433 } 434 } else { 435 dev_err(dev, "cannot request gpio for card detect\n"); 436 } 437} 438 439#ifdef CONFIG_OF 440static int __devinit sdhci_s3c_parse_dt(struct device *dev, 441 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 442{ 443 struct device_node *node = dev->of_node; 444 struct sdhci_s3c *ourhost = to_s3c(host); 445 u32 max_width; 446 int gpio, cnt, ret; 447 448 /* if the bus-width property is not specified, assume width as 1 */ 449 if (of_property_read_u32(node, "bus-width", &max_width)) 450 max_width = 1; 451 pdata->max_width = max_width; 452 453 ourhost->gpios = devm_kzalloc(dev, NUM_GPIOS(pdata->max_width) * 454 sizeof(int), GFP_KERNEL); 455 if (!ourhost->gpios) 456 return -ENOMEM; 457 458 /* get the card detection method */ 459 if (of_get_property(node, "broken-cd", NULL)) { 460 pdata->cd_type = S3C_SDHCI_CD_NONE; 461 goto setup_bus; 462 } 463 464 if (of_get_property(node, "non-removable", NULL)) { 465 pdata->cd_type = S3C_SDHCI_CD_PERMANENT; 466 goto setup_bus; 467 } 468 469 gpio = of_get_named_gpio(node, "cd-gpios", 0); 470 if (gpio_is_valid(gpio)) { 471 pdata->cd_type = S3C_SDHCI_CD_GPIO; 472 goto found_cd; 473 } else if (gpio != -ENOENT) { 474 dev_err(dev, "invalid card detect gpio specified\n"); 475 return -EINVAL; 476 } 477 478 gpio = of_get_named_gpio(node, "samsung,cd-pinmux-gpio", 0); 479 if (gpio_is_valid(gpio)) { 480 pdata->cd_type = S3C_SDHCI_CD_INTERNAL; 481 goto found_cd; 482 } else if (gpio != -ENOENT) { 483 dev_err(dev, "invalid card detect gpio specified\n"); 484 return -EINVAL; 485 } 486 487 dev_info(dev, "assuming no card detect line available\n"); 488 pdata->cd_type = S3C_SDHCI_CD_NONE; 489 490 found_cd: 491 if (pdata->cd_type == S3C_SDHCI_CD_GPIO) { 492 pdata->ext_cd_gpio = gpio; 493 ourhost->ext_cd_gpio = -1; 494 if (of_get_property(node, "cd-inverted", NULL)) 495 pdata->ext_cd_gpio_invert = 1; 496 } else if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 497 ret = devm_gpio_request(dev, gpio, "sdhci-cd"); 498 if (ret) { 499 dev_err(dev, "card detect gpio request failed\n"); 500 return -EINVAL; 501 } 502 ourhost->ext_cd_gpio = gpio; 503 } 504 505 setup_bus: 506 /* get the gpios for command, clock and data lines */ 507 for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) { 508 gpio = of_get_gpio(node, cnt); 509 if (!gpio_is_valid(gpio)) { 510 dev_err(dev, "invalid gpio[%d]\n", cnt); 511 return -EINVAL; 512 } 513 ourhost->gpios[cnt] = gpio; 514 } 515 516 for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) { 517 ret = devm_gpio_request(dev, ourhost->gpios[cnt], "sdhci-gpio"); 518 if (ret) { 519 dev_err(dev, "gpio[%d] request failed\n", cnt); 520 return -EINVAL; 521 } 522 } 523 524 return 0; 525} 526#else 527static int __devinit sdhci_s3c_parse_dt(struct device *dev, 528 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) 529{ 530 return -EINVAL; 531} 532#endif 533 534static const struct of_device_id sdhci_s3c_dt_match[]; 535 536static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( 537 struct platform_device *pdev) 538{ 539#ifdef CONFIG_OF 540 if (pdev->dev.of_node) { 541 const struct of_device_id *match; 542 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); 543 return (struct sdhci_s3c_drv_data *)match->data; 544 } 545#endif 546 return (struct sdhci_s3c_drv_data *) 547 platform_get_device_id(pdev)->driver_data; 548} 549 550static int __devinit sdhci_s3c_probe(struct platform_device *pdev) 551{ 552 struct s3c_sdhci_platdata *pdata; 553 struct sdhci_s3c_drv_data *drv_data; 554 struct device *dev = &pdev->dev; 555 struct sdhci_host *host; 556 struct sdhci_s3c *sc; 557 struct resource *res; 558 int ret, irq, ptr, clks; 559 560 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 561 dev_err(dev, "no device data specified\n"); 562 return -ENOENT; 563 } 564 565 irq = platform_get_irq(pdev, 0); 566 if (irq < 0) { 567 dev_err(dev, "no irq specified\n"); 568 return irq; 569 } 570 571 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); 572 if (IS_ERR(host)) { 573 dev_err(dev, "sdhci_alloc_host() failed\n"); 574 return PTR_ERR(host); 575 } 576 sc = sdhci_priv(host); 577 578 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 579 if (!pdata) { 580 ret = -ENOMEM; 581 goto err_pdata_io_clk; 582 } 583 584 if (pdev->dev.of_node) { 585 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); 586 if (ret) 587 goto err_pdata_io_clk; 588 } else { 589 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); 590 sc->ext_cd_gpio = -1; /* invalid gpio number */ 591 } 592 593 drv_data = sdhci_s3c_get_driver_data(pdev); 594 595 sc->host = host; 596 sc->pdev = pdev; 597 sc->pdata = pdata; 598 599 platform_set_drvdata(pdev, host); 600 601 sc->clk_io = clk_get(dev, "hsmmc"); 602 if (IS_ERR(sc->clk_io)) { 603 dev_err(dev, "failed to get io clock\n"); 604 ret = PTR_ERR(sc->clk_io); 605 goto err_pdata_io_clk; 606 } 607 608 /* enable the local io clock and keep it running for the moment. */ 609 clk_prepare_enable(sc->clk_io); 610 611 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 612 struct clk *clk; 613 char name[14]; 614 615 snprintf(name, 14, "mmc_busclk.%d", ptr); 616 clk = clk_get(dev, name); 617 if (IS_ERR(clk)) 618 continue; 619 620 clks++; 621 sc->clk_bus[ptr] = clk; 622 623 /* 624 * save current clock index to know which clock bus 625 * is used later in overriding functions. 626 */ 627 sc->cur_clk = ptr; 628 629 dev_info(dev, "clock source %d: %s (%ld Hz)\n", 630 ptr, name, clk_get_rate(clk)); 631 } 632 633 if (clks == 0) { 634 dev_err(dev, "failed to find any bus clocks\n"); 635 ret = -ENOENT; 636 goto err_no_busclks; 637 } 638 639#ifndef CONFIG_PM_RUNTIME 640 clk_prepare_enable(sc->clk_bus[sc->cur_clk]); 641#endif 642 643 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 644 host->ioaddr = devm_request_and_ioremap(&pdev->dev, res); 645 if (!host->ioaddr) { 646 dev_err(dev, "failed to map registers\n"); 647 ret = -ENXIO; 648 goto err_req_regs; 649 } 650 651 /* Ensure we have minimal gpio selected CMD/CLK/Detect */ 652 if (pdata->cfg_gpio) 653 pdata->cfg_gpio(pdev, pdata->max_width); 654 655 host->hw_name = "samsung-hsmmc"; 656 host->ops = &sdhci_s3c_ops; 657 host->quirks = 0; 658 host->irq = irq; 659 660 /* Setup quirks for the controller */ 661 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; 662 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; 663 if (drv_data) 664 host->quirks |= drv_data->sdhci_quirks; 665 666#ifndef CONFIG_MMC_SDHCI_S3C_DMA 667 668 /* we currently see overruns on errors, so disable the SDMA 669 * support as well. */ 670 host->quirks |= SDHCI_QUIRK_BROKEN_DMA; 671 672#endif /* CONFIG_MMC_SDHCI_S3C_DMA */ 673 674 /* It seems we do not get an DATA transfer complete on non-busy 675 * transfers, not sure if this is a problem with this specific 676 * SDHCI block, or a missing configuration that needs to be set. */ 677 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; 678 679 /* This host supports the Auto CMD12 */ 680 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; 681 682 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ 683 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; 684 685 if (pdata->cd_type == S3C_SDHCI_CD_NONE || 686 pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 687 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; 688 689 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) 690 host->mmc->caps = MMC_CAP_NONREMOVABLE; 691 692 switch (pdata->max_width) { 693 case 8: 694 host->mmc->caps |= MMC_CAP_8_BIT_DATA; 695 case 4: 696 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 697 break; 698 } 699 700 if (pdata->pm_caps) 701 host->mmc->pm_caps |= pdata->pm_caps; 702 703 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | 704 SDHCI_QUIRK_32BIT_DMA_SIZE); 705 706 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ 707 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 708 709 /* 710 * If controller does not have internal clock divider, 711 * we can use overriding functions instead of default. 712 */ 713 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { 714 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; 715 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; 716 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; 717 } 718 719 /* It supports additional host capabilities if needed */ 720 if (pdata->host_caps) 721 host->mmc->caps |= pdata->host_caps; 722 723 if (pdata->host_caps2) 724 host->mmc->caps2 |= pdata->host_caps2; 725 726 pm_runtime_enable(&pdev->dev); 727 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 728 pm_runtime_use_autosuspend(&pdev->dev); 729 pm_suspend_ignore_children(&pdev->dev, 1); 730 731 ret = sdhci_add_host(host); 732 if (ret) { 733 dev_err(dev, "sdhci_add_host() failed\n"); 734 pm_runtime_forbid(&pdev->dev); 735 pm_runtime_get_noresume(&pdev->dev); 736 goto err_req_regs; 737 } 738 739 /* The following two methods of card detection might call 740 sdhci_s3c_notify_change() immediately, so they can be called 741 only after sdhci_add_host(). Setup errors are ignored. */ 742 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) 743 pdata->ext_cd_init(&sdhci_s3c_notify_change); 744 if (pdata->cd_type == S3C_SDHCI_CD_GPIO && 745 gpio_is_valid(pdata->ext_cd_gpio)) 746 sdhci_s3c_setup_card_detect_gpio(sc); 747 748#ifdef CONFIG_PM_RUNTIME 749 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 750 clk_disable_unprepare(sc->clk_io); 751#endif 752 return 0; 753 754 err_req_regs: 755#ifndef CONFIG_PM_RUNTIME 756 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]); 757#endif 758 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 759 if (sc->clk_bus[ptr]) { 760 clk_put(sc->clk_bus[ptr]); 761 } 762 } 763 764 err_no_busclks: 765 clk_disable_unprepare(sc->clk_io); 766 clk_put(sc->clk_io); 767 768 err_pdata_io_clk: 769 sdhci_free_host(host); 770 771 return ret; 772} 773 774static int __devexit sdhci_s3c_remove(struct platform_device *pdev) 775{ 776 struct sdhci_host *host = platform_get_drvdata(pdev); 777 struct sdhci_s3c *sc = sdhci_priv(host); 778 struct s3c_sdhci_platdata *pdata = sc->pdata; 779 int ptr; 780 781 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) 782 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); 783 784 if (sc->ext_cd_irq) 785 free_irq(sc->ext_cd_irq, sc); 786 787#ifdef CONFIG_PM_RUNTIME 788 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) 789 clk_prepare_enable(sc->clk_io); 790#endif 791 sdhci_remove_host(host, 1); 792 793 pm_runtime_dont_use_autosuspend(&pdev->dev); 794 pm_runtime_disable(&pdev->dev); 795 796#ifndef CONFIG_PM_RUNTIME 797 clk_disable_unprepare(sc->clk_bus[sc->cur_clk]); 798#endif 799 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 800 if (sc->clk_bus[ptr]) { 801 clk_put(sc->clk_bus[ptr]); 802 } 803 } 804 clk_disable_unprepare(sc->clk_io); 805 clk_put(sc->clk_io); 806 807 sdhci_free_host(host); 808 platform_set_drvdata(pdev, NULL); 809 810 return 0; 811} 812 813#ifdef CONFIG_PM_SLEEP 814static int sdhci_s3c_suspend(struct device *dev) 815{ 816 struct sdhci_host *host = dev_get_drvdata(dev); 817 818 return sdhci_suspend_host(host); 819} 820 821static int sdhci_s3c_resume(struct device *dev) 822{ 823 struct sdhci_host *host = dev_get_drvdata(dev); 824 825 return sdhci_resume_host(host); 826} 827#endif 828 829#ifdef CONFIG_PM_RUNTIME 830static int sdhci_s3c_runtime_suspend(struct device *dev) 831{ 832 struct sdhci_host *host = dev_get_drvdata(dev); 833 struct sdhci_s3c *ourhost = to_s3c(host); 834 struct clk *busclk = ourhost->clk_io; 835 int ret; 836 837 ret = sdhci_runtime_suspend_host(host); 838 839 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); 840 clk_disable_unprepare(busclk); 841 return ret; 842} 843 844static int sdhci_s3c_runtime_resume(struct device *dev) 845{ 846 struct sdhci_host *host = dev_get_drvdata(dev); 847 struct sdhci_s3c *ourhost = to_s3c(host); 848 struct clk *busclk = ourhost->clk_io; 849 int ret; 850 851 clk_prepare_enable(busclk); 852 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); 853 ret = sdhci_runtime_resume_host(host); 854 return ret; 855} 856#endif 857 858#ifdef CONFIG_PM 859static const struct dev_pm_ops sdhci_s3c_pmops = { 860 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) 861 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, 862 NULL) 863}; 864 865#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) 866 867#else 868#define SDHCI_S3C_PMOPS NULL 869#endif 870 871#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) 872static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { 873 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, 874}; 875#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) 876#else 877#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) 878#endif 879 880static struct platform_device_id sdhci_s3c_driver_ids[] = { 881 { 882 .name = "s3c-sdhci", 883 .driver_data = (kernel_ulong_t)NULL, 884 }, { 885 .name = "exynos4-sdhci", 886 .driver_data = EXYNOS4_SDHCI_DRV_DATA, 887 }, 888 { } 889}; 890MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); 891 892#ifdef CONFIG_OF 893static const struct of_device_id sdhci_s3c_dt_match[] = { 894 { .compatible = "samsung,s3c6410-sdhci", }, 895 { .compatible = "samsung,exynos4210-sdhci", 896 .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, 897 {}, 898}; 899MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); 900#endif 901 902static struct platform_driver sdhci_s3c_driver = { 903 .probe = sdhci_s3c_probe, 904 .remove = __devexit_p(sdhci_s3c_remove), 905 .id_table = sdhci_s3c_driver_ids, 906 .driver = { 907 .owner = THIS_MODULE, 908 .name = "s3c-sdhci", 909 .of_match_table = of_match_ptr(sdhci_s3c_dt_match), 910 .pm = SDHCI_S3C_PMOPS, 911 }, 912}; 913 914module_platform_driver(sdhci_s3c_driver); 915 916MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); 917MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 918MODULE_LICENSE("GPL v2"); 919MODULE_ALIAS("platform:s3c-sdhci"); 920