tmio_mmc.c revision 845ecd20239c28e97e766ff54078a58be19f3a91
1/* 2 * linux/drivers/mmc/tmio_mmc.c 3 * 4 * Copyright (C) 2004 Ian Molton 5 * Copyright (C) 2007 Ian Molton 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Driver for the MMC / SD / SDIO cell found in: 12 * 13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3 14 * 15 * This driver draws mainly on scattered spec sheets, Reverse engineering 16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit 17 * support). (Further 4 bit support from a later datasheet). 18 * 19 * TODO: 20 * Investigate using a workqueue for PIO transfers 21 * Eliminate FIXMEs 22 * SDIO support 23 * Better Power management 24 * Handle MMC errors better 25 * double buffer support 26 * 27 */ 28 29#include <linux/delay.h> 30#include <linux/device.h> 31#include <linux/dmaengine.h> 32#include <linux/highmem.h> 33#include <linux/interrupt.h> 34#include <linux/io.h> 35#include <linux/irq.h> 36#include <linux/mfd/core.h> 37#include <linux/mfd/tmio.h> 38#include <linux/mmc/host.h> 39#include <linux/module.h> 40#include <linux/pagemap.h> 41#include <linux/scatterlist.h> 42 43#define CTL_SD_CMD 0x00 44#define CTL_ARG_REG 0x04 45#define CTL_STOP_INTERNAL_ACTION 0x08 46#define CTL_XFER_BLK_COUNT 0xa 47#define CTL_RESPONSE 0x0c 48#define CTL_STATUS 0x1c 49#define CTL_IRQ_MASK 0x20 50#define CTL_SD_CARD_CLK_CTL 0x24 51#define CTL_SD_XFER_LEN 0x26 52#define CTL_SD_MEM_CARD_OPT 0x28 53#define CTL_SD_ERROR_DETAIL_STATUS 0x2c 54#define CTL_SD_DATA_PORT 0x30 55#define CTL_TRANSACTION_CTL 0x34 56#define CTL_SDIO_STATUS 0x36 57#define CTL_SDIO_IRQ_MASK 0x38 58#define CTL_RESET_SD 0xe0 59#define CTL_SDIO_REGS 0x100 60#define CTL_CLK_AND_WAIT_CTL 0x138 61#define CTL_RESET_SDIO 0x1e0 62 63/* Definitions for values the CTRL_STATUS register can take. */ 64#define TMIO_STAT_CMDRESPEND 0x00000001 65#define TMIO_STAT_DATAEND 0x00000004 66#define TMIO_STAT_CARD_REMOVE 0x00000008 67#define TMIO_STAT_CARD_INSERT 0x00000010 68#define TMIO_STAT_SIGSTATE 0x00000020 69#define TMIO_STAT_WRPROTECT 0x00000080 70#define TMIO_STAT_CARD_REMOVE_A 0x00000100 71#define TMIO_STAT_CARD_INSERT_A 0x00000200 72#define TMIO_STAT_SIGSTATE_A 0x00000400 73#define TMIO_STAT_CMD_IDX_ERR 0x00010000 74#define TMIO_STAT_CRCFAIL 0x00020000 75#define TMIO_STAT_STOPBIT_ERR 0x00040000 76#define TMIO_STAT_DATATIMEOUT 0x00080000 77#define TMIO_STAT_RXOVERFLOW 0x00100000 78#define TMIO_STAT_TXUNDERRUN 0x00200000 79#define TMIO_STAT_CMDTIMEOUT 0x00400000 80#define TMIO_STAT_RXRDY 0x01000000 81#define TMIO_STAT_TXRQ 0x02000000 82#define TMIO_STAT_ILL_FUNC 0x20000000 83#define TMIO_STAT_CMD_BUSY 0x40000000 84#define TMIO_STAT_ILL_ACCESS 0x80000000 85 86/* Definitions for values the CTRL_SDIO_STATUS register can take. */ 87#define TMIO_SDIO_STAT_IOIRQ 0x0001 88#define TMIO_SDIO_STAT_EXPUB52 0x4000 89#define TMIO_SDIO_STAT_EXWT 0x8000 90#define TMIO_SDIO_MASK_ALL 0xc007 91 92/* Define some IRQ masks */ 93/* This is the mask used at reset by the chip */ 94#define TMIO_MASK_ALL 0x837f031d 95#define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) 96#define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) 97#define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ 98 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) 99#define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) 100 101#define enable_mmc_irqs(host, i) \ 102 do { \ 103 u32 mask;\ 104 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \ 105 mask &= ~((i) & TMIO_MASK_IRQ); \ 106 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \ 107 } while (0) 108 109#define disable_mmc_irqs(host, i) \ 110 do { \ 111 u32 mask;\ 112 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \ 113 mask |= ((i) & TMIO_MASK_IRQ); \ 114 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \ 115 } while (0) 116 117#define ack_mmc_irqs(host, i) \ 118 do { \ 119 sd_ctrl_write32((host), CTL_STATUS, ~(i)); \ 120 } while (0) 121 122/* This is arbitrary, just noone needed any higher alignment yet */ 123#define MAX_ALIGN 4 124 125struct tmio_mmc_host { 126 void __iomem *ctl; 127 unsigned long bus_shift; 128 struct mmc_command *cmd; 129 struct mmc_request *mrq; 130 struct mmc_data *data; 131 struct mmc_host *mmc; 132 int irq; 133 unsigned int sdio_irq_enabled; 134 135 /* Callbacks for clock / power control */ 136 void (*set_pwr)(struct platform_device *host, int state); 137 void (*set_clk_div)(struct platform_device *host, int state); 138 139 /* pio related stuff */ 140 struct scatterlist *sg_ptr; 141 struct scatterlist *sg_orig; 142 unsigned int sg_len; 143 unsigned int sg_off; 144 145 struct platform_device *pdev; 146 147 /* DMA support */ 148 struct dma_chan *chan_rx; 149 struct dma_chan *chan_tx; 150 struct tasklet_struct dma_complete; 151 struct tasklet_struct dma_issue; 152#ifdef CONFIG_TMIO_MMC_DMA 153 unsigned int dma_sglen; 154 u8 bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN))); 155 struct scatterlist bounce_sg; 156#endif 157}; 158 159static void tmio_check_bounce_buffer(struct tmio_mmc_host *host); 160 161static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) 162{ 163 return readw(host->ctl + (addr << host->bus_shift)); 164} 165 166static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, 167 u16 *buf, int count) 168{ 169 readsw(host->ctl + (addr << host->bus_shift), buf, count); 170} 171 172static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr) 173{ 174 return readw(host->ctl + (addr << host->bus_shift)) | 175 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16; 176} 177 178static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val) 179{ 180 writew(val, host->ctl + (addr << host->bus_shift)); 181} 182 183static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, 184 u16 *buf, int count) 185{ 186 writesw(host->ctl + (addr << host->bus_shift), buf, count); 187} 188 189static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) 190{ 191 writew(val, host->ctl + (addr << host->bus_shift)); 192 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); 193} 194 195static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data) 196{ 197 host->sg_len = data->sg_len; 198 host->sg_ptr = data->sg; 199 host->sg_orig = data->sg; 200 host->sg_off = 0; 201} 202 203static int tmio_mmc_next_sg(struct tmio_mmc_host *host) 204{ 205 host->sg_ptr = sg_next(host->sg_ptr); 206 host->sg_off = 0; 207 return --host->sg_len; 208} 209 210static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags) 211{ 212 local_irq_save(*flags); 213 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; 214} 215 216static void tmio_mmc_kunmap_atomic(void *virt, unsigned long *flags) 217{ 218 kunmap_atomic(virt, KM_BIO_SRC_IRQ); 219 local_irq_restore(*flags); 220} 221 222#ifdef CONFIG_MMC_DEBUG 223 224#define STATUS_TO_TEXT(a) \ 225 do { \ 226 if (status & TMIO_STAT_##a) \ 227 printk(#a); \ 228 } while (0) 229 230void pr_debug_status(u32 status) 231{ 232 printk(KERN_DEBUG "status: %08x = ", status); 233 STATUS_TO_TEXT(CARD_REMOVE); 234 STATUS_TO_TEXT(CARD_INSERT); 235 STATUS_TO_TEXT(SIGSTATE); 236 STATUS_TO_TEXT(WRPROTECT); 237 STATUS_TO_TEXT(CARD_REMOVE_A); 238 STATUS_TO_TEXT(CARD_INSERT_A); 239 STATUS_TO_TEXT(SIGSTATE_A); 240 STATUS_TO_TEXT(CMD_IDX_ERR); 241 STATUS_TO_TEXT(STOPBIT_ERR); 242 STATUS_TO_TEXT(ILL_FUNC); 243 STATUS_TO_TEXT(CMD_BUSY); 244 STATUS_TO_TEXT(CMDRESPEND); 245 STATUS_TO_TEXT(DATAEND); 246 STATUS_TO_TEXT(CRCFAIL); 247 STATUS_TO_TEXT(DATATIMEOUT); 248 STATUS_TO_TEXT(CMDTIMEOUT); 249 STATUS_TO_TEXT(RXOVERFLOW); 250 STATUS_TO_TEXT(TXUNDERRUN); 251 STATUS_TO_TEXT(RXRDY); 252 STATUS_TO_TEXT(TXRQ); 253 STATUS_TO_TEXT(ILL_ACCESS); 254 printk("\n"); 255} 256 257#else 258#define pr_debug_status(s) do { } while (0) 259#endif 260 261static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 262{ 263 struct tmio_mmc_host *host = mmc_priv(mmc); 264 265 if (enable) { 266 host->sdio_irq_enabled = 1; 267 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001); 268 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, 269 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ)); 270 } else { 271 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL); 272 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000); 273 host->sdio_irq_enabled = 0; 274 } 275} 276 277static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock) 278{ 279 u32 clk = 0, clock; 280 281 if (new_clock) { 282 for (clock = host->mmc->f_min, clk = 0x80000080; 283 new_clock >= (clock<<1); clk >>= 1) 284 clock <<= 1; 285 clk |= 0x100; 286 } 287 288 if (host->set_clk_div) 289 host->set_clk_div(host->pdev, (clk>>22) & 1); 290 291 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff); 292} 293 294static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) 295{ 296 struct mfd_cell *cell = host->pdev->dev.platform_data; 297 struct tmio_mmc_data *pdata = cell->driver_data; 298 299 /* 300 * Testing on sh-mobile showed that SDIO IRQs are unmasked when 301 * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the 302 * device IRQ here and restore the SDIO IRQ mask before 303 * re-enabling the device IRQ. 304 */ 305 if (pdata->flags & TMIO_MMC_SDIO_IRQ) 306 disable_irq(host->irq); 307 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); 308 msleep(10); 309 if (pdata->flags & TMIO_MMC_SDIO_IRQ) { 310 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled); 311 enable_irq(host->irq); 312 } 313 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 & 314 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 315 msleep(10); 316} 317 318static void tmio_mmc_clk_start(struct tmio_mmc_host *host) 319{ 320 struct mfd_cell *cell = host->pdev->dev.platform_data; 321 struct tmio_mmc_data *pdata = cell->driver_data; 322 323 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 | 324 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 325 msleep(10); 326 /* see comment in tmio_mmc_clk_stop above */ 327 if (pdata->flags & TMIO_MMC_SDIO_IRQ) 328 disable_irq(host->irq); 329 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); 330 msleep(10); 331 if (pdata->flags & TMIO_MMC_SDIO_IRQ) { 332 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled); 333 enable_irq(host->irq); 334 } 335} 336 337static void reset(struct tmio_mmc_host *host) 338{ 339 /* FIXME - should we set stop clock reg here */ 340 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000); 341 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000); 342 msleep(10); 343 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 344 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001); 345 msleep(10); 346} 347 348static void 349tmio_mmc_finish_request(struct tmio_mmc_host *host) 350{ 351 struct mmc_request *mrq = host->mrq; 352 353 host->mrq = NULL; 354 host->cmd = NULL; 355 host->data = NULL; 356 357 mmc_request_done(host->mmc, mrq); 358} 359 360/* These are the bitmasks the tmio chip requires to implement the MMC response 361 * types. Note that R1 and R6 are the same in this scheme. */ 362#define APP_CMD 0x0040 363#define RESP_NONE 0x0300 364#define RESP_R1 0x0400 365#define RESP_R1B 0x0500 366#define RESP_R2 0x0600 367#define RESP_R3 0x0700 368#define DATA_PRESENT 0x0800 369#define TRANSFER_READ 0x1000 370#define TRANSFER_MULTI 0x2000 371#define SECURITY_CMD 0x4000 372 373static int 374tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd) 375{ 376 struct mmc_data *data = host->data; 377 int c = cmd->opcode; 378 379 /* Command 12 is handled by hardware */ 380 if (cmd->opcode == 12 && !cmd->arg) { 381 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001); 382 return 0; 383 } 384 385 switch (mmc_resp_type(cmd)) { 386 case MMC_RSP_NONE: c |= RESP_NONE; break; 387 case MMC_RSP_R1: c |= RESP_R1; break; 388 case MMC_RSP_R1B: c |= RESP_R1B; break; 389 case MMC_RSP_R2: c |= RESP_R2; break; 390 case MMC_RSP_R3: c |= RESP_R3; break; 391 default: 392 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd)); 393 return -EINVAL; 394 } 395 396 host->cmd = cmd; 397 398/* FIXME - this seems to be ok commented out but the spec suggest this bit 399 * should be set when issuing app commands. 400 * if(cmd->flags & MMC_FLAG_ACMD) 401 * c |= APP_CMD; 402 */ 403 if (data) { 404 c |= DATA_PRESENT; 405 if (data->blocks > 1) { 406 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100); 407 c |= TRANSFER_MULTI; 408 } 409 if (data->flags & MMC_DATA_READ) 410 c |= TRANSFER_READ; 411 } 412 413 enable_mmc_irqs(host, TMIO_MASK_CMD); 414 415 /* Fire off the command */ 416 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg); 417 sd_ctrl_write16(host, CTL_SD_CMD, c); 418 419 return 0; 420} 421 422/* 423 * This chip always returns (at least?) as much data as you ask for. 424 * I'm unsure what happens if you ask for less than a block. This should be 425 * looked into to ensure that a funny length read doesnt hose the controller. 426 */ 427static void tmio_mmc_pio_irq(struct tmio_mmc_host *host) 428{ 429 struct mmc_data *data = host->data; 430 void *sg_virt; 431 unsigned short *buf; 432 unsigned int count; 433 unsigned long flags; 434 435 if (!data) { 436 pr_debug("Spurious PIO IRQ\n"); 437 return; 438 } 439 440 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags); 441 buf = (unsigned short *)(sg_virt + host->sg_off); 442 443 count = host->sg_ptr->length - host->sg_off; 444 if (count > data->blksz) 445 count = data->blksz; 446 447 pr_debug("count: %08x offset: %08x flags %08x\n", 448 count, host->sg_off, data->flags); 449 450 /* Transfer the data */ 451 if (data->flags & MMC_DATA_READ) 452 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); 453 else 454 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1); 455 456 host->sg_off += count; 457 458 tmio_mmc_kunmap_atomic(sg_virt, &flags); 459 460 if (host->sg_off == host->sg_ptr->length) 461 tmio_mmc_next_sg(host); 462 463 return; 464} 465 466static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host) 467{ 468 struct mmc_data *data = host->data; 469 struct mmc_command *stop; 470 471 host->data = NULL; 472 473 if (!data) { 474 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n"); 475 return; 476 } 477 stop = data->stop; 478 479 /* FIXME - return correct transfer count on errors */ 480 if (!data->error) 481 data->bytes_xfered = data->blocks * data->blksz; 482 else 483 data->bytes_xfered = 0; 484 485 pr_debug("Completed data request\n"); 486 487 /* 488 * FIXME: other drivers allow an optional stop command of any given type 489 * which we dont do, as the chip can auto generate them. 490 * Perhaps we can be smarter about when to use auto CMD12 and 491 * only issue the auto request when we know this is the desired 492 * stop command, allowing fallback to the stop command the 493 * upper layers expect. For now, we do what works. 494 */ 495 496 if (data->flags & MMC_DATA_READ) { 497 if (!host->chan_rx) 498 disable_mmc_irqs(host, TMIO_MASK_READOP); 499 else 500 tmio_check_bounce_buffer(host); 501 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n", 502 host->mrq); 503 } else { 504 if (!host->chan_tx) 505 disable_mmc_irqs(host, TMIO_MASK_WRITEOP); 506 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n", 507 host->mrq); 508 } 509 510 if (stop) { 511 if (stop->opcode == 12 && !stop->arg) 512 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000); 513 else 514 BUG(); 515 } 516 517 tmio_mmc_finish_request(host); 518} 519 520static void tmio_mmc_data_irq(struct tmio_mmc_host *host) 521{ 522 struct mmc_data *data = host->data; 523 524 if (!data) 525 return; 526 527 if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) { 528 /* 529 * Has all data been written out yet? Testing on SuperH showed, 530 * that in most cases the first interrupt comes already with the 531 * BUSY status bit clear, but on some operations, like mount or 532 * in the beginning of a write / sync / umount, there is one 533 * DATAEND interrupt with the BUSY bit set, in this cases 534 * waiting for one more interrupt fixes the problem. 535 */ 536 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) { 537 disable_mmc_irqs(host, TMIO_STAT_DATAEND); 538 tasklet_schedule(&host->dma_complete); 539 } 540 } else if (host->chan_rx && (data->flags & MMC_DATA_READ)) { 541 disable_mmc_irqs(host, TMIO_STAT_DATAEND); 542 tasklet_schedule(&host->dma_complete); 543 } else { 544 tmio_mmc_do_data_irq(host); 545 } 546} 547 548static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, 549 unsigned int stat) 550{ 551 struct mmc_command *cmd = host->cmd; 552 int i, addr; 553 554 if (!host->cmd) { 555 pr_debug("Spurious CMD irq\n"); 556 return; 557 } 558 559 host->cmd = NULL; 560 561 /* This controller is sicker than the PXA one. Not only do we need to 562 * drop the top 8 bits of the first response word, we also need to 563 * modify the order of the response for short response command types. 564 */ 565 566 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4) 567 cmd->resp[i] = sd_ctrl_read32(host, addr); 568 569 if (cmd->flags & MMC_RSP_136) { 570 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24); 571 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24); 572 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24); 573 cmd->resp[3] <<= 8; 574 } else if (cmd->flags & MMC_RSP_R3) { 575 cmd->resp[0] = cmd->resp[3]; 576 } 577 578 if (stat & TMIO_STAT_CMDTIMEOUT) 579 cmd->error = -ETIMEDOUT; 580 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) 581 cmd->error = -EILSEQ; 582 583 /* If there is data to handle we enable data IRQs here, and 584 * we will ultimatley finish the request in the data_end handler. 585 * If theres no data or we encountered an error, finish now. 586 */ 587 if (host->data && !cmd->error) { 588 if (host->data->flags & MMC_DATA_READ) { 589 if (!host->chan_rx) 590 enable_mmc_irqs(host, TMIO_MASK_READOP); 591 } else { 592 if (!host->chan_tx) 593 enable_mmc_irqs(host, TMIO_MASK_WRITEOP); 594 else 595 tasklet_schedule(&host->dma_issue); 596 } 597 } else { 598 tmio_mmc_finish_request(host); 599 } 600 601 return; 602} 603 604static irqreturn_t tmio_mmc_irq(int irq, void *devid) 605{ 606 struct tmio_mmc_host *host = devid; 607 struct mfd_cell *cell = host->pdev->dev.platform_data; 608 struct tmio_mmc_data *pdata = cell->driver_data; 609 unsigned int ireg, irq_mask, status; 610 unsigned int sdio_ireg, sdio_irq_mask, sdio_status; 611 612 pr_debug("MMC IRQ begin\n"); 613 614 status = sd_ctrl_read32(host, CTL_STATUS); 615 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK); 616 ireg = status & TMIO_MASK_IRQ & ~irq_mask; 617 618 sdio_ireg = 0; 619 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) { 620 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS); 621 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK); 622 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask; 623 624 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL); 625 626 if (sdio_ireg && !host->sdio_irq_enabled) { 627 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n", 628 sdio_status, sdio_irq_mask, sdio_ireg); 629 tmio_mmc_enable_sdio_irq(host->mmc, 0); 630 goto out; 631 } 632 633 if (host->mmc->caps & MMC_CAP_SDIO_IRQ && 634 sdio_ireg & TMIO_SDIO_STAT_IOIRQ) 635 mmc_signal_sdio_irq(host->mmc); 636 637 if (sdio_ireg) 638 goto out; 639 } 640 641 pr_debug_status(status); 642 pr_debug_status(ireg); 643 644 if (!ireg) { 645 disable_mmc_irqs(host, status & ~irq_mask); 646 647 pr_warning("tmio_mmc: Spurious irq, disabling! " 648 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg); 649 pr_debug_status(status); 650 651 goto out; 652 } 653 654 while (ireg) { 655 /* Card insert / remove attempts */ 656 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) { 657 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT | 658 TMIO_STAT_CARD_REMOVE); 659 mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 660 } 661 662 /* CRC and other errors */ 663/* if (ireg & TMIO_STAT_ERR_IRQ) 664 * handled |= tmio_error_irq(host, irq, stat); 665 */ 666 667 /* Command completion */ 668 if (ireg & TMIO_MASK_CMD) { 669 ack_mmc_irqs(host, TMIO_MASK_CMD); 670 tmio_mmc_cmd_irq(host, status); 671 } 672 673 /* Data transfer */ 674 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) { 675 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ); 676 tmio_mmc_pio_irq(host); 677 } 678 679 /* Data transfer completion */ 680 if (ireg & TMIO_STAT_DATAEND) { 681 ack_mmc_irqs(host, TMIO_STAT_DATAEND); 682 tmio_mmc_data_irq(host); 683 } 684 685 /* Check status - keep going until we've handled it all */ 686 status = sd_ctrl_read32(host, CTL_STATUS); 687 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK); 688 ireg = status & TMIO_MASK_IRQ & ~irq_mask; 689 690 pr_debug("Status at end of loop: %08x\n", status); 691 pr_debug_status(status); 692 } 693 pr_debug("MMC IRQ end\n"); 694 695out: 696 return IRQ_HANDLED; 697} 698 699#ifdef CONFIG_TMIO_MMC_DMA 700static void tmio_check_bounce_buffer(struct tmio_mmc_host *host) 701{ 702 if (host->sg_ptr == &host->bounce_sg) { 703 unsigned long flags; 704 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags); 705 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length); 706 tmio_mmc_kunmap_atomic(sg_vaddr, &flags); 707 } 708} 709 710static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable) 711{ 712#if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE) 713 /* Switch DMA mode on or off - SuperH specific? */ 714 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0); 715#endif 716} 717 718static void tmio_dma_complete(void *arg) 719{ 720 struct tmio_mmc_host *host = arg; 721 722 dev_dbg(&host->pdev->dev, "Command completed\n"); 723 724 if (!host->data) 725 dev_warn(&host->pdev->dev, "NULL data in DMA completion!\n"); 726 else 727 enable_mmc_irqs(host, TMIO_STAT_DATAEND); 728} 729 730static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host) 731{ 732 struct scatterlist *sg = host->sg_ptr, *sg_tmp; 733 struct dma_async_tx_descriptor *desc = NULL; 734 struct dma_chan *chan = host->chan_rx; 735 struct mfd_cell *cell = host->pdev->dev.platform_data; 736 struct tmio_mmc_data *pdata = cell->driver_data; 737 dma_cookie_t cookie; 738 int ret, i; 739 bool aligned = true, multiple = true; 740 unsigned int align = (1 << pdata->dma->alignment_shift) - 1; 741 742 for_each_sg(sg, sg_tmp, host->sg_len, i) { 743 if (sg_tmp->offset & align) 744 aligned = false; 745 if (sg_tmp->length & align) { 746 multiple = false; 747 break; 748 } 749 } 750 751 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE || 752 align >= MAX_ALIGN)) || !multiple) { 753 ret = -EINVAL; 754 goto pio; 755 } 756 757 /* The only sg element can be unaligned, use our bounce buffer then */ 758 if (!aligned) { 759 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length); 760 host->sg_ptr = &host->bounce_sg; 761 sg = host->sg_ptr; 762 } 763 764 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_FROM_DEVICE); 765 if (ret > 0) { 766 host->dma_sglen = ret; 767 desc = chan->device->device_prep_slave_sg(chan, sg, ret, 768 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 769 } 770 771 if (desc) { 772 desc->callback = tmio_dma_complete; 773 desc->callback_param = host; 774 cookie = desc->tx_submit(desc); 775 if (cookie < 0) { 776 desc = NULL; 777 ret = cookie; 778 } else { 779 chan->device->device_issue_pending(chan); 780 } 781 } 782 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n", 783 __func__, host->sg_len, ret, cookie, host->mrq); 784 785pio: 786 if (!desc) { 787 /* DMA failed, fall back to PIO */ 788 if (ret >= 0) 789 ret = -EIO; 790 host->chan_rx = NULL; 791 dma_release_channel(chan); 792 /* Free the Tx channel too */ 793 chan = host->chan_tx; 794 if (chan) { 795 host->chan_tx = NULL; 796 dma_release_channel(chan); 797 } 798 dev_warn(&host->pdev->dev, 799 "DMA failed: %d, falling back to PIO\n", ret); 800 tmio_mmc_enable_dma(host, false); 801 } 802 803 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 804 desc, cookie, host->sg_len); 805} 806 807static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host) 808{ 809 struct scatterlist *sg = host->sg_ptr, *sg_tmp; 810 struct dma_async_tx_descriptor *desc = NULL; 811 struct dma_chan *chan = host->chan_tx; 812 struct mfd_cell *cell = host->pdev->dev.platform_data; 813 struct tmio_mmc_data *pdata = cell->driver_data; 814 dma_cookie_t cookie; 815 int ret, i; 816 bool aligned = true, multiple = true; 817 unsigned int align = (1 << pdata->dma->alignment_shift) - 1; 818 819 for_each_sg(sg, sg_tmp, host->sg_len, i) { 820 if (sg_tmp->offset & align) 821 aligned = false; 822 if (sg_tmp->length & align) { 823 multiple = false; 824 break; 825 } 826 } 827 828 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE || 829 align >= MAX_ALIGN)) || !multiple) { 830 ret = -EINVAL; 831 goto pio; 832 } 833 834 /* The only sg element can be unaligned, use our bounce buffer then */ 835 if (!aligned) { 836 unsigned long flags; 837 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags); 838 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length); 839 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length); 840 tmio_mmc_kunmap_atomic(sg_vaddr, &flags); 841 host->sg_ptr = &host->bounce_sg; 842 sg = host->sg_ptr; 843 } 844 845 ret = dma_map_sg(&host->pdev->dev, sg, host->sg_len, DMA_TO_DEVICE); 846 if (ret > 0) { 847 host->dma_sglen = ret; 848 desc = chan->device->device_prep_slave_sg(chan, sg, ret, 849 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 850 } 851 852 if (desc) { 853 desc->callback = tmio_dma_complete; 854 desc->callback_param = host; 855 cookie = desc->tx_submit(desc); 856 if (cookie < 0) { 857 desc = NULL; 858 ret = cookie; 859 } 860 } 861 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n", 862 __func__, host->sg_len, ret, cookie, host->mrq); 863 864pio: 865 if (!desc) { 866 /* DMA failed, fall back to PIO */ 867 if (ret >= 0) 868 ret = -EIO; 869 host->chan_tx = NULL; 870 dma_release_channel(chan); 871 /* Free the Rx channel too */ 872 chan = host->chan_rx; 873 if (chan) { 874 host->chan_rx = NULL; 875 dma_release_channel(chan); 876 } 877 dev_warn(&host->pdev->dev, 878 "DMA failed: %d, falling back to PIO\n", ret); 879 tmio_mmc_enable_dma(host, false); 880 } 881 882 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__, 883 desc, cookie); 884} 885 886static void tmio_mmc_start_dma(struct tmio_mmc_host *host, 887 struct mmc_data *data) 888{ 889 if (data->flags & MMC_DATA_READ) { 890 if (host->chan_rx) 891 tmio_mmc_start_dma_rx(host); 892 } else { 893 if (host->chan_tx) 894 tmio_mmc_start_dma_tx(host); 895 } 896} 897 898static void tmio_issue_tasklet_fn(unsigned long priv) 899{ 900 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv; 901 struct dma_chan *chan = host->chan_tx; 902 903 chan->device->device_issue_pending(chan); 904} 905 906static void tmio_tasklet_fn(unsigned long arg) 907{ 908 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 909 910 if (host->data->flags & MMC_DATA_READ) 911 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen, 912 DMA_FROM_DEVICE); 913 else 914 dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->dma_sglen, 915 DMA_TO_DEVICE); 916 917 tmio_mmc_do_data_irq(host); 918} 919 920/* It might be necessary to make filter MFD specific */ 921static bool tmio_mmc_filter(struct dma_chan *chan, void *arg) 922{ 923 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 924 chan->private = arg; 925 return true; 926} 927 928static void tmio_mmc_request_dma(struct tmio_mmc_host *host, 929 struct tmio_mmc_data *pdata) 930{ 931 /* We can only either use DMA for both Tx and Rx or not use it at all */ 932 if (pdata->dma) { 933 dma_cap_mask_t mask; 934 935 dma_cap_zero(mask); 936 dma_cap_set(DMA_SLAVE, mask); 937 938 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter, 939 pdata->dma->chan_priv_tx); 940 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__, 941 host->chan_tx); 942 943 if (!host->chan_tx) 944 return; 945 946 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter, 947 pdata->dma->chan_priv_rx); 948 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__, 949 host->chan_rx); 950 951 if (!host->chan_rx) { 952 dma_release_channel(host->chan_tx); 953 host->chan_tx = NULL; 954 return; 955 } 956 957 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host); 958 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host); 959 960 tmio_mmc_enable_dma(host, true); 961 } 962} 963 964static void tmio_mmc_release_dma(struct tmio_mmc_host *host) 965{ 966 if (host->chan_tx) { 967 struct dma_chan *chan = host->chan_tx; 968 host->chan_tx = NULL; 969 dma_release_channel(chan); 970 } 971 if (host->chan_rx) { 972 struct dma_chan *chan = host->chan_rx; 973 host->chan_rx = NULL; 974 dma_release_channel(chan); 975 } 976} 977#else 978static void tmio_check_bounce_buffer(struct tmio_mmc_host *host) 979{ 980} 981 982static void tmio_mmc_start_dma(struct tmio_mmc_host *host, 983 struct mmc_data *data) 984{ 985} 986 987static void tmio_mmc_request_dma(struct tmio_mmc_host *host, 988 struct tmio_mmc_data *pdata) 989{ 990 host->chan_tx = NULL; 991 host->chan_rx = NULL; 992} 993 994static void tmio_mmc_release_dma(struct tmio_mmc_host *host) 995{ 996} 997#endif 998 999static int tmio_mmc_start_data(struct tmio_mmc_host *host, 1000 struct mmc_data *data) 1001{ 1002 struct mfd_cell *cell = host->pdev->dev.platform_data; 1003 struct tmio_mmc_data *pdata = cell->driver_data; 1004 1005 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n", 1006 data->blksz, data->blocks); 1007 1008 /* Some hardware cannot perform 2 byte requests in 4 bit mode */ 1009 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) { 1010 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES; 1011 1012 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) { 1013 pr_err("%s: %d byte block unsupported in 4 bit mode\n", 1014 mmc_hostname(host->mmc), data->blksz); 1015 return -EINVAL; 1016 } 1017 } 1018 1019 tmio_mmc_init_sg(host, data); 1020 host->data = data; 1021 1022 /* Set transfer length / blocksize */ 1023 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz); 1024 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks); 1025 1026 tmio_mmc_start_dma(host, data); 1027 1028 return 0; 1029} 1030 1031/* Process requests from the MMC layer */ 1032static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 1033{ 1034 struct tmio_mmc_host *host = mmc_priv(mmc); 1035 int ret; 1036 1037 if (host->mrq) 1038 pr_debug("request not null\n"); 1039 1040 host->mrq = mrq; 1041 1042 if (mrq->data) { 1043 ret = tmio_mmc_start_data(host, mrq->data); 1044 if (ret) 1045 goto fail; 1046 } 1047 1048 ret = tmio_mmc_start_command(host, mrq->cmd); 1049 if (!ret) 1050 return; 1051 1052fail: 1053 mrq->cmd->error = ret; 1054 mmc_request_done(mmc, mrq); 1055} 1056 1057/* Set MMC clock / power. 1058 * Note: This controller uses a simple divider scheme therefore it cannot 1059 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as 1060 * MMC wont run that fast, it has to be clocked at 12MHz which is the next 1061 * slowest setting. 1062 */ 1063static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1064{ 1065 struct tmio_mmc_host *host = mmc_priv(mmc); 1066 1067 if (ios->clock) 1068 tmio_mmc_set_clock(host, ios->clock); 1069 1070 /* Power sequence - OFF -> ON -> UP */ 1071 switch (ios->power_mode) { 1072 case MMC_POWER_OFF: /* power down SD bus */ 1073 if (host->set_pwr) 1074 host->set_pwr(host->pdev, 0); 1075 tmio_mmc_clk_stop(host); 1076 break; 1077 case MMC_POWER_ON: /* power up SD bus */ 1078 if (host->set_pwr) 1079 host->set_pwr(host->pdev, 1); 1080 break; 1081 case MMC_POWER_UP: /* start bus clock */ 1082 tmio_mmc_clk_start(host); 1083 break; 1084 } 1085 1086 switch (ios->bus_width) { 1087 case MMC_BUS_WIDTH_1: 1088 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0); 1089 break; 1090 case MMC_BUS_WIDTH_4: 1091 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0); 1092 break; 1093 } 1094 1095 /* Let things settle. delay taken from winCE driver */ 1096 udelay(140); 1097} 1098 1099static int tmio_mmc_get_ro(struct mmc_host *mmc) 1100{ 1101 struct tmio_mmc_host *host = mmc_priv(mmc); 1102 struct mfd_cell *cell = host->pdev->dev.platform_data; 1103 struct tmio_mmc_data *pdata = cell->driver_data; 1104 1105 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) || 1106 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1; 1107} 1108 1109static int tmio_mmc_get_cd(struct mmc_host *mmc) 1110{ 1111 struct tmio_mmc_host *host = mmc_priv(mmc); 1112 struct mfd_cell *cell = host->pdev->dev.platform_data; 1113 struct tmio_mmc_data *pdata = cell->driver_data; 1114 1115 if (!pdata->get_cd) 1116 return -ENOSYS; 1117 else 1118 return pdata->get_cd(host->pdev); 1119} 1120 1121static const struct mmc_host_ops tmio_mmc_ops = { 1122 .request = tmio_mmc_request, 1123 .set_ios = tmio_mmc_set_ios, 1124 .get_ro = tmio_mmc_get_ro, 1125 .get_cd = tmio_mmc_get_cd, 1126 .enable_sdio_irq = tmio_mmc_enable_sdio_irq, 1127}; 1128 1129#ifdef CONFIG_PM 1130static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state) 1131{ 1132 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 1133 struct mmc_host *mmc = platform_get_drvdata(dev); 1134 int ret; 1135 1136 ret = mmc_suspend_host(mmc); 1137 1138 /* Tell MFD core it can disable us now.*/ 1139 if (!ret && cell->disable) 1140 cell->disable(dev); 1141 1142 return ret; 1143} 1144 1145static int tmio_mmc_resume(struct platform_device *dev) 1146{ 1147 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 1148 struct mmc_host *mmc = platform_get_drvdata(dev); 1149 int ret = 0; 1150 1151 /* Tell the MFD core we are ready to be enabled */ 1152 if (cell->resume) { 1153 ret = cell->resume(dev); 1154 if (ret) 1155 goto out; 1156 } 1157 1158 mmc_resume_host(mmc); 1159 1160out: 1161 return ret; 1162} 1163#else 1164#define tmio_mmc_suspend NULL 1165#define tmio_mmc_resume NULL 1166#endif 1167 1168static int __devinit tmio_mmc_probe(struct platform_device *dev) 1169{ 1170 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 1171 struct tmio_mmc_data *pdata; 1172 struct resource *res_ctl; 1173 struct tmio_mmc_host *host; 1174 struct mmc_host *mmc; 1175 int ret = -EINVAL; 1176 u32 irq_mask = TMIO_MASK_CMD; 1177 1178 if (dev->num_resources != 2) 1179 goto out; 1180 1181 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0); 1182 if (!res_ctl) 1183 goto out; 1184 1185 pdata = cell->driver_data; 1186 if (!pdata || !pdata->hclk) 1187 goto out; 1188 1189 ret = -ENOMEM; 1190 1191 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev); 1192 if (!mmc) 1193 goto out; 1194 1195 host = mmc_priv(mmc); 1196 host->mmc = mmc; 1197 host->pdev = dev; 1198 platform_set_drvdata(dev, mmc); 1199 1200 host->set_pwr = pdata->set_pwr; 1201 host->set_clk_div = pdata->set_clk_div; 1202 1203 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ 1204 host->bus_shift = resource_size(res_ctl) >> 10; 1205 1206 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl)); 1207 if (!host->ctl) 1208 goto host_free; 1209 1210 mmc->ops = &tmio_mmc_ops; 1211 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities; 1212 mmc->f_max = pdata->hclk; 1213 mmc->f_min = mmc->f_max / 512; 1214 mmc->max_segs = 32; 1215 mmc->max_blk_size = 512; 1216 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) * 1217 mmc->max_segs; 1218 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1219 mmc->max_seg_size = mmc->max_req_size; 1220 if (pdata->ocr_mask) 1221 mmc->ocr_avail = pdata->ocr_mask; 1222 else 1223 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1224 1225 /* Tell the MFD core we are ready to be enabled */ 1226 if (cell->enable) { 1227 ret = cell->enable(dev); 1228 if (ret) 1229 goto unmap_ctl; 1230 } 1231 1232 tmio_mmc_clk_stop(host); 1233 reset(host); 1234 1235 ret = platform_get_irq(dev, 0); 1236 if (ret >= 0) 1237 host->irq = ret; 1238 else 1239 goto cell_disable; 1240 1241 disable_mmc_irqs(host, TMIO_MASK_ALL); 1242 if (pdata->flags & TMIO_MMC_SDIO_IRQ) 1243 tmio_mmc_enable_sdio_irq(mmc, 0); 1244 1245 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED | 1246 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host); 1247 if (ret) 1248 goto cell_disable; 1249 1250 /* See if we also get DMA */ 1251 tmio_mmc_request_dma(host, pdata); 1252 1253 mmc_add_host(mmc); 1254 1255 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc), 1256 (unsigned long)host->ctl, host->irq); 1257 1258 /* Unmask the IRQs we want to know about */ 1259 if (!host->chan_rx) 1260 irq_mask |= TMIO_MASK_READOP; 1261 if (!host->chan_tx) 1262 irq_mask |= TMIO_MASK_WRITEOP; 1263 enable_mmc_irqs(host, irq_mask); 1264 1265 return 0; 1266 1267cell_disable: 1268 if (cell->disable) 1269 cell->disable(dev); 1270unmap_ctl: 1271 iounmap(host->ctl); 1272host_free: 1273 mmc_free_host(mmc); 1274out: 1275 return ret; 1276} 1277 1278static int __devexit tmio_mmc_remove(struct platform_device *dev) 1279{ 1280 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data; 1281 struct mmc_host *mmc = platform_get_drvdata(dev); 1282 1283 platform_set_drvdata(dev, NULL); 1284 1285 if (mmc) { 1286 struct tmio_mmc_host *host = mmc_priv(mmc); 1287 mmc_remove_host(mmc); 1288 tmio_mmc_release_dma(host); 1289 free_irq(host->irq, host); 1290 if (cell->disable) 1291 cell->disable(dev); 1292 iounmap(host->ctl); 1293 mmc_free_host(mmc); 1294 } 1295 1296 return 0; 1297} 1298 1299/* ------------------- device registration ----------------------- */ 1300 1301static struct platform_driver tmio_mmc_driver = { 1302 .driver = { 1303 .name = "tmio-mmc", 1304 .owner = THIS_MODULE, 1305 }, 1306 .probe = tmio_mmc_probe, 1307 .remove = __devexit_p(tmio_mmc_remove), 1308 .suspend = tmio_mmc_suspend, 1309 .resume = tmio_mmc_resume, 1310}; 1311 1312 1313static int __init tmio_mmc_init(void) 1314{ 1315 return platform_driver_register(&tmio_mmc_driver); 1316} 1317 1318static void __exit tmio_mmc_exit(void) 1319{ 1320 platform_driver_unregister(&tmio_mmc_driver); 1321} 1322 1323module_init(tmio_mmc_init); 1324module_exit(tmio_mmc_exit); 1325 1326MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver"); 1327MODULE_AUTHOR("Ian Molton <spyro@f2s.com>"); 1328MODULE_LICENSE("GPL v2"); 1329MODULE_ALIAS("platform:tmio-mmc"); 1330