ndfc.c revision 04bbd0eafb0c733c6c7f5d63c5098c615fe0685a 
1/*
2 *  drivers/mtd/ndfc.c
3 *
4 *  Overview:
5 *   Platform independend driver for NDFC (NanD Flash Controller)
6 *   integrated into EP440 cores
7 *
8 *  Author: Thomas Gleixner
9 *
10 *  Copyright 2006 IBM
11 *
12 *  This program is free software; you can redistribute	 it and/or modify it
13 *  under  the terms of	 the GNU General  Public License as published by the
14 *  Free Software Foundation;  either version 2 of the	License, or (at your
15 *  option) any later version.
16 *
17 */
18#include <linux/module.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/nand_ecc.h>
21#include <linux/mtd/partitions.h>
22#include <linux/mtd/ndfc.h>
23#include <linux/mtd/ubi.h>
24#include <linux/mtd/mtd.h>
25#include <linux/platform_device.h>
26
27#include <asm/io.h>
28#include <asm/ibm44x.h>
29
30struct ndfc_nand_mtd {
31	struct mtd_info			mtd;
32	struct nand_chip		chip;
33	struct platform_nand_chip	*pl_chip;
34};
35
36static struct ndfc_nand_mtd ndfc_mtd[NDFC_MAX_BANKS];
37
38struct ndfc_controller {
39	void __iomem		*ndfcbase;
40	struct nand_hw_control	ndfc_control;
41	atomic_t		childs_active;
42};
43
44static struct ndfc_controller ndfc_ctrl;
45
46static void ndfc_select_chip(struct mtd_info *mtd, int chip)
47{
48	uint32_t ccr;
49	struct ndfc_controller *ndfc = &ndfc_ctrl;
50	struct nand_chip *nandchip = mtd->priv;
51	struct ndfc_nand_mtd *nandmtd = nandchip->priv;
52	struct platform_nand_chip *pchip = nandmtd->pl_chip;
53
54	ccr = __raw_readl(ndfc->ndfcbase + NDFC_CCR);
55	if (chip >= 0) {
56		ccr &= ~NDFC_CCR_BS_MASK;
57		ccr |= NDFC_CCR_BS(chip + pchip->chip_offset);
58	} else
59		ccr |= NDFC_CCR_RESET_CE;
60	writel(ccr, ndfc->ndfcbase + NDFC_CCR);
61}
62
63static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
64{
65	struct nand_chip *chip = mtd->priv;
66
67	if (cmd == NAND_CMD_NONE)
68		return;
69
70	if (ctrl & NAND_CLE)
71		writel(cmd & 0xFF, chip->IO_ADDR_W + NDFC_CMD);
72	else
73		writel(cmd & 0xFF, chip->IO_ADDR_W + NDFC_ALE);
74}
75
76static int ndfc_ready(struct mtd_info *mtd)
77{
78	struct ndfc_controller *ndfc = &ndfc_ctrl;
79
80	return __raw_readl(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
81}
82
83static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
84{
85	uint32_t ccr;
86	struct ndfc_controller *ndfc = &ndfc_ctrl;
87
88	ccr = __raw_readl(ndfc->ndfcbase + NDFC_CCR);
89	ccr |= NDFC_CCR_RESET_ECC;
90	__raw_writel(ccr, ndfc->ndfcbase + NDFC_CCR);
91	wmb();
92}
93
94static int ndfc_calculate_ecc(struct mtd_info *mtd,
95			      const u_char *dat, u_char *ecc_code)
96{
97	struct ndfc_controller *ndfc = &ndfc_ctrl;
98	uint32_t ecc;
99	uint8_t *p = (uint8_t *)&ecc;
100
101	wmb();
102	ecc = __raw_readl(ndfc->ndfcbase + NDFC_ECC);
103	ecc_code[0] = p[1];
104	ecc_code[1] = p[2];
105	ecc_code[2] = p[3];
106
107	return 0;
108}
109
110/*
111 * Speedups for buffer read/write/verify
112 *
113 * NDFC allows 32bit read/write of data. So we can speed up the buffer
114 * functions. No further checking, as nand_base will always read/write
115 * page aligned.
116 */
117static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
118{
119	struct ndfc_controller *ndfc = &ndfc_ctrl;
120	uint32_t *p = (uint32_t *) buf;
121
122	for(;len > 0; len -= 4)
123		*p++ = __raw_readl(ndfc->ndfcbase + NDFC_DATA);
124}
125
126static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
127{
128	struct ndfc_controller *ndfc = &ndfc_ctrl;
129	uint32_t *p = (uint32_t *) buf;
130
131	for(;len > 0; len -= 4)
132		__raw_writel(*p++, ndfc->ndfcbase + NDFC_DATA);
133}
134
135static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
136{
137	struct ndfc_controller *ndfc = &ndfc_ctrl;
138	uint32_t *p = (uint32_t *) buf;
139
140	for(;len > 0; len -= 4)
141		if (*p++ != __raw_readl(ndfc->ndfcbase + NDFC_DATA))
142			return -EFAULT;
143	return 0;
144}
145
146/*
147 * Initialize chip structure
148 */
149static void ndfc_chip_init(struct ndfc_nand_mtd *mtd)
150{
151	struct ndfc_controller *ndfc = &ndfc_ctrl;
152	struct nand_chip *chip = &mtd->chip;
153
154	chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
155	chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
156	chip->cmd_ctrl = ndfc_hwcontrol;
157	chip->dev_ready = ndfc_ready;
158	chip->select_chip = ndfc_select_chip;
159	chip->chip_delay = 50;
160	chip->priv = mtd;
161	chip->options = mtd->pl_chip->options;
162	chip->controller = &ndfc->ndfc_control;
163	chip->read_buf = ndfc_read_buf;
164	chip->write_buf = ndfc_write_buf;
165	chip->verify_buf = ndfc_verify_buf;
166	chip->ecc.correct = nand_correct_data;
167	chip->ecc.hwctl = ndfc_enable_hwecc;
168	chip->ecc.calculate = ndfc_calculate_ecc;
169	chip->ecc.mode = NAND_ECC_HW;
170	chip->ecc.size = 256;
171	chip->ecc.bytes = 3;
172	chip->autooob = mtd->pl_chip->autooob;
173	mtd->mtd.priv = chip;
174	mtd->mtd.owner = THIS_MODULE;
175}
176
177static int ndfc_chip_probe(struct platform_device *pdev)
178{
179	int rc;
180	struct platform_nand_chip *nc = pdev->dev.platform_data;
181	struct ndfc_chip_settings *settings = nc->priv;
182	struct ndfc_controller *ndfc = &ndfc_ctrl;
183	struct ndfc_nand_mtd *nandmtd;
184
185	if (nc->chip_offset >= NDFC_MAX_BANKS || nc->nr_chips > NDFC_MAX_BANKS)
186		return -EINVAL;
187
188	/* Set the bank settings */
189	__raw_writel(settings->bank_settings,
190		     ndfc->ndfcbase + NDFC_BCFG0 + (nc->chip_offset << 2));
191
192	nandmtd = &ndfc_mtd[pdev->id];
193	if (nandmtd->pl_chip)
194		return -EBUSY;
195
196	nandmtd->pl_chip = nc;
197	ndfc_chip_init(nandmtd);
198
199	/* Scan for chips */
200	if (nand_scan(&nandmtd->mtd, nc->nr_chips)) {
201		nandmtd->pl_chip = NULL;
202		return -ENODEV;
203	}
204
205#ifdef CONFIG_MTD_PARTITIONS
206	printk("Number of partitions %d\n", nc->nr_partitions);
207	if (nc->nr_partitions) {
208		struct mtd_info *mtd_ubi;
209		nc->partitions[NAND_PARTS_CONTENT_IDX].mtdp = &mtd_ubi;
210
211		add_mtd_device(&nandmtd->mtd); /* for testing */
212		add_mtd_partitions(&nandmtd->mtd,
213				   nc->partitions,
214				   nc->nr_partitions);
215
216		add_mtd_device(mtd_ubi);
217
218	} else
219#else
220		add_mtd_device(&nandmtd->mtd);
221#endif
222
223	atomic_inc(&ndfc->childs_active);
224	return 0;
225}
226
227static int ndfc_chip_remove(struct platform_device *pdev)
228{
229	return 0;
230}
231
232static int ndfc_nand_probe(struct platform_device *pdev)
233{
234	struct platform_nand_ctrl *nc = pdev->dev.platform_data;
235	struct ndfc_controller_settings *settings = nc->priv;
236	struct resource *res = pdev->resource;
237	struct ndfc_controller *ndfc = &ndfc_ctrl;
238	unsigned long long phys = NDFC_PHYSADDR_OFFS | res->start;
239
240	ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1);
241	if (!ndfc->ndfcbase) {
242		printk(KERN_ERR "NDFC: ioremap failed\n");
243		return -EIO;
244	}
245
246	__raw_writel(settings->ccr_settings, ndfc->ndfcbase + NDFC_CCR);
247
248	spin_lock_init(&ndfc->ndfc_control.lock);
249	init_waitqueue_head(&ndfc->ndfc_control.wq);
250
251	platform_set_drvdata(pdev, ndfc);
252
253	printk("NDFC NAND Driver initialized. Chip-Rev: 0x%08x\n",
254	       __raw_readl(ndfc->ndfcbase + NDFC_REVID));
255
256	return 0;
257}
258
259static int ndfc_nand_remove(struct platform_device *pdev)
260{
261	struct ndfc_controller *ndfc = platform_get_drvdata(pdev);
262
263	if (atomic_read(&ndfc->childs_active))
264		return -EBUSY;
265
266	if (ndfc) {
267		platform_set_drvdata(pdev, NULL);
268		iounmap(ndfc_ctrl.ndfcbase);
269		ndfc_ctrl.ndfcbase = NULL;
270	}
271	return 0;
272}
273
274/* driver device registration */
275
276static struct platform_driver ndfc_chip_driver = {
277	.probe		= ndfc_chip_probe,
278	.remove		= ndfc_chip_remove,
279	.driver		= {
280		.name	= "ndfc-chip",
281		.owner	= THIS_MODULE,
282	},
283};
284
285static struct platform_driver ndfc_nand_driver = {
286	.probe		= ndfc_nand_probe,
287	.remove		= ndfc_nand_remove,
288	.driver		= {
289		.name	= "ndfc-nand",
290		.owner	= THIS_MODULE,
291	},
292};
293
294static int __init ndfc_nand_init(void)
295{
296	int ret;
297
298	spin_lock_init(&ndfc_ctrl.ndfc_control.lock);
299	init_waitqueue_head(&ndfc_ctrl.ndfc_control.wq);
300
301	ret = platform_driver_register(&ndfc_nand_driver);
302	if (!ret)
303		ret = platform_driver_register(&ndfc_chip_driver);
304	return ret;
305}
306
307static void __exit ndfc_nand_exit(void)
308{
309	platform_driver_unregister(&ndfc_chip_driver);
310	platform_driver_unregister(&ndfc_nand_driver);
311}
312
313module_init(ndfc_nand_init);
314module_exit(ndfc_nand_exit);
315
316MODULE_LICENSE("GPL");
317MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
318MODULE_DESCRIPTION("Platform driver for NDFC");
319