at91_can.c revision 07a648e668aa7f7c94d41d8d2e4ad53b609e391d
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/rtnetlink.h> 34#include <linux/skbuff.h> 35#include <linux/spinlock.h> 36#include <linux/string.h> 37#include <linux/types.h> 38 39#include <linux/can/dev.h> 40#include <linux/can/error.h> 41 42#include <mach/board.h> 43 44#define AT91_MB_MASK(i) ((1 << (i)) - 1) 45 46/* Common registers */ 47enum at91_reg { 48 AT91_MR = 0x000, 49 AT91_IER = 0x004, 50 AT91_IDR = 0x008, 51 AT91_IMR = 0x00C, 52 AT91_SR = 0x010, 53 AT91_BR = 0x014, 54 AT91_TIM = 0x018, 55 AT91_TIMESTP = 0x01C, 56 AT91_ECR = 0x020, 57 AT91_TCR = 0x024, 58 AT91_ACR = 0x028, 59}; 60 61/* Mailbox registers (0 <= i <= 15) */ 62#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 63#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 64#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 65#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 66#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 67#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 68#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 69#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 70 71/* Register bits */ 72#define AT91_MR_CANEN BIT(0) 73#define AT91_MR_LPM BIT(1) 74#define AT91_MR_ABM BIT(2) 75#define AT91_MR_OVL BIT(3) 76#define AT91_MR_TEOF BIT(4) 77#define AT91_MR_TTM BIT(5) 78#define AT91_MR_TIMFRZ BIT(6) 79#define AT91_MR_DRPT BIT(7) 80 81#define AT91_SR_RBSY BIT(29) 82 83#define AT91_MMR_PRIO_SHIFT (16) 84 85#define AT91_MID_MIDE BIT(29) 86 87#define AT91_MSR_MRTR BIT(20) 88#define AT91_MSR_MABT BIT(22) 89#define AT91_MSR_MRDY BIT(23) 90#define AT91_MSR_MMI BIT(24) 91 92#define AT91_MCR_MRTR BIT(20) 93#define AT91_MCR_MTCR BIT(23) 94 95/* Mailbox Modes */ 96enum at91_mb_mode { 97 AT91_MB_MODE_DISABLED = 0, 98 AT91_MB_MODE_RX = 1, 99 AT91_MB_MODE_RX_OVRWR = 2, 100 AT91_MB_MODE_TX = 3, 101 AT91_MB_MODE_CONSUMER = 4, 102 AT91_MB_MODE_PRODUCER = 5, 103}; 104 105/* Interrupt mask bits */ 106#define AT91_IRQ_ERRA (1 << 16) 107#define AT91_IRQ_WARN (1 << 17) 108#define AT91_IRQ_ERRP (1 << 18) 109#define AT91_IRQ_BOFF (1 << 19) 110#define AT91_IRQ_SLEEP (1 << 20) 111#define AT91_IRQ_WAKEUP (1 << 21) 112#define AT91_IRQ_TOVF (1 << 22) 113#define AT91_IRQ_TSTP (1 << 23) 114#define AT91_IRQ_CERR (1 << 24) 115#define AT91_IRQ_SERR (1 << 25) 116#define AT91_IRQ_AERR (1 << 26) 117#define AT91_IRQ_FERR (1 << 27) 118#define AT91_IRQ_BERR (1 << 28) 119 120#define AT91_IRQ_ERR_ALL (0x1fff0000) 121#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 122 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 123#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 124 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 125 126#define AT91_IRQ_ALL (0x1fffffff) 127 128enum at91_devtype { 129 AT91_DEVTYPE_SAM9263, 130}; 131 132struct at91_devtype_data { 133 unsigned int rx_first; 134 unsigned int rx_split; 135 unsigned int rx_last; 136 unsigned int tx_shift; 137 enum at91_devtype type; 138}; 139 140struct at91_priv { 141 struct can_priv can; /* must be the first member! */ 142 struct net_device *dev; 143 struct napi_struct napi; 144 145 void __iomem *reg_base; 146 147 u32 reg_sr; 148 unsigned int tx_next; 149 unsigned int tx_echo; 150 unsigned int rx_next; 151 struct at91_devtype_data devtype_data; 152 153 struct clk *clk; 154 struct at91_can_data *pdata; 155 156 canid_t mb0_id; 157}; 158 159static const struct at91_devtype_data at91_devtype_data[] __devinitconst = { 160 [AT91_DEVTYPE_SAM9263] = { 161 .rx_first = 1, 162 .rx_split = 8, 163 .rx_last = 11, 164 .tx_shift = 2, 165 }, 166}; 167 168static struct can_bittiming_const at91_bittiming_const = { 169 .name = KBUILD_MODNAME, 170 .tseg1_min = 4, 171 .tseg1_max = 16, 172 .tseg2_min = 2, 173 .tseg2_max = 8, 174 .sjw_max = 4, 175 .brp_min = 2, 176 .brp_max = 128, 177 .brp_inc = 1, 178}; 179 180#define AT91_IS(_model) \ 181static inline int at91_is_sam##_model(const struct at91_priv *priv) \ 182{ \ 183 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 184} 185 186AT91_IS(9263); 187 188static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 189{ 190 return priv->devtype_data.rx_first; 191} 192 193static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 194{ 195 return priv->devtype_data.rx_last; 196} 197 198static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 199{ 200 return priv->devtype_data.rx_split; 201} 202 203static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 204{ 205 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 206} 207 208static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 209{ 210 return get_mb_rx_split(priv) - 1; 211} 212 213static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 214{ 215 return AT91_MB_MASK(get_mb_rx_split(priv)) & 216 ~AT91_MB_MASK(get_mb_rx_first(priv)); 217} 218 219static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 220{ 221 return priv->devtype_data.tx_shift; 222} 223 224static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 225{ 226 return 1 << get_mb_tx_shift(priv); 227} 228 229static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 230{ 231 return get_mb_rx_last(priv) + 1; 232} 233 234static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 235{ 236 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 237} 238 239static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 240{ 241 return get_mb_tx_shift(priv); 242} 243 244static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 245{ 246 return 0xf << get_mb_tx_shift(priv); 247} 248 249static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 250{ 251 return AT91_MB_MASK(get_mb_tx_shift(priv)); 252} 253 254static inline unsigned int get_next_mask(const struct at91_priv *priv) 255{ 256 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 257} 258 259static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 260{ 261 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 262 ~AT91_MB_MASK(get_mb_rx_first(priv)); 263} 264 265static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 266{ 267 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 268 ~AT91_MB_MASK(get_mb_tx_first(priv)); 269} 270 271static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 272{ 273 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 274} 275 276static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 277{ 278 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 279} 280 281static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 282{ 283 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 284} 285 286static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 287{ 288 return __raw_readl(priv->reg_base + reg); 289} 290 291static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 292 u32 value) 293{ 294 __raw_writel(value, priv->reg_base + reg); 295} 296 297static inline void set_mb_mode_prio(const struct at91_priv *priv, 298 unsigned int mb, enum at91_mb_mode mode, int prio) 299{ 300 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 301} 302 303static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 304 enum at91_mb_mode mode) 305{ 306 set_mb_mode_prio(priv, mb, mode, 0); 307} 308 309static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 310{ 311 u32 reg_mid; 312 313 if (can_id & CAN_EFF_FLAG) 314 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 315 else 316 reg_mid = (can_id & CAN_SFF_MASK) << 18; 317 318 return reg_mid; 319} 320 321/* 322 * Swtich transceiver on or off 323 */ 324static void at91_transceiver_switch(const struct at91_priv *priv, int on) 325{ 326 if (priv->pdata && priv->pdata->transceiver_switch) 327 priv->pdata->transceiver_switch(on); 328} 329 330static void at91_setup_mailboxes(struct net_device *dev) 331{ 332 struct at91_priv *priv = netdev_priv(dev); 333 unsigned int i; 334 u32 reg_mid; 335 336 /* 337 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 338 * mailbox is disabled. The next 11 mailboxes are used as a 339 * reception FIFO. The last mailbox is configured with 340 * overwrite option. The overwrite flag indicates a FIFO 341 * overflow. 342 */ 343 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 344 for (i = 0; i < get_mb_rx_first(priv); i++) { 345 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 346 at91_write(priv, AT91_MID(i), reg_mid); 347 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 348 } 349 350 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 351 set_mb_mode(priv, i, AT91_MB_MODE_RX); 352 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 353 354 /* reset acceptance mask and id register */ 355 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 356 at91_write(priv, AT91_MAM(i), 0x0); 357 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 358 } 359 360 /* The last 4 mailboxes are used for transmitting. */ 361 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 362 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 363 364 /* Reset tx and rx helper pointers */ 365 priv->tx_next = priv->tx_echo = 0; 366 priv->rx_next = get_mb_rx_first(priv); 367} 368 369static int at91_set_bittiming(struct net_device *dev) 370{ 371 const struct at91_priv *priv = netdev_priv(dev); 372 const struct can_bittiming *bt = &priv->can.bittiming; 373 u32 reg_br; 374 375 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 376 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 377 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 378 ((bt->phase_seg2 - 1) << 0); 379 380 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 381 382 at91_write(priv, AT91_BR, reg_br); 383 384 return 0; 385} 386 387static int at91_get_berr_counter(const struct net_device *dev, 388 struct can_berr_counter *bec) 389{ 390 const struct at91_priv *priv = netdev_priv(dev); 391 u32 reg_ecr = at91_read(priv, AT91_ECR); 392 393 bec->rxerr = reg_ecr & 0xff; 394 bec->txerr = reg_ecr >> 16; 395 396 return 0; 397} 398 399static void at91_chip_start(struct net_device *dev) 400{ 401 struct at91_priv *priv = netdev_priv(dev); 402 u32 reg_mr, reg_ier; 403 404 /* disable interrupts */ 405 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 406 407 /* disable chip */ 408 reg_mr = at91_read(priv, AT91_MR); 409 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 410 411 at91_set_bittiming(dev); 412 at91_setup_mailboxes(dev); 413 at91_transceiver_switch(priv, 1); 414 415 /* enable chip */ 416 at91_write(priv, AT91_MR, AT91_MR_CANEN); 417 418 priv->can.state = CAN_STATE_ERROR_ACTIVE; 419 420 /* Enable interrupts */ 421 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 422 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 423 at91_write(priv, AT91_IER, reg_ier); 424} 425 426static void at91_chip_stop(struct net_device *dev, enum can_state state) 427{ 428 struct at91_priv *priv = netdev_priv(dev); 429 u32 reg_mr; 430 431 /* disable interrupts */ 432 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 433 434 reg_mr = at91_read(priv, AT91_MR); 435 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 436 437 at91_transceiver_switch(priv, 0); 438 priv->can.state = state; 439} 440 441/* 442 * theory of operation: 443 * 444 * According to the datasheet priority 0 is the highest priority, 15 445 * is the lowest. If two mailboxes have the same priority level the 446 * message of the mailbox with the lowest number is sent first. 447 * 448 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 449 * the next mailbox with prio 0, and so on, until all mailboxes are 450 * used. Then we start from the beginning with mailbox 451 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 452 * prio 1. When we reach the last mailbox with prio 15, we have to 453 * stop sending, waiting for all messages to be delivered, then start 454 * again with mailbox AT91_MB_TX_FIRST prio 0. 455 * 456 * We use the priv->tx_next as counter for the next transmission 457 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 458 * encode the mailbox number, the upper 4 bits the mailbox priority: 459 * 460 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 461 * (mb - get_mb_tx_first(priv)); 462 * 463 */ 464static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 465{ 466 struct at91_priv *priv = netdev_priv(dev); 467 struct net_device_stats *stats = &dev->stats; 468 struct can_frame *cf = (struct can_frame *)skb->data; 469 unsigned int mb, prio; 470 u32 reg_mid, reg_mcr; 471 472 if (can_dropped_invalid_skb(dev, skb)) 473 return NETDEV_TX_OK; 474 475 mb = get_tx_next_mb(priv); 476 prio = get_tx_next_prio(priv); 477 478 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 479 netif_stop_queue(dev); 480 481 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 482 return NETDEV_TX_BUSY; 483 } 484 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 485 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 486 (cf->can_dlc << 16) | AT91_MCR_MTCR; 487 488 /* disable MB while writing ID (see datasheet) */ 489 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 490 at91_write(priv, AT91_MID(mb), reg_mid); 491 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 492 493 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 494 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 495 496 /* This triggers transmission */ 497 at91_write(priv, AT91_MCR(mb), reg_mcr); 498 499 stats->tx_bytes += cf->can_dlc; 500 501 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 502 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv)); 503 504 /* 505 * we have to stop the queue and deliver all messages in case 506 * of a prio+mb counter wrap around. This is the case if 507 * tx_next buffer prio and mailbox equals 0. 508 * 509 * also stop the queue if next buffer is still in use 510 * (== not ready) 511 */ 512 priv->tx_next++; 513 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 514 AT91_MSR_MRDY) || 515 (priv->tx_next & get_next_mask(priv)) == 0) 516 netif_stop_queue(dev); 517 518 /* Enable interrupt for this mailbox */ 519 at91_write(priv, AT91_IER, 1 << mb); 520 521 return NETDEV_TX_OK; 522} 523 524/** 525 * at91_activate_rx_low - activate lower rx mailboxes 526 * @priv: a91 context 527 * 528 * Reenables the lower mailboxes for reception of new CAN messages 529 */ 530static inline void at91_activate_rx_low(const struct at91_priv *priv) 531{ 532 u32 mask = get_mb_rx_low_mask(priv); 533 at91_write(priv, AT91_TCR, mask); 534} 535 536/** 537 * at91_activate_rx_mb - reactive single rx mailbox 538 * @priv: a91 context 539 * @mb: mailbox to reactivate 540 * 541 * Reenables given mailbox for reception of new CAN messages 542 */ 543static inline void at91_activate_rx_mb(const struct at91_priv *priv, 544 unsigned int mb) 545{ 546 u32 mask = 1 << mb; 547 at91_write(priv, AT91_TCR, mask); 548} 549 550/** 551 * at91_rx_overflow_err - send error frame due to rx overflow 552 * @dev: net device 553 */ 554static void at91_rx_overflow_err(struct net_device *dev) 555{ 556 struct net_device_stats *stats = &dev->stats; 557 struct sk_buff *skb; 558 struct can_frame *cf; 559 560 netdev_dbg(dev, "RX buffer overflow\n"); 561 stats->rx_over_errors++; 562 stats->rx_errors++; 563 564 skb = alloc_can_err_skb(dev, &cf); 565 if (unlikely(!skb)) 566 return; 567 568 cf->can_id |= CAN_ERR_CRTL; 569 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 570 netif_receive_skb(skb); 571 572 stats->rx_packets++; 573 stats->rx_bytes += cf->can_dlc; 574} 575 576/** 577 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 578 * @dev: net device 579 * @mb: mailbox number to read from 580 * @cf: can frame where to store message 581 * 582 * Reads a CAN message from the given mailbox and stores data into 583 * given can frame. "mb" and "cf" must be valid. 584 */ 585static void at91_read_mb(struct net_device *dev, unsigned int mb, 586 struct can_frame *cf) 587{ 588 const struct at91_priv *priv = netdev_priv(dev); 589 u32 reg_msr, reg_mid; 590 591 reg_mid = at91_read(priv, AT91_MID(mb)); 592 if (reg_mid & AT91_MID_MIDE) 593 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 594 else 595 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 596 597 reg_msr = at91_read(priv, AT91_MSR(mb)); 598 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 599 600 if (reg_msr & AT91_MSR_MRTR) 601 cf->can_id |= CAN_RTR_FLAG; 602 else { 603 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 604 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 605 } 606 607 /* allow RX of extended frames */ 608 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 609 610 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 611 at91_rx_overflow_err(dev); 612} 613 614/** 615 * at91_read_msg - read CAN message from mailbox 616 * @dev: net device 617 * @mb: mail box to read from 618 * 619 * Reads a CAN message from given mailbox, and put into linux network 620 * RX queue, does all housekeeping chores (stats, ...) 621 */ 622static void at91_read_msg(struct net_device *dev, unsigned int mb) 623{ 624 struct net_device_stats *stats = &dev->stats; 625 struct can_frame *cf; 626 struct sk_buff *skb; 627 628 skb = alloc_can_skb(dev, &cf); 629 if (unlikely(!skb)) { 630 stats->rx_dropped++; 631 return; 632 } 633 634 at91_read_mb(dev, mb, cf); 635 netif_receive_skb(skb); 636 637 stats->rx_packets++; 638 stats->rx_bytes += cf->can_dlc; 639} 640 641/** 642 * at91_poll_rx - read multiple CAN messages from mailboxes 643 * @dev: net device 644 * @quota: max number of pkgs we're allowed to receive 645 * 646 * Theory of Operation: 647 * 648 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 649 * on the chip are reserved for RX. We split them into 2 groups. The 650 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 651 * 652 * Like it or not, but the chip always saves a received CAN message 653 * into the first free mailbox it finds (starting with the 654 * lowest). This makes it very difficult to read the messages in the 655 * right order from the chip. This is how we work around that problem: 656 * 657 * The first message goes into mb nr. 1 and issues an interrupt. All 658 * rx ints are disabled in the interrupt handler and a napi poll is 659 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 660 * receive another message). 661 * 662 * lower mbxs upper 663 * ____^______ __^__ 664 * / \ / \ 665 * +-+-+-+-+-+-+-+-++-+-+-+-+ 666 * | |x|x|x|x|x|x|x|| | | | | 667 * +-+-+-+-+-+-+-+-++-+-+-+-+ 668 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 669 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 670 * ^ 671 * | 672 * \ 673 * unused, due to chip bug 674 * 675 * The variable priv->rx_next points to the next mailbox to read a 676 * message from. As long we're in the lower mailboxes we just read the 677 * mailbox but not reenable it. 678 * 679 * With completion of the last of the lower mailboxes, we reenable the 680 * whole first group, but continue to look for filled mailboxes in the 681 * upper mailboxes. Imagine the second group like overflow mailboxes, 682 * which takes CAN messages if the lower goup is full. While in the 683 * upper group we reenable the mailbox right after reading it. Giving 684 * the chip more room to store messages. 685 * 686 * After finishing we look again in the lower group if we've still 687 * quota. 688 * 689 */ 690static int at91_poll_rx(struct net_device *dev, int quota) 691{ 692 struct at91_priv *priv = netdev_priv(dev); 693 u32 reg_sr = at91_read(priv, AT91_SR); 694 const unsigned long *addr = (unsigned long *)®_sr; 695 unsigned int mb; 696 int received = 0; 697 698 if (priv->rx_next > get_mb_rx_low_last(priv) && 699 reg_sr & get_mb_rx_low_mask(priv)) 700 netdev_info(dev, 701 "order of incoming frames cannot be guaranteed\n"); 702 703 again: 704 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 705 mb < get_mb_tx_first(priv) && quota > 0; 706 reg_sr = at91_read(priv, AT91_SR), 707 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 708 at91_read_msg(dev, mb); 709 710 /* reactivate mailboxes */ 711 if (mb == get_mb_rx_low_last(priv)) 712 /* all lower mailboxed, if just finished it */ 713 at91_activate_rx_low(priv); 714 else if (mb > get_mb_rx_low_last(priv)) 715 /* only the mailbox we read */ 716 at91_activate_rx_mb(priv, mb); 717 718 received++; 719 quota--; 720 } 721 722 /* upper group completed, look again in lower */ 723 if (priv->rx_next > get_mb_rx_low_last(priv) && 724 quota > 0 && mb > get_mb_rx_last(priv)) { 725 priv->rx_next = get_mb_rx_first(priv); 726 goto again; 727 } 728 729 return received; 730} 731 732static void at91_poll_err_frame(struct net_device *dev, 733 struct can_frame *cf, u32 reg_sr) 734{ 735 struct at91_priv *priv = netdev_priv(dev); 736 737 /* CRC error */ 738 if (reg_sr & AT91_IRQ_CERR) { 739 netdev_dbg(dev, "CERR irq\n"); 740 dev->stats.rx_errors++; 741 priv->can.can_stats.bus_error++; 742 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 743 } 744 745 /* Stuffing Error */ 746 if (reg_sr & AT91_IRQ_SERR) { 747 netdev_dbg(dev, "SERR irq\n"); 748 dev->stats.rx_errors++; 749 priv->can.can_stats.bus_error++; 750 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 751 cf->data[2] |= CAN_ERR_PROT_STUFF; 752 } 753 754 /* Acknowledgement Error */ 755 if (reg_sr & AT91_IRQ_AERR) { 756 netdev_dbg(dev, "AERR irq\n"); 757 dev->stats.tx_errors++; 758 cf->can_id |= CAN_ERR_ACK; 759 } 760 761 /* Form error */ 762 if (reg_sr & AT91_IRQ_FERR) { 763 netdev_dbg(dev, "FERR irq\n"); 764 dev->stats.rx_errors++; 765 priv->can.can_stats.bus_error++; 766 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 767 cf->data[2] |= CAN_ERR_PROT_FORM; 768 } 769 770 /* Bit Error */ 771 if (reg_sr & AT91_IRQ_BERR) { 772 netdev_dbg(dev, "BERR irq\n"); 773 dev->stats.tx_errors++; 774 priv->can.can_stats.bus_error++; 775 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 776 cf->data[2] |= CAN_ERR_PROT_BIT; 777 } 778} 779 780static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 781{ 782 struct sk_buff *skb; 783 struct can_frame *cf; 784 785 if (quota == 0) 786 return 0; 787 788 skb = alloc_can_err_skb(dev, &cf); 789 if (unlikely(!skb)) 790 return 0; 791 792 at91_poll_err_frame(dev, cf, reg_sr); 793 netif_receive_skb(skb); 794 795 dev->stats.rx_packets++; 796 dev->stats.rx_bytes += cf->can_dlc; 797 798 return 1; 799} 800 801static int at91_poll(struct napi_struct *napi, int quota) 802{ 803 struct net_device *dev = napi->dev; 804 const struct at91_priv *priv = netdev_priv(dev); 805 u32 reg_sr = at91_read(priv, AT91_SR); 806 int work_done = 0; 807 808 if (reg_sr & get_irq_mb_rx(priv)) 809 work_done += at91_poll_rx(dev, quota - work_done); 810 811 /* 812 * The error bits are clear on read, 813 * so use saved value from irq handler. 814 */ 815 reg_sr |= priv->reg_sr; 816 if (reg_sr & AT91_IRQ_ERR_FRAME) 817 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 818 819 if (work_done < quota) { 820 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 821 u32 reg_ier = AT91_IRQ_ERR_FRAME; 822 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 823 824 napi_complete(napi); 825 at91_write(priv, AT91_IER, reg_ier); 826 } 827 828 return work_done; 829} 830 831/* 832 * theory of operation: 833 * 834 * priv->tx_echo holds the number of the oldest can_frame put for 835 * transmission into the hardware, but not yet ACKed by the CAN tx 836 * complete IRQ. 837 * 838 * We iterate from priv->tx_echo to priv->tx_next and check if the 839 * packet has been transmitted, echo it back to the CAN framework. If 840 * we discover a not yet transmitted package, stop looking for more. 841 * 842 */ 843static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 844{ 845 struct at91_priv *priv = netdev_priv(dev); 846 u32 reg_msr; 847 unsigned int mb; 848 849 /* masking of reg_sr not needed, already done by at91_irq */ 850 851 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 852 mb = get_tx_echo_mb(priv); 853 854 /* no event in mailbox? */ 855 if (!(reg_sr & (1 << mb))) 856 break; 857 858 /* Disable irq for this TX mailbox */ 859 at91_write(priv, AT91_IDR, 1 << mb); 860 861 /* 862 * only echo if mailbox signals us a transfer 863 * complete (MSR_MRDY). Otherwise it's a tansfer 864 * abort. "can_bus_off()" takes care about the skbs 865 * parked in the echo queue. 866 */ 867 reg_msr = at91_read(priv, AT91_MSR(mb)); 868 if (likely(reg_msr & AT91_MSR_MRDY && 869 ~reg_msr & AT91_MSR_MABT)) { 870 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 871 can_get_echo_skb(dev, mb - get_mb_tx_first(priv)); 872 dev->stats.tx_packets++; 873 } 874 } 875 876 /* 877 * restart queue if we don't have a wrap around but restart if 878 * we get a TX int for the last can frame directly before a 879 * wrap around. 880 */ 881 if ((priv->tx_next & get_next_mask(priv)) != 0 || 882 (priv->tx_echo & get_next_mask(priv)) == 0) 883 netif_wake_queue(dev); 884} 885 886static void at91_irq_err_state(struct net_device *dev, 887 struct can_frame *cf, enum can_state new_state) 888{ 889 struct at91_priv *priv = netdev_priv(dev); 890 u32 reg_idr = 0, reg_ier = 0; 891 struct can_berr_counter bec; 892 893 at91_get_berr_counter(dev, &bec); 894 895 switch (priv->can.state) { 896 case CAN_STATE_ERROR_ACTIVE: 897 /* 898 * from: ERROR_ACTIVE 899 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 900 * => : there was a warning int 901 */ 902 if (new_state >= CAN_STATE_ERROR_WARNING && 903 new_state <= CAN_STATE_BUS_OFF) { 904 netdev_dbg(dev, "Error Warning IRQ\n"); 905 priv->can.can_stats.error_warning++; 906 907 cf->can_id |= CAN_ERR_CRTL; 908 cf->data[1] = (bec.txerr > bec.rxerr) ? 909 CAN_ERR_CRTL_TX_WARNING : 910 CAN_ERR_CRTL_RX_WARNING; 911 } 912 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 913 /* 914 * from: ERROR_ACTIVE, ERROR_WARNING 915 * to : ERROR_PASSIVE, BUS_OFF 916 * => : error passive int 917 */ 918 if (new_state >= CAN_STATE_ERROR_PASSIVE && 919 new_state <= CAN_STATE_BUS_OFF) { 920 netdev_dbg(dev, "Error Passive IRQ\n"); 921 priv->can.can_stats.error_passive++; 922 923 cf->can_id |= CAN_ERR_CRTL; 924 cf->data[1] = (bec.txerr > bec.rxerr) ? 925 CAN_ERR_CRTL_TX_PASSIVE : 926 CAN_ERR_CRTL_RX_PASSIVE; 927 } 928 break; 929 case CAN_STATE_BUS_OFF: 930 /* 931 * from: BUS_OFF 932 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 933 */ 934 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 935 cf->can_id |= CAN_ERR_RESTARTED; 936 937 netdev_dbg(dev, "restarted\n"); 938 priv->can.can_stats.restarts++; 939 940 netif_carrier_on(dev); 941 netif_wake_queue(dev); 942 } 943 break; 944 default: 945 break; 946 } 947 948 949 /* process state changes depending on the new state */ 950 switch (new_state) { 951 case CAN_STATE_ERROR_ACTIVE: 952 /* 953 * actually we want to enable AT91_IRQ_WARN here, but 954 * it screws up the system under certain 955 * circumstances. so just enable AT91_IRQ_ERRP, thus 956 * the "fallthrough" 957 */ 958 netdev_dbg(dev, "Error Active\n"); 959 cf->can_id |= CAN_ERR_PROT; 960 cf->data[2] = CAN_ERR_PROT_ACTIVE; 961 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 962 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 963 reg_ier = AT91_IRQ_ERRP; 964 break; 965 case CAN_STATE_ERROR_PASSIVE: 966 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 967 reg_ier = AT91_IRQ_BOFF; 968 break; 969 case CAN_STATE_BUS_OFF: 970 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 971 AT91_IRQ_WARN | AT91_IRQ_BOFF; 972 reg_ier = 0; 973 974 cf->can_id |= CAN_ERR_BUSOFF; 975 976 netdev_dbg(dev, "bus-off\n"); 977 netif_carrier_off(dev); 978 priv->can.can_stats.bus_off++; 979 980 /* turn off chip, if restart is disabled */ 981 if (!priv->can.restart_ms) { 982 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 983 return; 984 } 985 break; 986 default: 987 break; 988 } 989 990 at91_write(priv, AT91_IDR, reg_idr); 991 at91_write(priv, AT91_IER, reg_ier); 992} 993 994static void at91_irq_err(struct net_device *dev) 995{ 996 struct at91_priv *priv = netdev_priv(dev); 997 struct sk_buff *skb; 998 struct can_frame *cf; 999 enum can_state new_state; 1000 u32 reg_sr; 1001 1002 reg_sr = at91_read(priv, AT91_SR); 1003 1004 /* we need to look at the unmasked reg_sr */ 1005 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 1006 new_state = CAN_STATE_BUS_OFF; 1007 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 1008 new_state = CAN_STATE_ERROR_PASSIVE; 1009 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 1010 new_state = CAN_STATE_ERROR_WARNING; 1011 else if (likely(reg_sr & AT91_IRQ_ERRA)) 1012 new_state = CAN_STATE_ERROR_ACTIVE; 1013 else { 1014 netdev_err(dev, "BUG! hardware in undefined state\n"); 1015 return; 1016 } 1017 1018 /* state hasn't changed */ 1019 if (likely(new_state == priv->can.state)) 1020 return; 1021 1022 skb = alloc_can_err_skb(dev, &cf); 1023 if (unlikely(!skb)) 1024 return; 1025 1026 at91_irq_err_state(dev, cf, new_state); 1027 netif_rx(skb); 1028 1029 dev->stats.rx_packets++; 1030 dev->stats.rx_bytes += cf->can_dlc; 1031 1032 priv->can.state = new_state; 1033} 1034 1035/* 1036 * interrupt handler 1037 */ 1038static irqreturn_t at91_irq(int irq, void *dev_id) 1039{ 1040 struct net_device *dev = dev_id; 1041 struct at91_priv *priv = netdev_priv(dev); 1042 irqreturn_t handled = IRQ_NONE; 1043 u32 reg_sr, reg_imr; 1044 1045 reg_sr = at91_read(priv, AT91_SR); 1046 reg_imr = at91_read(priv, AT91_IMR); 1047 1048 /* Ignore masked interrupts */ 1049 reg_sr &= reg_imr; 1050 if (!reg_sr) 1051 goto exit; 1052 1053 handled = IRQ_HANDLED; 1054 1055 /* Receive or error interrupt? -> napi */ 1056 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1057 /* 1058 * The error bits are clear on read, 1059 * save for later use. 1060 */ 1061 priv->reg_sr = reg_sr; 1062 at91_write(priv, AT91_IDR, 1063 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1064 napi_schedule(&priv->napi); 1065 } 1066 1067 /* Transmission complete interrupt */ 1068 if (reg_sr & get_irq_mb_tx(priv)) 1069 at91_irq_tx(dev, reg_sr); 1070 1071 at91_irq_err(dev); 1072 1073 exit: 1074 return handled; 1075} 1076 1077static int at91_open(struct net_device *dev) 1078{ 1079 struct at91_priv *priv = netdev_priv(dev); 1080 int err; 1081 1082 clk_enable(priv->clk); 1083 1084 /* check or determine and set bittime */ 1085 err = open_candev(dev); 1086 if (err) 1087 goto out; 1088 1089 /* register interrupt handler */ 1090 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1091 dev->name, dev)) { 1092 err = -EAGAIN; 1093 goto out_close; 1094 } 1095 1096 /* start chip and queuing */ 1097 at91_chip_start(dev); 1098 napi_enable(&priv->napi); 1099 netif_start_queue(dev); 1100 1101 return 0; 1102 1103 out_close: 1104 close_candev(dev); 1105 out: 1106 clk_disable(priv->clk); 1107 1108 return err; 1109} 1110 1111/* 1112 * stop CAN bus activity 1113 */ 1114static int at91_close(struct net_device *dev) 1115{ 1116 struct at91_priv *priv = netdev_priv(dev); 1117 1118 netif_stop_queue(dev); 1119 napi_disable(&priv->napi); 1120 at91_chip_stop(dev, CAN_STATE_STOPPED); 1121 1122 free_irq(dev->irq, dev); 1123 clk_disable(priv->clk); 1124 1125 close_candev(dev); 1126 1127 return 0; 1128} 1129 1130static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1131{ 1132 switch (mode) { 1133 case CAN_MODE_START: 1134 at91_chip_start(dev); 1135 netif_wake_queue(dev); 1136 break; 1137 1138 default: 1139 return -EOPNOTSUPP; 1140 } 1141 1142 return 0; 1143} 1144 1145static const struct net_device_ops at91_netdev_ops = { 1146 .ndo_open = at91_open, 1147 .ndo_stop = at91_close, 1148 .ndo_start_xmit = at91_start_xmit, 1149}; 1150 1151static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1152 struct device_attribute *attr, char *buf) 1153{ 1154 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1155 1156 if (priv->mb0_id & CAN_EFF_FLAG) 1157 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1158 else 1159 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1160} 1161 1162static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1163 struct device_attribute *attr, const char *buf, size_t count) 1164{ 1165 struct net_device *ndev = to_net_dev(dev); 1166 struct at91_priv *priv = netdev_priv(ndev); 1167 unsigned long can_id; 1168 ssize_t ret; 1169 int err; 1170 1171 rtnl_lock(); 1172 1173 if (ndev->flags & IFF_UP) { 1174 ret = -EBUSY; 1175 goto out; 1176 } 1177 1178 err = strict_strtoul(buf, 0, &can_id); 1179 if (err) { 1180 ret = err; 1181 goto out; 1182 } 1183 1184 if (can_id & CAN_EFF_FLAG) 1185 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1186 else 1187 can_id &= CAN_SFF_MASK; 1188 1189 priv->mb0_id = can_id; 1190 ret = count; 1191 1192 out: 1193 rtnl_unlock(); 1194 return ret; 1195} 1196 1197static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1198 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1199 1200static struct attribute *at91_sysfs_attrs[] = { 1201 &dev_attr_mb0_id.attr, 1202 NULL, 1203}; 1204 1205static struct attribute_group at91_sysfs_attr_group = { 1206 .attrs = at91_sysfs_attrs, 1207}; 1208 1209static int __devinit at91_can_probe(struct platform_device *pdev) 1210{ 1211 const struct at91_devtype_data *devtype_data; 1212 enum at91_devtype devtype; 1213 struct net_device *dev; 1214 struct at91_priv *priv; 1215 struct resource *res; 1216 struct clk *clk; 1217 void __iomem *addr; 1218 int err, irq; 1219 1220 devtype = pdev->id_entry->driver_data; 1221 devtype_data = &at91_devtype_data[devtype]; 1222 1223 clk = clk_get(&pdev->dev, "can_clk"); 1224 if (IS_ERR(clk)) { 1225 dev_err(&pdev->dev, "no clock defined\n"); 1226 err = -ENODEV; 1227 goto exit; 1228 } 1229 1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1231 irq = platform_get_irq(pdev, 0); 1232 if (!res || irq <= 0) { 1233 err = -ENODEV; 1234 goto exit_put; 1235 } 1236 1237 if (!request_mem_region(res->start, 1238 resource_size(res), 1239 pdev->name)) { 1240 err = -EBUSY; 1241 goto exit_put; 1242 } 1243 1244 addr = ioremap_nocache(res->start, resource_size(res)); 1245 if (!addr) { 1246 err = -ENOMEM; 1247 goto exit_release; 1248 } 1249 1250 dev = alloc_candev(sizeof(struct at91_priv), 1251 1 << devtype_data->tx_shift); 1252 if (!dev) { 1253 err = -ENOMEM; 1254 goto exit_iounmap; 1255 } 1256 1257 dev->netdev_ops = &at91_netdev_ops; 1258 dev->irq = irq; 1259 dev->flags |= IFF_ECHO; 1260 1261 priv = netdev_priv(dev); 1262 priv->can.clock.freq = clk_get_rate(clk); 1263 priv->can.bittiming_const = &at91_bittiming_const; 1264 priv->can.do_set_mode = at91_set_mode; 1265 priv->can.do_get_berr_counter = at91_get_berr_counter; 1266 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1267 priv->dev = dev; 1268 priv->reg_base = addr; 1269 priv->devtype_data = *devtype_data; 1270 priv->devtype_data.type = devtype; 1271 priv->clk = clk; 1272 priv->pdata = pdev->dev.platform_data; 1273 priv->mb0_id = 0x7ff; 1274 1275 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1276 1277 if (at91_is_sam9263(priv)) 1278 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1279 1280 dev_set_drvdata(&pdev->dev, dev); 1281 SET_NETDEV_DEV(dev, &pdev->dev); 1282 1283 err = register_candev(dev); 1284 if (err) { 1285 dev_err(&pdev->dev, "registering netdev failed\n"); 1286 goto exit_free; 1287 } 1288 1289 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1290 priv->reg_base, dev->irq); 1291 1292 return 0; 1293 1294 exit_free: 1295 free_candev(dev); 1296 exit_iounmap: 1297 iounmap(addr); 1298 exit_release: 1299 release_mem_region(res->start, resource_size(res)); 1300 exit_put: 1301 clk_put(clk); 1302 exit: 1303 return err; 1304} 1305 1306static int __devexit at91_can_remove(struct platform_device *pdev) 1307{ 1308 struct net_device *dev = platform_get_drvdata(pdev); 1309 struct at91_priv *priv = netdev_priv(dev); 1310 struct resource *res; 1311 1312 unregister_netdev(dev); 1313 1314 platform_set_drvdata(pdev, NULL); 1315 1316 iounmap(priv->reg_base); 1317 1318 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1319 release_mem_region(res->start, resource_size(res)); 1320 1321 clk_put(priv->clk); 1322 1323 free_candev(dev); 1324 1325 return 0; 1326} 1327 1328static const struct platform_device_id at91_can_id_table[] = { 1329 { 1330 .name = "at91_can", 1331 .driver_data = AT91_DEVTYPE_SAM9263, 1332 }, { 1333 /* sentinel */ 1334 } 1335}; 1336 1337static struct platform_driver at91_can_driver = { 1338 .probe = at91_can_probe, 1339 .remove = __devexit_p(at91_can_remove), 1340 .driver = { 1341 .name = KBUILD_MODNAME, 1342 .owner = THIS_MODULE, 1343 }, 1344 .id_table = at91_can_id_table, 1345}; 1346 1347static int __init at91_can_module_init(void) 1348{ 1349 return platform_driver_register(&at91_can_driver); 1350} 1351 1352static void __exit at91_can_module_exit(void) 1353{ 1354 platform_driver_unregister(&at91_can_driver); 1355} 1356 1357module_init(at91_can_module_init); 1358module_exit(at91_can_module_exit); 1359 1360MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1361MODULE_LICENSE("GPL v2"); 1362MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1363