at91_can.c revision 0909c1ec6f016b3f580fa2f4630659a5874a8ef8
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define AT91_NAPI_WEIGHT 12 44 45/* 46 * RX/TX Mailbox split 47 * don't dare to touch 48 */ 49#define AT91_MB_RX_NUM 12 50#define AT91_MB_TX_SHIFT 2 51 52#define AT91_MB_RX_FIRST 0 53#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 54 55#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 56#define AT91_MB_RX_SPLIT 8 57#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 58#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \ 59 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 131 - (1 << AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 133 - (1 << AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172}; 173 174static struct can_bittiming_const at91_bittiming_const = { 175 .name = KBUILD_MODNAME, 176 .tseg1_min = 4, 177 .tseg1_max = 16, 178 .tseg2_min = 2, 179 .tseg2_max = 8, 180 .sjw_max = 4, 181 .brp_min = 2, 182 .brp_max = 128, 183 .brp_inc = 1, 184}; 185 186static inline int get_tx_next_mb(const struct at91_priv *priv) 187{ 188 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 189} 190 191static inline int get_tx_next_prio(const struct at91_priv *priv) 192{ 193 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 194} 195 196static inline int get_tx_echo_mb(const struct at91_priv *priv) 197{ 198 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 199} 200 201static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 202{ 203 return __raw_readl(priv->reg_base + reg); 204} 205 206static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 207 u32 value) 208{ 209 __raw_writel(value, priv->reg_base + reg); 210} 211 212static inline void set_mb_mode_prio(const struct at91_priv *priv, 213 unsigned int mb, enum at91_mb_mode mode, int prio) 214{ 215 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 216} 217 218static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 219 enum at91_mb_mode mode) 220{ 221 set_mb_mode_prio(priv, mb, mode, 0); 222} 223 224/* 225 * Swtich transceiver on or off 226 */ 227static void at91_transceiver_switch(const struct at91_priv *priv, int on) 228{ 229 if (priv->pdata && priv->pdata->transceiver_switch) 230 priv->pdata->transceiver_switch(on); 231} 232 233static void at91_setup_mailboxes(struct net_device *dev) 234{ 235 struct at91_priv *priv = netdev_priv(dev); 236 unsigned int i; 237 238 /* 239 * The first 12 mailboxes are used as a reception FIFO. The 240 * last mailbox is configured with overwrite option. The 241 * overwrite flag indicates a FIFO overflow. 242 */ 243 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 244 set_mb_mode(priv, i, AT91_MB_MODE_RX); 245 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 246 247 /* reset acceptance mask and id register */ 248 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 249 at91_write(priv, AT91_MAM(i), 0x0 ); 250 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 251 } 252 253 /* The last 4 mailboxes are used for transmitting. */ 254 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 255 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 256 257 /* Reset tx and rx helper pointers */ 258 priv->tx_next = priv->tx_echo = 0; 259 priv->rx_next = AT91_MB_RX_FIRST; 260} 261 262static int at91_set_bittiming(struct net_device *dev) 263{ 264 const struct at91_priv *priv = netdev_priv(dev); 265 const struct can_bittiming *bt = &priv->can.bittiming; 266 u32 reg_br; 267 268 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 269 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 270 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 271 ((bt->phase_seg2 - 1) << 0); 272 273 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 274 275 at91_write(priv, AT91_BR, reg_br); 276 277 return 0; 278} 279 280static int at91_get_berr_counter(const struct net_device *dev, 281 struct can_berr_counter *bec) 282{ 283 const struct at91_priv *priv = netdev_priv(dev); 284 u32 reg_ecr = at91_read(priv, AT91_ECR); 285 286 bec->rxerr = reg_ecr & 0xff; 287 bec->txerr = reg_ecr >> 16; 288 289 return 0; 290} 291 292static void at91_chip_start(struct net_device *dev) 293{ 294 struct at91_priv *priv = netdev_priv(dev); 295 u32 reg_mr, reg_ier; 296 297 /* disable interrupts */ 298 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 299 300 /* disable chip */ 301 reg_mr = at91_read(priv, AT91_MR); 302 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 303 304 at91_set_bittiming(dev); 305 at91_setup_mailboxes(dev); 306 at91_transceiver_switch(priv, 1); 307 308 /* enable chip */ 309 at91_write(priv, AT91_MR, AT91_MR_CANEN); 310 311 priv->can.state = CAN_STATE_ERROR_ACTIVE; 312 313 /* Enable interrupts */ 314 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 315 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 316 at91_write(priv, AT91_IER, reg_ier); 317} 318 319static void at91_chip_stop(struct net_device *dev, enum can_state state) 320{ 321 struct at91_priv *priv = netdev_priv(dev); 322 u32 reg_mr; 323 324 /* disable interrupts */ 325 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 326 327 reg_mr = at91_read(priv, AT91_MR); 328 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 329 330 at91_transceiver_switch(priv, 0); 331 priv->can.state = state; 332} 333 334/* 335 * theory of operation: 336 * 337 * According to the datasheet priority 0 is the highest priority, 15 338 * is the lowest. If two mailboxes have the same priority level the 339 * message of the mailbox with the lowest number is sent first. 340 * 341 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 342 * the next mailbox with prio 0, and so on, until all mailboxes are 343 * used. Then we start from the beginning with mailbox 344 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 345 * prio 1. When we reach the last mailbox with prio 15, we have to 346 * stop sending, waiting for all messages to be delivered, then start 347 * again with mailbox AT91_MB_TX_FIRST prio 0. 348 * 349 * We use the priv->tx_next as counter for the next transmission 350 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 351 * encode the mailbox number, the upper 4 bits the mailbox priority: 352 * 353 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 354 * (mb - AT91_MB_TX_FIRST); 355 * 356 */ 357static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 358{ 359 struct at91_priv *priv = netdev_priv(dev); 360 struct net_device_stats *stats = &dev->stats; 361 struct can_frame *cf = (struct can_frame *)skb->data; 362 unsigned int mb, prio; 363 u32 reg_mid, reg_mcr; 364 365 if (can_dropped_invalid_skb(dev, skb)) 366 return NETDEV_TX_OK; 367 368 mb = get_tx_next_mb(priv); 369 prio = get_tx_next_prio(priv); 370 371 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 372 netif_stop_queue(dev); 373 374 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 375 return NETDEV_TX_BUSY; 376 } 377 378 if (cf->can_id & CAN_EFF_FLAG) 379 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 380 else 381 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 382 383 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 384 (cf->can_dlc << 16) | AT91_MCR_MTCR; 385 386 /* disable MB while writing ID (see datasheet) */ 387 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 388 at91_write(priv, AT91_MID(mb), reg_mid); 389 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 390 391 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 392 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 393 394 /* This triggers transmission */ 395 at91_write(priv, AT91_MCR(mb), reg_mcr); 396 397 stats->tx_bytes += cf->can_dlc; 398 399 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 400 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 401 402 /* 403 * we have to stop the queue and deliver all messages in case 404 * of a prio+mb counter wrap around. This is the case if 405 * tx_next buffer prio and mailbox equals 0. 406 * 407 * also stop the queue if next buffer is still in use 408 * (== not ready) 409 */ 410 priv->tx_next++; 411 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 412 AT91_MSR_MRDY) || 413 (priv->tx_next & AT91_NEXT_MASK) == 0) 414 netif_stop_queue(dev); 415 416 /* Enable interrupt for this mailbox */ 417 at91_write(priv, AT91_IER, 1 << mb); 418 419 return NETDEV_TX_OK; 420} 421 422/** 423 * at91_activate_rx_low - activate lower rx mailboxes 424 * @priv: a91 context 425 * 426 * Reenables the lower mailboxes for reception of new CAN messages 427 */ 428static inline void at91_activate_rx_low(const struct at91_priv *priv) 429{ 430 u32 mask = AT91_MB_RX_LOW_MASK; 431 at91_write(priv, AT91_TCR, mask); 432} 433 434/** 435 * at91_activate_rx_mb - reactive single rx mailbox 436 * @priv: a91 context 437 * @mb: mailbox to reactivate 438 * 439 * Reenables given mailbox for reception of new CAN messages 440 */ 441static inline void at91_activate_rx_mb(const struct at91_priv *priv, 442 unsigned int mb) 443{ 444 u32 mask = 1 << mb; 445 at91_write(priv, AT91_TCR, mask); 446} 447 448/** 449 * at91_rx_overflow_err - send error frame due to rx overflow 450 * @dev: net device 451 */ 452static void at91_rx_overflow_err(struct net_device *dev) 453{ 454 struct net_device_stats *stats = &dev->stats; 455 struct sk_buff *skb; 456 struct can_frame *cf; 457 458 netdev_dbg(dev, "RX buffer overflow\n"); 459 stats->rx_over_errors++; 460 stats->rx_errors++; 461 462 skb = alloc_can_err_skb(dev, &cf); 463 if (unlikely(!skb)) 464 return; 465 466 cf->can_id |= CAN_ERR_CRTL; 467 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 468 netif_receive_skb(skb); 469 470 stats->rx_packets++; 471 stats->rx_bytes += cf->can_dlc; 472} 473 474/** 475 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 476 * @dev: net device 477 * @mb: mailbox number to read from 478 * @cf: can frame where to store message 479 * 480 * Reads a CAN message from the given mailbox and stores data into 481 * given can frame. "mb" and "cf" must be valid. 482 */ 483static void at91_read_mb(struct net_device *dev, unsigned int mb, 484 struct can_frame *cf) 485{ 486 const struct at91_priv *priv = netdev_priv(dev); 487 u32 reg_msr, reg_mid; 488 489 reg_mid = at91_read(priv, AT91_MID(mb)); 490 if (reg_mid & AT91_MID_MIDE) 491 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 492 else 493 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 494 495 reg_msr = at91_read(priv, AT91_MSR(mb)); 496 if (reg_msr & AT91_MSR_MRTR) 497 cf->can_id |= CAN_RTR_FLAG; 498 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 499 500 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 501 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 502 503 /* allow RX of extended frames */ 504 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 505 506 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 507 at91_rx_overflow_err(dev); 508} 509 510/** 511 * at91_read_msg - read CAN message from mailbox 512 * @dev: net device 513 * @mb: mail box to read from 514 * 515 * Reads a CAN message from given mailbox, and put into linux network 516 * RX queue, does all housekeeping chores (stats, ...) 517 */ 518static void at91_read_msg(struct net_device *dev, unsigned int mb) 519{ 520 struct net_device_stats *stats = &dev->stats; 521 struct can_frame *cf; 522 struct sk_buff *skb; 523 524 skb = alloc_can_skb(dev, &cf); 525 if (unlikely(!skb)) { 526 stats->rx_dropped++; 527 return; 528 } 529 530 at91_read_mb(dev, mb, cf); 531 netif_receive_skb(skb); 532 533 stats->rx_packets++; 534 stats->rx_bytes += cf->can_dlc; 535} 536 537/** 538 * at91_poll_rx - read multiple CAN messages from mailboxes 539 * @dev: net device 540 * @quota: max number of pkgs we're allowed to receive 541 * 542 * Theory of Operation: 543 * 544 * 12 of the 16 mailboxes on the chip are reserved for RX. we split 545 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes. 546 * 547 * Like it or not, but the chip always saves a received CAN message 548 * into the first free mailbox it finds (starting with the 549 * lowest). This makes it very difficult to read the messages in the 550 * right order from the chip. This is how we work around that problem: 551 * 552 * The first message goes into mb nr. 0 and issues an interrupt. All 553 * rx ints are disabled in the interrupt handler and a napi poll is 554 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 555 * receive another message). 556 * 557 * lower mbxs upper 558 * ______^______ __^__ 559 * / \ / \ 560 * +-+-+-+-+-+-+-+-++-+-+-+-+ 561 * |x|x|x|x|x|x|x|x|| | | | | 562 * +-+-+-+-+-+-+-+-++-+-+-+-+ 563 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 564 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 565 * 566 * The variable priv->rx_next points to the next mailbox to read a 567 * message from. As long we're in the lower mailboxes we just read the 568 * mailbox but not reenable it. 569 * 570 * With completion of the last of the lower mailboxes, we reenable the 571 * whole first group, but continue to look for filled mailboxes in the 572 * upper mailboxes. Imagine the second group like overflow mailboxes, 573 * which takes CAN messages if the lower goup is full. While in the 574 * upper group we reenable the mailbox right after reading it. Giving 575 * the chip more room to store messages. 576 * 577 * After finishing we look again in the lower group if we've still 578 * quota. 579 * 580 */ 581static int at91_poll_rx(struct net_device *dev, int quota) 582{ 583 struct at91_priv *priv = netdev_priv(dev); 584 u32 reg_sr = at91_read(priv, AT91_SR); 585 const unsigned long *addr = (unsigned long *)®_sr; 586 unsigned int mb; 587 int received = 0; 588 589 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 590 reg_sr & AT91_MB_RX_LOW_MASK) 591 netdev_info(dev, 592 "order of incoming frames cannot be guaranteed\n"); 593 594 again: 595 for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next); 596 mb < AT91_MB_RX_LAST + 1 && quota > 0; 597 reg_sr = at91_read(priv, AT91_SR), 598 mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) { 599 at91_read_msg(dev, mb); 600 601 /* reactivate mailboxes */ 602 if (mb == AT91_MB_RX_LOW_LAST) 603 /* all lower mailboxed, if just finished it */ 604 at91_activate_rx_low(priv); 605 else if (mb > AT91_MB_RX_LOW_LAST) 606 /* only the mailbox we read */ 607 at91_activate_rx_mb(priv, mb); 608 609 received++; 610 quota--; 611 } 612 613 /* upper group completed, look again in lower */ 614 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 615 quota > 0 && mb > AT91_MB_RX_LAST) { 616 priv->rx_next = AT91_MB_RX_FIRST; 617 goto again; 618 } 619 620 return received; 621} 622 623static void at91_poll_err_frame(struct net_device *dev, 624 struct can_frame *cf, u32 reg_sr) 625{ 626 struct at91_priv *priv = netdev_priv(dev); 627 628 /* CRC error */ 629 if (reg_sr & AT91_IRQ_CERR) { 630 netdev_dbg(dev, "CERR irq\n"); 631 dev->stats.rx_errors++; 632 priv->can.can_stats.bus_error++; 633 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 634 } 635 636 /* Stuffing Error */ 637 if (reg_sr & AT91_IRQ_SERR) { 638 netdev_dbg(dev, "SERR irq\n"); 639 dev->stats.rx_errors++; 640 priv->can.can_stats.bus_error++; 641 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 642 cf->data[2] |= CAN_ERR_PROT_STUFF; 643 } 644 645 /* Acknowledgement Error */ 646 if (reg_sr & AT91_IRQ_AERR) { 647 netdev_dbg(dev, "AERR irq\n"); 648 dev->stats.tx_errors++; 649 cf->can_id |= CAN_ERR_ACK; 650 } 651 652 /* Form error */ 653 if (reg_sr & AT91_IRQ_FERR) { 654 netdev_dbg(dev, "FERR irq\n"); 655 dev->stats.rx_errors++; 656 priv->can.can_stats.bus_error++; 657 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 658 cf->data[2] |= CAN_ERR_PROT_FORM; 659 } 660 661 /* Bit Error */ 662 if (reg_sr & AT91_IRQ_BERR) { 663 netdev_dbg(dev, "BERR irq\n"); 664 dev->stats.tx_errors++; 665 priv->can.can_stats.bus_error++; 666 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 667 cf->data[2] |= CAN_ERR_PROT_BIT; 668 } 669} 670 671static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 672{ 673 struct sk_buff *skb; 674 struct can_frame *cf; 675 676 if (quota == 0) 677 return 0; 678 679 skb = alloc_can_err_skb(dev, &cf); 680 if (unlikely(!skb)) 681 return 0; 682 683 at91_poll_err_frame(dev, cf, reg_sr); 684 netif_receive_skb(skb); 685 686 dev->stats.rx_packets++; 687 dev->stats.rx_bytes += cf->can_dlc; 688 689 return 1; 690} 691 692static int at91_poll(struct napi_struct *napi, int quota) 693{ 694 struct net_device *dev = napi->dev; 695 const struct at91_priv *priv = netdev_priv(dev); 696 u32 reg_sr = at91_read(priv, AT91_SR); 697 int work_done = 0; 698 699 if (reg_sr & AT91_IRQ_MB_RX) 700 work_done += at91_poll_rx(dev, quota - work_done); 701 702 /* 703 * The error bits are clear on read, 704 * so use saved value from irq handler. 705 */ 706 reg_sr |= priv->reg_sr; 707 if (reg_sr & AT91_IRQ_ERR_FRAME) 708 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 709 710 if (work_done < quota) { 711 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 712 u32 reg_ier = AT91_IRQ_ERR_FRAME; 713 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 714 715 napi_complete(napi); 716 at91_write(priv, AT91_IER, reg_ier); 717 } 718 719 return work_done; 720} 721 722/* 723 * theory of operation: 724 * 725 * priv->tx_echo holds the number of the oldest can_frame put for 726 * transmission into the hardware, but not yet ACKed by the CAN tx 727 * complete IRQ. 728 * 729 * We iterate from priv->tx_echo to priv->tx_next and check if the 730 * packet has been transmitted, echo it back to the CAN framework. If 731 * we discover a not yet transmitted package, stop looking for more. 732 * 733 */ 734static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 735{ 736 struct at91_priv *priv = netdev_priv(dev); 737 u32 reg_msr; 738 unsigned int mb; 739 740 /* masking of reg_sr not needed, already done by at91_irq */ 741 742 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 743 mb = get_tx_echo_mb(priv); 744 745 /* no event in mailbox? */ 746 if (!(reg_sr & (1 << mb))) 747 break; 748 749 /* Disable irq for this TX mailbox */ 750 at91_write(priv, AT91_IDR, 1 << mb); 751 752 /* 753 * only echo if mailbox signals us a transfer 754 * complete (MSR_MRDY). Otherwise it's a tansfer 755 * abort. "can_bus_off()" takes care about the skbs 756 * parked in the echo queue. 757 */ 758 reg_msr = at91_read(priv, AT91_MSR(mb)); 759 if (likely(reg_msr & AT91_MSR_MRDY && 760 ~reg_msr & AT91_MSR_MABT)) { 761 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 762 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 763 dev->stats.tx_packets++; 764 } 765 } 766 767 /* 768 * restart queue if we don't have a wrap around but restart if 769 * we get a TX int for the last can frame directly before a 770 * wrap around. 771 */ 772 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 773 (priv->tx_echo & AT91_NEXT_MASK) == 0) 774 netif_wake_queue(dev); 775} 776 777static void at91_irq_err_state(struct net_device *dev, 778 struct can_frame *cf, enum can_state new_state) 779{ 780 struct at91_priv *priv = netdev_priv(dev); 781 u32 reg_idr = 0, reg_ier = 0; 782 struct can_berr_counter bec; 783 784 at91_get_berr_counter(dev, &bec); 785 786 switch (priv->can.state) { 787 case CAN_STATE_ERROR_ACTIVE: 788 /* 789 * from: ERROR_ACTIVE 790 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 791 * => : there was a warning int 792 */ 793 if (new_state >= CAN_STATE_ERROR_WARNING && 794 new_state <= CAN_STATE_BUS_OFF) { 795 netdev_dbg(dev, "Error Warning IRQ\n"); 796 priv->can.can_stats.error_warning++; 797 798 cf->can_id |= CAN_ERR_CRTL; 799 cf->data[1] = (bec.txerr > bec.rxerr) ? 800 CAN_ERR_CRTL_TX_WARNING : 801 CAN_ERR_CRTL_RX_WARNING; 802 } 803 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 804 /* 805 * from: ERROR_ACTIVE, ERROR_WARNING 806 * to : ERROR_PASSIVE, BUS_OFF 807 * => : error passive int 808 */ 809 if (new_state >= CAN_STATE_ERROR_PASSIVE && 810 new_state <= CAN_STATE_BUS_OFF) { 811 netdev_dbg(dev, "Error Passive IRQ\n"); 812 priv->can.can_stats.error_passive++; 813 814 cf->can_id |= CAN_ERR_CRTL; 815 cf->data[1] = (bec.txerr > bec.rxerr) ? 816 CAN_ERR_CRTL_TX_PASSIVE : 817 CAN_ERR_CRTL_RX_PASSIVE; 818 } 819 break; 820 case CAN_STATE_BUS_OFF: 821 /* 822 * from: BUS_OFF 823 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 824 */ 825 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 826 cf->can_id |= CAN_ERR_RESTARTED; 827 828 netdev_dbg(dev, "restarted\n"); 829 priv->can.can_stats.restarts++; 830 831 netif_carrier_on(dev); 832 netif_wake_queue(dev); 833 } 834 break; 835 default: 836 break; 837 } 838 839 840 /* process state changes depending on the new state */ 841 switch (new_state) { 842 case CAN_STATE_ERROR_ACTIVE: 843 /* 844 * actually we want to enable AT91_IRQ_WARN here, but 845 * it screws up the system under certain 846 * circumstances. so just enable AT91_IRQ_ERRP, thus 847 * the "fallthrough" 848 */ 849 netdev_dbg(dev, "Error Active\n"); 850 cf->can_id |= CAN_ERR_PROT; 851 cf->data[2] = CAN_ERR_PROT_ACTIVE; 852 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 853 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 854 reg_ier = AT91_IRQ_ERRP; 855 break; 856 case CAN_STATE_ERROR_PASSIVE: 857 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 858 reg_ier = AT91_IRQ_BOFF; 859 break; 860 case CAN_STATE_BUS_OFF: 861 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 862 AT91_IRQ_WARN | AT91_IRQ_BOFF; 863 reg_ier = 0; 864 865 cf->can_id |= CAN_ERR_BUSOFF; 866 867 netdev_dbg(dev, "bus-off\n"); 868 netif_carrier_off(dev); 869 priv->can.can_stats.bus_off++; 870 871 /* turn off chip, if restart is disabled */ 872 if (!priv->can.restart_ms) { 873 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 874 return; 875 } 876 break; 877 default: 878 break; 879 } 880 881 at91_write(priv, AT91_IDR, reg_idr); 882 at91_write(priv, AT91_IER, reg_ier); 883} 884 885static void at91_irq_err(struct net_device *dev) 886{ 887 struct at91_priv *priv = netdev_priv(dev); 888 struct sk_buff *skb; 889 struct can_frame *cf; 890 enum can_state new_state; 891 u32 reg_sr; 892 893 reg_sr = at91_read(priv, AT91_SR); 894 895 /* we need to look at the unmasked reg_sr */ 896 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 897 new_state = CAN_STATE_BUS_OFF; 898 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 899 new_state = CAN_STATE_ERROR_PASSIVE; 900 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 901 new_state = CAN_STATE_ERROR_WARNING; 902 else if (likely(reg_sr & AT91_IRQ_ERRA)) 903 new_state = CAN_STATE_ERROR_ACTIVE; 904 else { 905 netdev_err(dev, "BUG! hardware in undefined state\n"); 906 return; 907 } 908 909 /* state hasn't changed */ 910 if (likely(new_state == priv->can.state)) 911 return; 912 913 skb = alloc_can_err_skb(dev, &cf); 914 if (unlikely(!skb)) 915 return; 916 917 at91_irq_err_state(dev, cf, new_state); 918 netif_rx(skb); 919 920 dev->stats.rx_packets++; 921 dev->stats.rx_bytes += cf->can_dlc; 922 923 priv->can.state = new_state; 924} 925 926/* 927 * interrupt handler 928 */ 929static irqreturn_t at91_irq(int irq, void *dev_id) 930{ 931 struct net_device *dev = dev_id; 932 struct at91_priv *priv = netdev_priv(dev); 933 irqreturn_t handled = IRQ_NONE; 934 u32 reg_sr, reg_imr; 935 936 reg_sr = at91_read(priv, AT91_SR); 937 reg_imr = at91_read(priv, AT91_IMR); 938 939 /* Ignore masked interrupts */ 940 reg_sr &= reg_imr; 941 if (!reg_sr) 942 goto exit; 943 944 handled = IRQ_HANDLED; 945 946 /* Receive or error interrupt? -> napi */ 947 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 948 /* 949 * The error bits are clear on read, 950 * save for later use. 951 */ 952 priv->reg_sr = reg_sr; 953 at91_write(priv, AT91_IDR, 954 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 955 napi_schedule(&priv->napi); 956 } 957 958 /* Transmission complete interrupt */ 959 if (reg_sr & AT91_IRQ_MB_TX) 960 at91_irq_tx(dev, reg_sr); 961 962 at91_irq_err(dev); 963 964 exit: 965 return handled; 966} 967 968static int at91_open(struct net_device *dev) 969{ 970 struct at91_priv *priv = netdev_priv(dev); 971 int err; 972 973 clk_enable(priv->clk); 974 975 /* check or determine and set bittime */ 976 err = open_candev(dev); 977 if (err) 978 goto out; 979 980 /* register interrupt handler */ 981 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 982 dev->name, dev)) { 983 err = -EAGAIN; 984 goto out_close; 985 } 986 987 /* start chip and queuing */ 988 at91_chip_start(dev); 989 napi_enable(&priv->napi); 990 netif_start_queue(dev); 991 992 return 0; 993 994 out_close: 995 close_candev(dev); 996 out: 997 clk_disable(priv->clk); 998 999 return err; 1000} 1001 1002/* 1003 * stop CAN bus activity 1004 */ 1005static int at91_close(struct net_device *dev) 1006{ 1007 struct at91_priv *priv = netdev_priv(dev); 1008 1009 netif_stop_queue(dev); 1010 napi_disable(&priv->napi); 1011 at91_chip_stop(dev, CAN_STATE_STOPPED); 1012 1013 free_irq(dev->irq, dev); 1014 clk_disable(priv->clk); 1015 1016 close_candev(dev); 1017 1018 return 0; 1019} 1020 1021static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1022{ 1023 switch (mode) { 1024 case CAN_MODE_START: 1025 at91_chip_start(dev); 1026 netif_wake_queue(dev); 1027 break; 1028 1029 default: 1030 return -EOPNOTSUPP; 1031 } 1032 1033 return 0; 1034} 1035 1036static const struct net_device_ops at91_netdev_ops = { 1037 .ndo_open = at91_open, 1038 .ndo_stop = at91_close, 1039 .ndo_start_xmit = at91_start_xmit, 1040}; 1041 1042static int __devinit at91_can_probe(struct platform_device *pdev) 1043{ 1044 struct net_device *dev; 1045 struct at91_priv *priv; 1046 struct resource *res; 1047 struct clk *clk; 1048 void __iomem *addr; 1049 int err, irq; 1050 1051 clk = clk_get(&pdev->dev, "can_clk"); 1052 if (IS_ERR(clk)) { 1053 dev_err(&pdev->dev, "no clock defined\n"); 1054 err = -ENODEV; 1055 goto exit; 1056 } 1057 1058 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1059 irq = platform_get_irq(pdev, 0); 1060 if (!res || irq <= 0) { 1061 err = -ENODEV; 1062 goto exit_put; 1063 } 1064 1065 if (!request_mem_region(res->start, 1066 resource_size(res), 1067 pdev->name)) { 1068 err = -EBUSY; 1069 goto exit_put; 1070 } 1071 1072 addr = ioremap_nocache(res->start, resource_size(res)); 1073 if (!addr) { 1074 err = -ENOMEM; 1075 goto exit_release; 1076 } 1077 1078 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1079 if (!dev) { 1080 err = -ENOMEM; 1081 goto exit_iounmap; 1082 } 1083 1084 dev->netdev_ops = &at91_netdev_ops; 1085 dev->irq = irq; 1086 dev->flags |= IFF_ECHO; 1087 1088 priv = netdev_priv(dev); 1089 priv->can.clock.freq = clk_get_rate(clk); 1090 priv->can.bittiming_const = &at91_bittiming_const; 1091 priv->can.do_set_mode = at91_set_mode; 1092 priv->can.do_get_berr_counter = at91_get_berr_counter; 1093 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1094 priv->reg_base = addr; 1095 priv->dev = dev; 1096 priv->clk = clk; 1097 priv->pdata = pdev->dev.platform_data; 1098 1099 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1100 1101 dev_set_drvdata(&pdev->dev, dev); 1102 SET_NETDEV_DEV(dev, &pdev->dev); 1103 1104 err = register_candev(dev); 1105 if (err) { 1106 dev_err(&pdev->dev, "registering netdev failed\n"); 1107 goto exit_free; 1108 } 1109 1110 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1111 priv->reg_base, dev->irq); 1112 1113 return 0; 1114 1115 exit_free: 1116 free_candev(dev); 1117 exit_iounmap: 1118 iounmap(addr); 1119 exit_release: 1120 release_mem_region(res->start, resource_size(res)); 1121 exit_put: 1122 clk_put(clk); 1123 exit: 1124 return err; 1125} 1126 1127static int __devexit at91_can_remove(struct platform_device *pdev) 1128{ 1129 struct net_device *dev = platform_get_drvdata(pdev); 1130 struct at91_priv *priv = netdev_priv(dev); 1131 struct resource *res; 1132 1133 unregister_netdev(dev); 1134 1135 platform_set_drvdata(pdev, NULL); 1136 1137 iounmap(priv->reg_base); 1138 1139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1140 release_mem_region(res->start, resource_size(res)); 1141 1142 clk_put(priv->clk); 1143 1144 free_candev(dev); 1145 1146 return 0; 1147} 1148 1149static struct platform_driver at91_can_driver = { 1150 .probe = at91_can_probe, 1151 .remove = __devexit_p(at91_can_remove), 1152 .driver = { 1153 .name = KBUILD_MODNAME, 1154 .owner = THIS_MODULE, 1155 }, 1156}; 1157 1158static int __init at91_can_module_init(void) 1159{ 1160 return platform_driver_register(&at91_can_driver); 1161} 1162 1163static void __exit at91_can_module_exit(void) 1164{ 1165 platform_driver_unregister(&at91_can_driver); 1166} 1167 1168module_init(at91_can_module_init); 1169module_exit(at91_can_module_exit); 1170 1171MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1172MODULE_LICENSE("GPL v2"); 1173MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1174