at91_can.c revision 127aa0e14b3e1f8476c4781facdfac11d5546872
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de> 5 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define DRV_NAME "at91_can" 44#define AT91_NAPI_WEIGHT 12 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_RX_NUM 12 51#define AT91_MB_TX_SHIFT 2 52 53#define AT91_MB_RX_FIRST 0 54#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 55 56#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 57#define AT91_MB_RX_SPLIT 8 58#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 59#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 131 - (1 << AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 133 - (1 << AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172}; 173 174static struct can_bittiming_const at91_bittiming_const = { 175 .tseg1_min = 4, 176 .tseg1_max = 16, 177 .tseg2_min = 2, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 2, 181 .brp_max = 128, 182 .brp_inc = 1, 183}; 184 185static inline int get_tx_next_mb(const struct at91_priv *priv) 186{ 187 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 188} 189 190static inline int get_tx_next_prio(const struct at91_priv *priv) 191{ 192 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 193} 194 195static inline int get_tx_echo_mb(const struct at91_priv *priv) 196{ 197 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 198} 199 200static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 201{ 202 return readl(priv->reg_base + reg); 203} 204 205static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 206 u32 value) 207{ 208 writel(value, priv->reg_base + reg); 209} 210 211static inline void set_mb_mode_prio(const struct at91_priv *priv, 212 unsigned int mb, enum at91_mb_mode mode, int prio) 213{ 214 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 215} 216 217static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 218 enum at91_mb_mode mode) 219{ 220 set_mb_mode_prio(priv, mb, mode, 0); 221} 222 223/* 224 * Swtich transceiver on or off 225 */ 226static void at91_transceiver_switch(const struct at91_priv *priv, int on) 227{ 228 if (priv->pdata && priv->pdata->transceiver_switch) 229 priv->pdata->transceiver_switch(on); 230} 231 232static void at91_setup_mailboxes(struct net_device *dev) 233{ 234 struct at91_priv *priv = netdev_priv(dev); 235 unsigned int i; 236 237 /* 238 * The first 12 mailboxes are used as a reception FIFO. The 239 * last mailbox is configured with overwrite option. The 240 * overwrite flag indicates a FIFO overflow. 241 */ 242 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 243 set_mb_mode(priv, i, AT91_MB_MODE_RX); 244 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 245 246 /* The last 4 mailboxes are used for transmitting. */ 247 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 248 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 249 250 /* Reset tx and rx helper pointers */ 251 priv->tx_next = priv->tx_echo = priv->rx_next = 0; 252} 253 254static int at91_set_bittiming(struct net_device *dev) 255{ 256 const struct at91_priv *priv = netdev_priv(dev); 257 const struct can_bittiming *bt = &priv->can.bittiming; 258 u32 reg_br; 259 260 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) << 24) | 261 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 262 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 263 ((bt->phase_seg2 - 1) << 0); 264 265 dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br); 266 267 at91_write(priv, AT91_BR, reg_br); 268 269 return 0; 270} 271 272static void at91_chip_start(struct net_device *dev) 273{ 274 struct at91_priv *priv = netdev_priv(dev); 275 u32 reg_mr, reg_ier; 276 277 /* disable interrupts */ 278 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 279 280 /* disable chip */ 281 reg_mr = at91_read(priv, AT91_MR); 282 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 283 284 at91_setup_mailboxes(dev); 285 at91_transceiver_switch(priv, 1); 286 287 /* enable chip */ 288 at91_write(priv, AT91_MR, AT91_MR_CANEN); 289 290 priv->can.state = CAN_STATE_ERROR_ACTIVE; 291 292 /* Enable interrupts */ 293 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 294 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 295 at91_write(priv, AT91_IER, reg_ier); 296} 297 298static void at91_chip_stop(struct net_device *dev, enum can_state state) 299{ 300 struct at91_priv *priv = netdev_priv(dev); 301 u32 reg_mr; 302 303 /* disable interrupts */ 304 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 305 306 reg_mr = at91_read(priv, AT91_MR); 307 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 308 309 at91_transceiver_switch(priv, 0); 310 priv->can.state = state; 311} 312 313/* 314 * theory of operation: 315 * 316 * According to the datasheet priority 0 is the highest priority, 15 317 * is the lowest. If two mailboxes have the same priority level the 318 * message of the mailbox with the lowest number is sent first. 319 * 320 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 321 * the next mailbox with prio 0, and so on, until all mailboxes are 322 * used. Then we start from the beginning with mailbox 323 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 324 * prio 1. When we reach the last mailbox with prio 15, we have to 325 * stop sending, waiting for all messages to be delivered, then start 326 * again with mailbox AT91_MB_TX_FIRST prio 0. 327 * 328 * We use the priv->tx_next as counter for the next transmission 329 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 330 * encode the mailbox number, the upper 4 bits the mailbox priority: 331 * 332 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 333 * (mb - AT91_MB_TX_FIRST); 334 * 335 */ 336static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 337{ 338 struct at91_priv *priv = netdev_priv(dev); 339 struct net_device_stats *stats = &dev->stats; 340 struct can_frame *cf = (struct can_frame *)skb->data; 341 unsigned int mb, prio; 342 u32 reg_mid, reg_mcr; 343 344 if (can_dropped_invalid_skb(dev, skb)) 345 return NETDEV_TX_OK; 346 347 mb = get_tx_next_mb(priv); 348 prio = get_tx_next_prio(priv); 349 350 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 351 netif_stop_queue(dev); 352 353 dev_err(dev->dev.parent, 354 "BUG! TX buffer full when queue awake!\n"); 355 return NETDEV_TX_BUSY; 356 } 357 358 if (cf->can_id & CAN_EFF_FLAG) 359 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 360 else 361 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 362 363 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 364 (cf->can_dlc << 16) | AT91_MCR_MTCR; 365 366 /* disable MB while writing ID (see datasheet) */ 367 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 368 at91_write(priv, AT91_MID(mb), reg_mid); 369 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 370 371 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 372 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 373 374 /* This triggers transmission */ 375 at91_write(priv, AT91_MCR(mb), reg_mcr); 376 377 stats->tx_bytes += cf->can_dlc; 378 dev->trans_start = jiffies; 379 380 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 381 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 382 383 /* 384 * we have to stop the queue and deliver all messages in case 385 * of a prio+mb counter wrap around. This is the case if 386 * tx_next buffer prio and mailbox equals 0. 387 * 388 * also stop the queue if next buffer is still in use 389 * (== not ready) 390 */ 391 priv->tx_next++; 392 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 393 AT91_MSR_MRDY) || 394 (priv->tx_next & AT91_NEXT_MASK) == 0) 395 netif_stop_queue(dev); 396 397 /* Enable interrupt for this mailbox */ 398 at91_write(priv, AT91_IER, 1 << mb); 399 400 return NETDEV_TX_OK; 401} 402 403/** 404 * at91_activate_rx_low - activate lower rx mailboxes 405 * @priv: a91 context 406 * 407 * Reenables the lower mailboxes for reception of new CAN messages 408 */ 409static inline void at91_activate_rx_low(const struct at91_priv *priv) 410{ 411 u32 mask = AT91_MB_RX_LOW_MASK; 412 at91_write(priv, AT91_TCR, mask); 413} 414 415/** 416 * at91_activate_rx_mb - reactive single rx mailbox 417 * @priv: a91 context 418 * @mb: mailbox to reactivate 419 * 420 * Reenables given mailbox for reception of new CAN messages 421 */ 422static inline void at91_activate_rx_mb(const struct at91_priv *priv, 423 unsigned int mb) 424{ 425 u32 mask = 1 << mb; 426 at91_write(priv, AT91_TCR, mask); 427} 428 429/** 430 * at91_rx_overflow_err - send error frame due to rx overflow 431 * @dev: net device 432 */ 433static void at91_rx_overflow_err(struct net_device *dev) 434{ 435 struct net_device_stats *stats = &dev->stats; 436 struct sk_buff *skb; 437 struct can_frame *cf; 438 439 dev_dbg(dev->dev.parent, "RX buffer overflow\n"); 440 stats->rx_over_errors++; 441 stats->rx_errors++; 442 443 skb = alloc_can_err_skb(dev, &cf); 444 if (unlikely(!skb)) 445 return; 446 447 cf->can_id |= CAN_ERR_CRTL; 448 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 449 netif_receive_skb(skb); 450 451 stats->rx_packets++; 452 stats->rx_bytes += cf->can_dlc; 453} 454 455/** 456 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 457 * @dev: net device 458 * @mb: mailbox number to read from 459 * @cf: can frame where to store message 460 * 461 * Reads a CAN message from the given mailbox and stores data into 462 * given can frame. "mb" and "cf" must be valid. 463 */ 464static void at91_read_mb(struct net_device *dev, unsigned int mb, 465 struct can_frame *cf) 466{ 467 const struct at91_priv *priv = netdev_priv(dev); 468 u32 reg_msr, reg_mid; 469 470 reg_mid = at91_read(priv, AT91_MID(mb)); 471 if (reg_mid & AT91_MID_MIDE) 472 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 473 else 474 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 475 476 reg_msr = at91_read(priv, AT91_MSR(mb)); 477 if (reg_msr & AT91_MSR_MRTR) 478 cf->can_id |= CAN_RTR_FLAG; 479 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 480 481 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 482 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 483 484 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 485 at91_rx_overflow_err(dev); 486} 487 488/** 489 * at91_read_msg - read CAN message from mailbox 490 * @dev: net device 491 * @mb: mail box to read from 492 * 493 * Reads a CAN message from given mailbox, and put into linux network 494 * RX queue, does all housekeeping chores (stats, ...) 495 */ 496static void at91_read_msg(struct net_device *dev, unsigned int mb) 497{ 498 struct net_device_stats *stats = &dev->stats; 499 struct can_frame *cf; 500 struct sk_buff *skb; 501 502 skb = alloc_can_skb(dev, &cf); 503 if (unlikely(!skb)) { 504 stats->rx_dropped++; 505 return; 506 } 507 508 at91_read_mb(dev, mb, cf); 509 netif_receive_skb(skb); 510 511 stats->rx_packets++; 512 stats->rx_bytes += cf->can_dlc; 513} 514 515/** 516 * at91_poll_rx - read multiple CAN messages from mailboxes 517 * @dev: net device 518 * @quota: max number of pkgs we're allowed to receive 519 * 520 * Theory of Operation: 521 * 522 * 12 of the 16 mailboxes on the chip are reserved for RX. we split 523 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes. 524 * 525 * Like it or not, but the chip always saves a received CAN message 526 * into the first free mailbox it finds (starting with the 527 * lowest). This makes it very difficult to read the messages in the 528 * right order from the chip. This is how we work around that problem: 529 * 530 * The first message goes into mb nr. 0 and issues an interrupt. All 531 * rx ints are disabled in the interrupt handler and a napi poll is 532 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 533 * receive another message). 534 * 535 * lower mbxs upper 536 * ______^______ __^__ 537 * / \ / \ 538 * +-+-+-+-+-+-+-+-++-+-+-+-+ 539 * |x|x|x|x|x|x|x|x|| | | | | 540 * +-+-+-+-+-+-+-+-++-+-+-+-+ 541 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 542 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 543 * 544 * The variable priv->rx_next points to the next mailbox to read a 545 * message from. As long we're in the lower mailboxes we just read the 546 * mailbox but not reenable it. 547 * 548 * With completion of the last of the lower mailboxes, we reenable the 549 * whole first group, but continue to look for filled mailboxes in the 550 * upper mailboxes. Imagine the second group like overflow mailboxes, 551 * which takes CAN messages if the lower goup is full. While in the 552 * upper group we reenable the mailbox right after reading it. Giving 553 * the chip more room to store messages. 554 * 555 * After finishing we look again in the lower group if we've still 556 * quota. 557 * 558 */ 559static int at91_poll_rx(struct net_device *dev, int quota) 560{ 561 struct at91_priv *priv = netdev_priv(dev); 562 u32 reg_sr = at91_read(priv, AT91_SR); 563 const unsigned long *addr = (unsigned long *)®_sr; 564 unsigned int mb; 565 int received = 0; 566 567 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 568 reg_sr & AT91_MB_RX_LOW_MASK) 569 dev_info(dev->dev.parent, 570 "order of incoming frames cannot be guaranteed\n"); 571 572 again: 573 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next); 574 mb < AT91_MB_RX_NUM && quota > 0; 575 reg_sr = at91_read(priv, AT91_SR), 576 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) { 577 at91_read_msg(dev, mb); 578 579 /* reactivate mailboxes */ 580 if (mb == AT91_MB_RX_LOW_LAST) 581 /* all lower mailboxed, if just finished it */ 582 at91_activate_rx_low(priv); 583 else if (mb > AT91_MB_RX_LOW_LAST) 584 /* only the mailbox we read */ 585 at91_activate_rx_mb(priv, mb); 586 587 received++; 588 quota--; 589 } 590 591 /* upper group completed, look again in lower */ 592 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 593 quota > 0 && mb >= AT91_MB_RX_NUM) { 594 priv->rx_next = 0; 595 goto again; 596 } 597 598 return received; 599} 600 601static void at91_poll_err_frame(struct net_device *dev, 602 struct can_frame *cf, u32 reg_sr) 603{ 604 struct at91_priv *priv = netdev_priv(dev); 605 606 /* CRC error */ 607 if (reg_sr & AT91_IRQ_CERR) { 608 dev_dbg(dev->dev.parent, "CERR irq\n"); 609 dev->stats.rx_errors++; 610 priv->can.can_stats.bus_error++; 611 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 612 } 613 614 /* Stuffing Error */ 615 if (reg_sr & AT91_IRQ_SERR) { 616 dev_dbg(dev->dev.parent, "SERR irq\n"); 617 dev->stats.rx_errors++; 618 priv->can.can_stats.bus_error++; 619 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 620 cf->data[2] |= CAN_ERR_PROT_STUFF; 621 } 622 623 /* Acknowledgement Error */ 624 if (reg_sr & AT91_IRQ_AERR) { 625 dev_dbg(dev->dev.parent, "AERR irq\n"); 626 dev->stats.tx_errors++; 627 cf->can_id |= CAN_ERR_ACK; 628 } 629 630 /* Form error */ 631 if (reg_sr & AT91_IRQ_FERR) { 632 dev_dbg(dev->dev.parent, "FERR irq\n"); 633 dev->stats.rx_errors++; 634 priv->can.can_stats.bus_error++; 635 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 636 cf->data[2] |= CAN_ERR_PROT_FORM; 637 } 638 639 /* Bit Error */ 640 if (reg_sr & AT91_IRQ_BERR) { 641 dev_dbg(dev->dev.parent, "BERR irq\n"); 642 dev->stats.tx_errors++; 643 priv->can.can_stats.bus_error++; 644 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 645 cf->data[2] |= CAN_ERR_PROT_BIT; 646 } 647} 648 649static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 650{ 651 struct sk_buff *skb; 652 struct can_frame *cf; 653 654 if (quota == 0) 655 return 0; 656 657 skb = alloc_can_err_skb(dev, &cf); 658 if (unlikely(!skb)) 659 return 0; 660 661 at91_poll_err_frame(dev, cf, reg_sr); 662 netif_receive_skb(skb); 663 664 dev->stats.rx_packets++; 665 dev->stats.rx_bytes += cf->can_dlc; 666 667 return 1; 668} 669 670static int at91_poll(struct napi_struct *napi, int quota) 671{ 672 struct net_device *dev = napi->dev; 673 const struct at91_priv *priv = netdev_priv(dev); 674 u32 reg_sr = at91_read(priv, AT91_SR); 675 int work_done = 0; 676 677 if (reg_sr & AT91_IRQ_MB_RX) 678 work_done += at91_poll_rx(dev, quota - work_done); 679 680 /* 681 * The error bits are clear on read, 682 * so use saved value from irq handler. 683 */ 684 reg_sr |= priv->reg_sr; 685 if (reg_sr & AT91_IRQ_ERR_FRAME) 686 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 687 688 if (work_done < quota) { 689 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 690 u32 reg_ier = AT91_IRQ_ERR_FRAME; 691 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 692 693 napi_complete(napi); 694 at91_write(priv, AT91_IER, reg_ier); 695 } 696 697 return work_done; 698} 699 700/* 701 * theory of operation: 702 * 703 * priv->tx_echo holds the number of the oldest can_frame put for 704 * transmission into the hardware, but not yet ACKed by the CAN tx 705 * complete IRQ. 706 * 707 * We iterate from priv->tx_echo to priv->tx_next and check if the 708 * packet has been transmitted, echo it back to the CAN framework. If 709 * we discover a not yet transmitted package, stop looking for more. 710 * 711 */ 712static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 713{ 714 struct at91_priv *priv = netdev_priv(dev); 715 u32 reg_msr; 716 unsigned int mb; 717 718 /* masking of reg_sr not needed, already done by at91_irq */ 719 720 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 721 mb = get_tx_echo_mb(priv); 722 723 /* no event in mailbox? */ 724 if (!(reg_sr & (1 << mb))) 725 break; 726 727 /* Disable irq for this TX mailbox */ 728 at91_write(priv, AT91_IDR, 1 << mb); 729 730 /* 731 * only echo if mailbox signals us a transfer 732 * complete (MSR_MRDY). Otherwise it's a tansfer 733 * abort. "can_bus_off()" takes care about the skbs 734 * parked in the echo queue. 735 */ 736 reg_msr = at91_read(priv, AT91_MSR(mb)); 737 if (likely(reg_msr & AT91_MSR_MRDY && 738 ~reg_msr & AT91_MSR_MABT)) { 739 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 740 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 741 dev->stats.tx_packets++; 742 } 743 } 744 745 /* 746 * restart queue if we don't have a wrap around but restart if 747 * we get a TX int for the last can frame directly before a 748 * wrap around. 749 */ 750 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 751 (priv->tx_echo & AT91_NEXT_MASK) == 0) 752 netif_wake_queue(dev); 753} 754 755static void at91_irq_err_state(struct net_device *dev, 756 struct can_frame *cf, enum can_state new_state) 757{ 758 struct at91_priv *priv = netdev_priv(dev); 759 u32 reg_idr, reg_ier, reg_ecr; 760 u8 tec, rec; 761 762 reg_ecr = at91_read(priv, AT91_ECR); 763 rec = reg_ecr & 0xff; 764 tec = reg_ecr >> 16; 765 766 switch (priv->can.state) { 767 case CAN_STATE_ERROR_ACTIVE: 768 /* 769 * from: ERROR_ACTIVE 770 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 771 * => : there was a warning int 772 */ 773 if (new_state >= CAN_STATE_ERROR_WARNING && 774 new_state <= CAN_STATE_BUS_OFF) { 775 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 776 priv->can.can_stats.error_warning++; 777 778 cf->can_id |= CAN_ERR_CRTL; 779 cf->data[1] = (tec > rec) ? 780 CAN_ERR_CRTL_TX_WARNING : 781 CAN_ERR_CRTL_RX_WARNING; 782 } 783 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 784 /* 785 * from: ERROR_ACTIVE, ERROR_WARNING 786 * to : ERROR_PASSIVE, BUS_OFF 787 * => : error passive int 788 */ 789 if (new_state >= CAN_STATE_ERROR_PASSIVE && 790 new_state <= CAN_STATE_BUS_OFF) { 791 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 792 priv->can.can_stats.error_passive++; 793 794 cf->can_id |= CAN_ERR_CRTL; 795 cf->data[1] = (tec > rec) ? 796 CAN_ERR_CRTL_TX_PASSIVE : 797 CAN_ERR_CRTL_RX_PASSIVE; 798 } 799 break; 800 case CAN_STATE_BUS_OFF: 801 /* 802 * from: BUS_OFF 803 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 804 */ 805 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 806 cf->can_id |= CAN_ERR_RESTARTED; 807 808 dev_dbg(dev->dev.parent, "restarted\n"); 809 priv->can.can_stats.restarts++; 810 811 netif_carrier_on(dev); 812 netif_wake_queue(dev); 813 } 814 break; 815 default: 816 break; 817 } 818 819 820 /* process state changes depending on the new state */ 821 switch (new_state) { 822 case CAN_STATE_ERROR_ACTIVE: 823 /* 824 * actually we want to enable AT91_IRQ_WARN here, but 825 * it screws up the system under certain 826 * circumstances. so just enable AT91_IRQ_ERRP, thus 827 * the "fallthrough" 828 */ 829 dev_dbg(dev->dev.parent, "Error Active\n"); 830 cf->can_id |= CAN_ERR_PROT; 831 cf->data[2] = CAN_ERR_PROT_ACTIVE; 832 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 833 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 834 reg_ier = AT91_IRQ_ERRP; 835 break; 836 case CAN_STATE_ERROR_PASSIVE: 837 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 838 reg_ier = AT91_IRQ_BOFF; 839 break; 840 case CAN_STATE_BUS_OFF: 841 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 842 AT91_IRQ_WARN | AT91_IRQ_BOFF; 843 reg_ier = 0; 844 845 cf->can_id |= CAN_ERR_BUSOFF; 846 847 dev_dbg(dev->dev.parent, "bus-off\n"); 848 netif_carrier_off(dev); 849 priv->can.can_stats.bus_off++; 850 851 /* turn off chip, if restart is disabled */ 852 if (!priv->can.restart_ms) { 853 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 854 return; 855 } 856 break; 857 default: 858 break; 859 } 860 861 at91_write(priv, AT91_IDR, reg_idr); 862 at91_write(priv, AT91_IER, reg_ier); 863} 864 865static void at91_irq_err(struct net_device *dev) 866{ 867 struct at91_priv *priv = netdev_priv(dev); 868 struct sk_buff *skb; 869 struct can_frame *cf; 870 enum can_state new_state; 871 u32 reg_sr; 872 873 reg_sr = at91_read(priv, AT91_SR); 874 875 /* we need to look at the unmasked reg_sr */ 876 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 877 new_state = CAN_STATE_BUS_OFF; 878 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 879 new_state = CAN_STATE_ERROR_PASSIVE; 880 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 881 new_state = CAN_STATE_ERROR_WARNING; 882 else if (likely(reg_sr & AT91_IRQ_ERRA)) 883 new_state = CAN_STATE_ERROR_ACTIVE; 884 else { 885 dev_err(dev->dev.parent, "BUG! hardware in undefined state\n"); 886 return; 887 } 888 889 /* state hasn't changed */ 890 if (likely(new_state == priv->can.state)) 891 return; 892 893 skb = alloc_can_err_skb(dev, &cf); 894 if (unlikely(!skb)) 895 return; 896 897 at91_irq_err_state(dev, cf, new_state); 898 netif_rx(skb); 899 900 dev->stats.rx_packets++; 901 dev->stats.rx_bytes += cf->can_dlc; 902 903 priv->can.state = new_state; 904} 905 906/* 907 * interrupt handler 908 */ 909static irqreturn_t at91_irq(int irq, void *dev_id) 910{ 911 struct net_device *dev = dev_id; 912 struct at91_priv *priv = netdev_priv(dev); 913 irqreturn_t handled = IRQ_NONE; 914 u32 reg_sr, reg_imr; 915 916 reg_sr = at91_read(priv, AT91_SR); 917 reg_imr = at91_read(priv, AT91_IMR); 918 919 /* Ignore masked interrupts */ 920 reg_sr &= reg_imr; 921 if (!reg_sr) 922 goto exit; 923 924 handled = IRQ_HANDLED; 925 926 /* Receive or error interrupt? -> napi */ 927 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 928 /* 929 * The error bits are clear on read, 930 * save for later use. 931 */ 932 priv->reg_sr = reg_sr; 933 at91_write(priv, AT91_IDR, 934 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 935 napi_schedule(&priv->napi); 936 } 937 938 /* Transmission complete interrupt */ 939 if (reg_sr & AT91_IRQ_MB_TX) 940 at91_irq_tx(dev, reg_sr); 941 942 at91_irq_err(dev); 943 944 exit: 945 return handled; 946} 947 948static int at91_open(struct net_device *dev) 949{ 950 struct at91_priv *priv = netdev_priv(dev); 951 int err; 952 953 clk_enable(priv->clk); 954 955 /* check or determine and set bittime */ 956 err = open_candev(dev); 957 if (err) 958 goto out; 959 960 /* register interrupt handler */ 961 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 962 dev->name, dev)) { 963 err = -EAGAIN; 964 goto out_close; 965 } 966 967 /* start chip and queuing */ 968 at91_chip_start(dev); 969 napi_enable(&priv->napi); 970 netif_start_queue(dev); 971 972 return 0; 973 974 out_close: 975 close_candev(dev); 976 out: 977 clk_disable(priv->clk); 978 979 return err; 980} 981 982/* 983 * stop CAN bus activity 984 */ 985static int at91_close(struct net_device *dev) 986{ 987 struct at91_priv *priv = netdev_priv(dev); 988 989 netif_stop_queue(dev); 990 napi_disable(&priv->napi); 991 at91_chip_stop(dev, CAN_STATE_STOPPED); 992 993 free_irq(dev->irq, dev); 994 clk_disable(priv->clk); 995 996 close_candev(dev); 997 998 return 0; 999} 1000 1001static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1002{ 1003 switch (mode) { 1004 case CAN_MODE_START: 1005 at91_chip_start(dev); 1006 netif_wake_queue(dev); 1007 break; 1008 1009 default: 1010 return -EOPNOTSUPP; 1011 } 1012 1013 return 0; 1014} 1015 1016static const struct net_device_ops at91_netdev_ops = { 1017 .ndo_open = at91_open, 1018 .ndo_stop = at91_close, 1019 .ndo_start_xmit = at91_start_xmit, 1020}; 1021 1022static int __init at91_can_probe(struct platform_device *pdev) 1023{ 1024 struct net_device *dev; 1025 struct at91_priv *priv; 1026 struct resource *res; 1027 struct clk *clk; 1028 void __iomem *addr; 1029 int err, irq; 1030 1031 clk = clk_get(&pdev->dev, "can_clk"); 1032 if (IS_ERR(clk)) { 1033 dev_err(&pdev->dev, "no clock defined\n"); 1034 err = -ENODEV; 1035 goto exit; 1036 } 1037 1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1039 irq = platform_get_irq(pdev, 0); 1040 if (!res || irq <= 0) { 1041 err = -ENODEV; 1042 goto exit_put; 1043 } 1044 1045 if (!request_mem_region(res->start, 1046 resource_size(res), 1047 pdev->name)) { 1048 err = -EBUSY; 1049 goto exit_put; 1050 } 1051 1052 addr = ioremap_nocache(res->start, resource_size(res)); 1053 if (!addr) { 1054 err = -ENOMEM; 1055 goto exit_release; 1056 } 1057 1058 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1059 if (!dev) { 1060 err = -ENOMEM; 1061 goto exit_iounmap; 1062 } 1063 1064 dev->netdev_ops = &at91_netdev_ops; 1065 dev->irq = irq; 1066 dev->flags |= IFF_ECHO; 1067 1068 priv = netdev_priv(dev); 1069 priv->can.clock.freq = clk_get_rate(clk); 1070 priv->can.bittiming_const = &at91_bittiming_const; 1071 priv->can.do_set_bittiming = at91_set_bittiming; 1072 priv->can.do_set_mode = at91_set_mode; 1073 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1074 priv->reg_base = addr; 1075 priv->dev = dev; 1076 priv->clk = clk; 1077 priv->pdata = pdev->dev.platform_data; 1078 1079 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1080 1081 dev_set_drvdata(&pdev->dev, dev); 1082 SET_NETDEV_DEV(dev, &pdev->dev); 1083 1084 err = register_candev(dev); 1085 if (err) { 1086 dev_err(&pdev->dev, "registering netdev failed\n"); 1087 goto exit_free; 1088 } 1089 1090 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1091 priv->reg_base, dev->irq); 1092 1093 return 0; 1094 1095 exit_free: 1096 free_netdev(dev); 1097 exit_iounmap: 1098 iounmap(addr); 1099 exit_release: 1100 release_mem_region(res->start, resource_size(res)); 1101 exit_put: 1102 clk_put(clk); 1103 exit: 1104 return err; 1105} 1106 1107static int __devexit at91_can_remove(struct platform_device *pdev) 1108{ 1109 struct net_device *dev = platform_get_drvdata(pdev); 1110 struct at91_priv *priv = netdev_priv(dev); 1111 struct resource *res; 1112 1113 unregister_netdev(dev); 1114 1115 platform_set_drvdata(pdev, NULL); 1116 1117 free_netdev(dev); 1118 1119 iounmap(priv->reg_base); 1120 1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1122 release_mem_region(res->start, resource_size(res)); 1123 1124 clk_put(priv->clk); 1125 1126 return 0; 1127} 1128 1129static struct platform_driver at91_can_driver = { 1130 .probe = at91_can_probe, 1131 .remove = __devexit_p(at91_can_remove), 1132 .driver = { 1133 .name = DRV_NAME, 1134 .owner = THIS_MODULE, 1135 }, 1136}; 1137 1138static int __init at91_can_module_init(void) 1139{ 1140 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME); 1141 return platform_driver_register(&at91_can_driver); 1142} 1143 1144static void __exit at91_can_module_exit(void) 1145{ 1146 platform_driver_unregister(&at91_can_driver); 1147 printk(KERN_INFO "%s: driver removed\n", DRV_NAME); 1148} 1149 1150module_init(at91_can_module_init); 1151module_exit(at91_can_module_exit); 1152 1153MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1154MODULE_LICENSE("GPL v2"); 1155MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver"); 1156