at91_can.c revision 3e9ebd3cf48d9181e0931c6fd8f1a7dc4d6cb27c
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define AT91_NAPI_WEIGHT 12 44 45/* 46 * RX/TX Mailbox split 47 * don't dare to touch 48 */ 49#define AT91_MB_RX_NUM 12 50#define AT91_MB_TX_SHIFT 2 51 52#define AT91_MB_RX_FIRST 0 53#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 54 55#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 56#define AT91_MB_RX_SPLIT 8 57#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 58#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT)) 59 60#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 61#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 62#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 63 64#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 65#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 66#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 67#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 68 69/* Common registers */ 70enum at91_reg { 71 AT91_MR = 0x000, 72 AT91_IER = 0x004, 73 AT91_IDR = 0x008, 74 AT91_IMR = 0x00C, 75 AT91_SR = 0x010, 76 AT91_BR = 0x014, 77 AT91_TIM = 0x018, 78 AT91_TIMESTP = 0x01C, 79 AT91_ECR = 0x020, 80 AT91_TCR = 0x024, 81 AT91_ACR = 0x028, 82}; 83 84/* Mailbox registers (0 <= i <= 15) */ 85#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 86#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 87#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 88#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 89#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 90#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 91#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 92#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 93 94/* Register bits */ 95#define AT91_MR_CANEN BIT(0) 96#define AT91_MR_LPM BIT(1) 97#define AT91_MR_ABM BIT(2) 98#define AT91_MR_OVL BIT(3) 99#define AT91_MR_TEOF BIT(4) 100#define AT91_MR_TTM BIT(5) 101#define AT91_MR_TIMFRZ BIT(6) 102#define AT91_MR_DRPT BIT(7) 103 104#define AT91_SR_RBSY BIT(29) 105 106#define AT91_MMR_PRIO_SHIFT (16) 107 108#define AT91_MID_MIDE BIT(29) 109 110#define AT91_MSR_MRTR BIT(20) 111#define AT91_MSR_MABT BIT(22) 112#define AT91_MSR_MRDY BIT(23) 113#define AT91_MSR_MMI BIT(24) 114 115#define AT91_MCR_MRTR BIT(20) 116#define AT91_MCR_MTCR BIT(23) 117 118/* Mailbox Modes */ 119enum at91_mb_mode { 120 AT91_MB_MODE_DISABLED = 0, 121 AT91_MB_MODE_RX = 1, 122 AT91_MB_MODE_RX_OVRWR = 2, 123 AT91_MB_MODE_TX = 3, 124 AT91_MB_MODE_CONSUMER = 4, 125 AT91_MB_MODE_PRODUCER = 5, 126}; 127 128/* Interrupt mask bits */ 129#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 130 - (1 << AT91_MB_RX_FIRST)) 131#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 132 - (1 << AT91_MB_TX_FIRST)) 133#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 134 135#define AT91_IRQ_ERRA (1 << 16) 136#define AT91_IRQ_WARN (1 << 17) 137#define AT91_IRQ_ERRP (1 << 18) 138#define AT91_IRQ_BOFF (1 << 19) 139#define AT91_IRQ_SLEEP (1 << 20) 140#define AT91_IRQ_WAKEUP (1 << 21) 141#define AT91_IRQ_TOVF (1 << 22) 142#define AT91_IRQ_TSTP (1 << 23) 143#define AT91_IRQ_CERR (1 << 24) 144#define AT91_IRQ_SERR (1 << 25) 145#define AT91_IRQ_AERR (1 << 26) 146#define AT91_IRQ_FERR (1 << 27) 147#define AT91_IRQ_BERR (1 << 28) 148 149#define AT91_IRQ_ERR_ALL (0x1fff0000) 150#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 151 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 152#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 153 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 154 155#define AT91_IRQ_ALL (0x1fffffff) 156 157struct at91_priv { 158 struct can_priv can; /* must be the first member! */ 159 struct net_device *dev; 160 struct napi_struct napi; 161 162 void __iomem *reg_base; 163 164 u32 reg_sr; 165 unsigned int tx_next; 166 unsigned int tx_echo; 167 unsigned int rx_next; 168 169 struct clk *clk; 170 struct at91_can_data *pdata; 171}; 172 173static struct can_bittiming_const at91_bittiming_const = { 174 .name = KBUILD_MODNAME, 175 .tseg1_min = 4, 176 .tseg1_max = 16, 177 .tseg2_min = 2, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 2, 181 .brp_max = 128, 182 .brp_inc = 1, 183}; 184 185static inline int get_tx_next_mb(const struct at91_priv *priv) 186{ 187 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 188} 189 190static inline int get_tx_next_prio(const struct at91_priv *priv) 191{ 192 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 193} 194 195static inline int get_tx_echo_mb(const struct at91_priv *priv) 196{ 197 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 198} 199 200static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 201{ 202 return __raw_readl(priv->reg_base + reg); 203} 204 205static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 206 u32 value) 207{ 208 __raw_writel(value, priv->reg_base + reg); 209} 210 211static inline void set_mb_mode_prio(const struct at91_priv *priv, 212 unsigned int mb, enum at91_mb_mode mode, int prio) 213{ 214 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 215} 216 217static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 218 enum at91_mb_mode mode) 219{ 220 set_mb_mode_prio(priv, mb, mode, 0); 221} 222 223/* 224 * Swtich transceiver on or off 225 */ 226static void at91_transceiver_switch(const struct at91_priv *priv, int on) 227{ 228 if (priv->pdata && priv->pdata->transceiver_switch) 229 priv->pdata->transceiver_switch(on); 230} 231 232static void at91_setup_mailboxes(struct net_device *dev) 233{ 234 struct at91_priv *priv = netdev_priv(dev); 235 unsigned int i; 236 237 /* 238 * The first 12 mailboxes are used as a reception FIFO. The 239 * last mailbox is configured with overwrite option. The 240 * overwrite flag indicates a FIFO overflow. 241 */ 242 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 243 set_mb_mode(priv, i, AT91_MB_MODE_RX); 244 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 245 246 /* reset acceptance mask and id register */ 247 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 248 at91_write(priv, AT91_MAM(i), 0x0 ); 249 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 250 } 251 252 /* The last 4 mailboxes are used for transmitting. */ 253 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 254 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 255 256 /* Reset tx and rx helper pointers */ 257 priv->tx_next = priv->tx_echo = priv->rx_next = 0; 258} 259 260static int at91_set_bittiming(struct net_device *dev) 261{ 262 const struct at91_priv *priv = netdev_priv(dev); 263 const struct can_bittiming *bt = &priv->can.bittiming; 264 u32 reg_br; 265 266 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 267 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 268 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 269 ((bt->phase_seg2 - 1) << 0); 270 271 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 272 273 at91_write(priv, AT91_BR, reg_br); 274 275 return 0; 276} 277 278static int at91_get_berr_counter(const struct net_device *dev, 279 struct can_berr_counter *bec) 280{ 281 const struct at91_priv *priv = netdev_priv(dev); 282 u32 reg_ecr = at91_read(priv, AT91_ECR); 283 284 bec->rxerr = reg_ecr & 0xff; 285 bec->txerr = reg_ecr >> 16; 286 287 return 0; 288} 289 290static void at91_chip_start(struct net_device *dev) 291{ 292 struct at91_priv *priv = netdev_priv(dev); 293 u32 reg_mr, reg_ier; 294 295 /* disable interrupts */ 296 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 297 298 /* disable chip */ 299 reg_mr = at91_read(priv, AT91_MR); 300 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 301 302 at91_set_bittiming(dev); 303 at91_setup_mailboxes(dev); 304 at91_transceiver_switch(priv, 1); 305 306 /* enable chip */ 307 at91_write(priv, AT91_MR, AT91_MR_CANEN); 308 309 priv->can.state = CAN_STATE_ERROR_ACTIVE; 310 311 /* Enable interrupts */ 312 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 313 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 314 at91_write(priv, AT91_IER, reg_ier); 315} 316 317static void at91_chip_stop(struct net_device *dev, enum can_state state) 318{ 319 struct at91_priv *priv = netdev_priv(dev); 320 u32 reg_mr; 321 322 /* disable interrupts */ 323 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 324 325 reg_mr = at91_read(priv, AT91_MR); 326 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 327 328 at91_transceiver_switch(priv, 0); 329 priv->can.state = state; 330} 331 332/* 333 * theory of operation: 334 * 335 * According to the datasheet priority 0 is the highest priority, 15 336 * is the lowest. If two mailboxes have the same priority level the 337 * message of the mailbox with the lowest number is sent first. 338 * 339 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 340 * the next mailbox with prio 0, and so on, until all mailboxes are 341 * used. Then we start from the beginning with mailbox 342 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 343 * prio 1. When we reach the last mailbox with prio 15, we have to 344 * stop sending, waiting for all messages to be delivered, then start 345 * again with mailbox AT91_MB_TX_FIRST prio 0. 346 * 347 * We use the priv->tx_next as counter for the next transmission 348 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 349 * encode the mailbox number, the upper 4 bits the mailbox priority: 350 * 351 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 352 * (mb - AT91_MB_TX_FIRST); 353 * 354 */ 355static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 356{ 357 struct at91_priv *priv = netdev_priv(dev); 358 struct net_device_stats *stats = &dev->stats; 359 struct can_frame *cf = (struct can_frame *)skb->data; 360 unsigned int mb, prio; 361 u32 reg_mid, reg_mcr; 362 363 if (can_dropped_invalid_skb(dev, skb)) 364 return NETDEV_TX_OK; 365 366 mb = get_tx_next_mb(priv); 367 prio = get_tx_next_prio(priv); 368 369 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 370 netif_stop_queue(dev); 371 372 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 373 return NETDEV_TX_BUSY; 374 } 375 376 if (cf->can_id & CAN_EFF_FLAG) 377 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 378 else 379 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 380 381 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 382 (cf->can_dlc << 16) | AT91_MCR_MTCR; 383 384 /* disable MB while writing ID (see datasheet) */ 385 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 386 at91_write(priv, AT91_MID(mb), reg_mid); 387 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 388 389 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 390 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 391 392 /* This triggers transmission */ 393 at91_write(priv, AT91_MCR(mb), reg_mcr); 394 395 stats->tx_bytes += cf->can_dlc; 396 397 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 398 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 399 400 /* 401 * we have to stop the queue and deliver all messages in case 402 * of a prio+mb counter wrap around. This is the case if 403 * tx_next buffer prio and mailbox equals 0. 404 * 405 * also stop the queue if next buffer is still in use 406 * (== not ready) 407 */ 408 priv->tx_next++; 409 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 410 AT91_MSR_MRDY) || 411 (priv->tx_next & AT91_NEXT_MASK) == 0) 412 netif_stop_queue(dev); 413 414 /* Enable interrupt for this mailbox */ 415 at91_write(priv, AT91_IER, 1 << mb); 416 417 return NETDEV_TX_OK; 418} 419 420/** 421 * at91_activate_rx_low - activate lower rx mailboxes 422 * @priv: a91 context 423 * 424 * Reenables the lower mailboxes for reception of new CAN messages 425 */ 426static inline void at91_activate_rx_low(const struct at91_priv *priv) 427{ 428 u32 mask = AT91_MB_RX_LOW_MASK; 429 at91_write(priv, AT91_TCR, mask); 430} 431 432/** 433 * at91_activate_rx_mb - reactive single rx mailbox 434 * @priv: a91 context 435 * @mb: mailbox to reactivate 436 * 437 * Reenables given mailbox for reception of new CAN messages 438 */ 439static inline void at91_activate_rx_mb(const struct at91_priv *priv, 440 unsigned int mb) 441{ 442 u32 mask = 1 << mb; 443 at91_write(priv, AT91_TCR, mask); 444} 445 446/** 447 * at91_rx_overflow_err - send error frame due to rx overflow 448 * @dev: net device 449 */ 450static void at91_rx_overflow_err(struct net_device *dev) 451{ 452 struct net_device_stats *stats = &dev->stats; 453 struct sk_buff *skb; 454 struct can_frame *cf; 455 456 netdev_dbg(dev, "RX buffer overflow\n"); 457 stats->rx_over_errors++; 458 stats->rx_errors++; 459 460 skb = alloc_can_err_skb(dev, &cf); 461 if (unlikely(!skb)) 462 return; 463 464 cf->can_id |= CAN_ERR_CRTL; 465 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 466 netif_receive_skb(skb); 467 468 stats->rx_packets++; 469 stats->rx_bytes += cf->can_dlc; 470} 471 472/** 473 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 474 * @dev: net device 475 * @mb: mailbox number to read from 476 * @cf: can frame where to store message 477 * 478 * Reads a CAN message from the given mailbox and stores data into 479 * given can frame. "mb" and "cf" must be valid. 480 */ 481static void at91_read_mb(struct net_device *dev, unsigned int mb, 482 struct can_frame *cf) 483{ 484 const struct at91_priv *priv = netdev_priv(dev); 485 u32 reg_msr, reg_mid; 486 487 reg_mid = at91_read(priv, AT91_MID(mb)); 488 if (reg_mid & AT91_MID_MIDE) 489 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 490 else 491 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 492 493 reg_msr = at91_read(priv, AT91_MSR(mb)); 494 if (reg_msr & AT91_MSR_MRTR) 495 cf->can_id |= CAN_RTR_FLAG; 496 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 497 498 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 499 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 500 501 /* allow RX of extended frames */ 502 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 503 504 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 505 at91_rx_overflow_err(dev); 506} 507 508/** 509 * at91_read_msg - read CAN message from mailbox 510 * @dev: net device 511 * @mb: mail box to read from 512 * 513 * Reads a CAN message from given mailbox, and put into linux network 514 * RX queue, does all housekeeping chores (stats, ...) 515 */ 516static void at91_read_msg(struct net_device *dev, unsigned int mb) 517{ 518 struct net_device_stats *stats = &dev->stats; 519 struct can_frame *cf; 520 struct sk_buff *skb; 521 522 skb = alloc_can_skb(dev, &cf); 523 if (unlikely(!skb)) { 524 stats->rx_dropped++; 525 return; 526 } 527 528 at91_read_mb(dev, mb, cf); 529 netif_receive_skb(skb); 530 531 stats->rx_packets++; 532 stats->rx_bytes += cf->can_dlc; 533} 534 535/** 536 * at91_poll_rx - read multiple CAN messages from mailboxes 537 * @dev: net device 538 * @quota: max number of pkgs we're allowed to receive 539 * 540 * Theory of Operation: 541 * 542 * 12 of the 16 mailboxes on the chip are reserved for RX. we split 543 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes. 544 * 545 * Like it or not, but the chip always saves a received CAN message 546 * into the first free mailbox it finds (starting with the 547 * lowest). This makes it very difficult to read the messages in the 548 * right order from the chip. This is how we work around that problem: 549 * 550 * The first message goes into mb nr. 0 and issues an interrupt. All 551 * rx ints are disabled in the interrupt handler and a napi poll is 552 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 553 * receive another message). 554 * 555 * lower mbxs upper 556 * ______^______ __^__ 557 * / \ / \ 558 * +-+-+-+-+-+-+-+-++-+-+-+-+ 559 * |x|x|x|x|x|x|x|x|| | | | | 560 * +-+-+-+-+-+-+-+-++-+-+-+-+ 561 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 562 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 563 * 564 * The variable priv->rx_next points to the next mailbox to read a 565 * message from. As long we're in the lower mailboxes we just read the 566 * mailbox but not reenable it. 567 * 568 * With completion of the last of the lower mailboxes, we reenable the 569 * whole first group, but continue to look for filled mailboxes in the 570 * upper mailboxes. Imagine the second group like overflow mailboxes, 571 * which takes CAN messages if the lower goup is full. While in the 572 * upper group we reenable the mailbox right after reading it. Giving 573 * the chip more room to store messages. 574 * 575 * After finishing we look again in the lower group if we've still 576 * quota. 577 * 578 */ 579static int at91_poll_rx(struct net_device *dev, int quota) 580{ 581 struct at91_priv *priv = netdev_priv(dev); 582 u32 reg_sr = at91_read(priv, AT91_SR); 583 const unsigned long *addr = (unsigned long *)®_sr; 584 unsigned int mb; 585 int received = 0; 586 587 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 588 reg_sr & AT91_MB_RX_LOW_MASK) 589 netdev_info(dev, 590 "order of incoming frames cannot be guaranteed\n"); 591 592 again: 593 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next); 594 mb < AT91_MB_RX_NUM && quota > 0; 595 reg_sr = at91_read(priv, AT91_SR), 596 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) { 597 at91_read_msg(dev, mb); 598 599 /* reactivate mailboxes */ 600 if (mb == AT91_MB_RX_LOW_LAST) 601 /* all lower mailboxed, if just finished it */ 602 at91_activate_rx_low(priv); 603 else if (mb > AT91_MB_RX_LOW_LAST) 604 /* only the mailbox we read */ 605 at91_activate_rx_mb(priv, mb); 606 607 received++; 608 quota--; 609 } 610 611 /* upper group completed, look again in lower */ 612 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 613 quota > 0 && mb >= AT91_MB_RX_NUM) { 614 priv->rx_next = 0; 615 goto again; 616 } 617 618 return received; 619} 620 621static void at91_poll_err_frame(struct net_device *dev, 622 struct can_frame *cf, u32 reg_sr) 623{ 624 struct at91_priv *priv = netdev_priv(dev); 625 626 /* CRC error */ 627 if (reg_sr & AT91_IRQ_CERR) { 628 netdev_dbg(dev, "CERR irq\n"); 629 dev->stats.rx_errors++; 630 priv->can.can_stats.bus_error++; 631 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 632 } 633 634 /* Stuffing Error */ 635 if (reg_sr & AT91_IRQ_SERR) { 636 netdev_dbg(dev, "SERR irq\n"); 637 dev->stats.rx_errors++; 638 priv->can.can_stats.bus_error++; 639 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 640 cf->data[2] |= CAN_ERR_PROT_STUFF; 641 } 642 643 /* Acknowledgement Error */ 644 if (reg_sr & AT91_IRQ_AERR) { 645 netdev_dbg(dev, "AERR irq\n"); 646 dev->stats.tx_errors++; 647 cf->can_id |= CAN_ERR_ACK; 648 } 649 650 /* Form error */ 651 if (reg_sr & AT91_IRQ_FERR) { 652 netdev_dbg(dev, "FERR irq\n"); 653 dev->stats.rx_errors++; 654 priv->can.can_stats.bus_error++; 655 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 656 cf->data[2] |= CAN_ERR_PROT_FORM; 657 } 658 659 /* Bit Error */ 660 if (reg_sr & AT91_IRQ_BERR) { 661 netdev_dbg(dev, "BERR irq\n"); 662 dev->stats.tx_errors++; 663 priv->can.can_stats.bus_error++; 664 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 665 cf->data[2] |= CAN_ERR_PROT_BIT; 666 } 667} 668 669static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 670{ 671 struct sk_buff *skb; 672 struct can_frame *cf; 673 674 if (quota == 0) 675 return 0; 676 677 skb = alloc_can_err_skb(dev, &cf); 678 if (unlikely(!skb)) 679 return 0; 680 681 at91_poll_err_frame(dev, cf, reg_sr); 682 netif_receive_skb(skb); 683 684 dev->stats.rx_packets++; 685 dev->stats.rx_bytes += cf->can_dlc; 686 687 return 1; 688} 689 690static int at91_poll(struct napi_struct *napi, int quota) 691{ 692 struct net_device *dev = napi->dev; 693 const struct at91_priv *priv = netdev_priv(dev); 694 u32 reg_sr = at91_read(priv, AT91_SR); 695 int work_done = 0; 696 697 if (reg_sr & AT91_IRQ_MB_RX) 698 work_done += at91_poll_rx(dev, quota - work_done); 699 700 /* 701 * The error bits are clear on read, 702 * so use saved value from irq handler. 703 */ 704 reg_sr |= priv->reg_sr; 705 if (reg_sr & AT91_IRQ_ERR_FRAME) 706 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 707 708 if (work_done < quota) { 709 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 710 u32 reg_ier = AT91_IRQ_ERR_FRAME; 711 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 712 713 napi_complete(napi); 714 at91_write(priv, AT91_IER, reg_ier); 715 } 716 717 return work_done; 718} 719 720/* 721 * theory of operation: 722 * 723 * priv->tx_echo holds the number of the oldest can_frame put for 724 * transmission into the hardware, but not yet ACKed by the CAN tx 725 * complete IRQ. 726 * 727 * We iterate from priv->tx_echo to priv->tx_next and check if the 728 * packet has been transmitted, echo it back to the CAN framework. If 729 * we discover a not yet transmitted package, stop looking for more. 730 * 731 */ 732static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 733{ 734 struct at91_priv *priv = netdev_priv(dev); 735 u32 reg_msr; 736 unsigned int mb; 737 738 /* masking of reg_sr not needed, already done by at91_irq */ 739 740 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 741 mb = get_tx_echo_mb(priv); 742 743 /* no event in mailbox? */ 744 if (!(reg_sr & (1 << mb))) 745 break; 746 747 /* Disable irq for this TX mailbox */ 748 at91_write(priv, AT91_IDR, 1 << mb); 749 750 /* 751 * only echo if mailbox signals us a transfer 752 * complete (MSR_MRDY). Otherwise it's a tansfer 753 * abort. "can_bus_off()" takes care about the skbs 754 * parked in the echo queue. 755 */ 756 reg_msr = at91_read(priv, AT91_MSR(mb)); 757 if (likely(reg_msr & AT91_MSR_MRDY && 758 ~reg_msr & AT91_MSR_MABT)) { 759 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 760 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 761 dev->stats.tx_packets++; 762 } 763 } 764 765 /* 766 * restart queue if we don't have a wrap around but restart if 767 * we get a TX int for the last can frame directly before a 768 * wrap around. 769 */ 770 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 771 (priv->tx_echo & AT91_NEXT_MASK) == 0) 772 netif_wake_queue(dev); 773} 774 775static void at91_irq_err_state(struct net_device *dev, 776 struct can_frame *cf, enum can_state new_state) 777{ 778 struct at91_priv *priv = netdev_priv(dev); 779 u32 reg_idr = 0, reg_ier = 0; 780 struct can_berr_counter bec; 781 782 at91_get_berr_counter(dev, &bec); 783 784 switch (priv->can.state) { 785 case CAN_STATE_ERROR_ACTIVE: 786 /* 787 * from: ERROR_ACTIVE 788 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 789 * => : there was a warning int 790 */ 791 if (new_state >= CAN_STATE_ERROR_WARNING && 792 new_state <= CAN_STATE_BUS_OFF) { 793 netdev_dbg(dev, "Error Warning IRQ\n"); 794 priv->can.can_stats.error_warning++; 795 796 cf->can_id |= CAN_ERR_CRTL; 797 cf->data[1] = (bec.txerr > bec.rxerr) ? 798 CAN_ERR_CRTL_TX_WARNING : 799 CAN_ERR_CRTL_RX_WARNING; 800 } 801 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 802 /* 803 * from: ERROR_ACTIVE, ERROR_WARNING 804 * to : ERROR_PASSIVE, BUS_OFF 805 * => : error passive int 806 */ 807 if (new_state >= CAN_STATE_ERROR_PASSIVE && 808 new_state <= CAN_STATE_BUS_OFF) { 809 netdev_dbg(dev, "Error Passive IRQ\n"); 810 priv->can.can_stats.error_passive++; 811 812 cf->can_id |= CAN_ERR_CRTL; 813 cf->data[1] = (bec.txerr > bec.rxerr) ? 814 CAN_ERR_CRTL_TX_PASSIVE : 815 CAN_ERR_CRTL_RX_PASSIVE; 816 } 817 break; 818 case CAN_STATE_BUS_OFF: 819 /* 820 * from: BUS_OFF 821 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 822 */ 823 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 824 cf->can_id |= CAN_ERR_RESTARTED; 825 826 netdev_dbg(dev, "restarted\n"); 827 priv->can.can_stats.restarts++; 828 829 netif_carrier_on(dev); 830 netif_wake_queue(dev); 831 } 832 break; 833 default: 834 break; 835 } 836 837 838 /* process state changes depending on the new state */ 839 switch (new_state) { 840 case CAN_STATE_ERROR_ACTIVE: 841 /* 842 * actually we want to enable AT91_IRQ_WARN here, but 843 * it screws up the system under certain 844 * circumstances. so just enable AT91_IRQ_ERRP, thus 845 * the "fallthrough" 846 */ 847 netdev_dbg(dev, "Error Active\n"); 848 cf->can_id |= CAN_ERR_PROT; 849 cf->data[2] = CAN_ERR_PROT_ACTIVE; 850 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 851 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 852 reg_ier = AT91_IRQ_ERRP; 853 break; 854 case CAN_STATE_ERROR_PASSIVE: 855 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 856 reg_ier = AT91_IRQ_BOFF; 857 break; 858 case CAN_STATE_BUS_OFF: 859 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 860 AT91_IRQ_WARN | AT91_IRQ_BOFF; 861 reg_ier = 0; 862 863 cf->can_id |= CAN_ERR_BUSOFF; 864 865 netdev_dbg(dev, "bus-off\n"); 866 netif_carrier_off(dev); 867 priv->can.can_stats.bus_off++; 868 869 /* turn off chip, if restart is disabled */ 870 if (!priv->can.restart_ms) { 871 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 872 return; 873 } 874 break; 875 default: 876 break; 877 } 878 879 at91_write(priv, AT91_IDR, reg_idr); 880 at91_write(priv, AT91_IER, reg_ier); 881} 882 883static void at91_irq_err(struct net_device *dev) 884{ 885 struct at91_priv *priv = netdev_priv(dev); 886 struct sk_buff *skb; 887 struct can_frame *cf; 888 enum can_state new_state; 889 u32 reg_sr; 890 891 reg_sr = at91_read(priv, AT91_SR); 892 893 /* we need to look at the unmasked reg_sr */ 894 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 895 new_state = CAN_STATE_BUS_OFF; 896 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 897 new_state = CAN_STATE_ERROR_PASSIVE; 898 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 899 new_state = CAN_STATE_ERROR_WARNING; 900 else if (likely(reg_sr & AT91_IRQ_ERRA)) 901 new_state = CAN_STATE_ERROR_ACTIVE; 902 else { 903 netdev_err(dev, "BUG! hardware in undefined state\n"); 904 return; 905 } 906 907 /* state hasn't changed */ 908 if (likely(new_state == priv->can.state)) 909 return; 910 911 skb = alloc_can_err_skb(dev, &cf); 912 if (unlikely(!skb)) 913 return; 914 915 at91_irq_err_state(dev, cf, new_state); 916 netif_rx(skb); 917 918 dev->stats.rx_packets++; 919 dev->stats.rx_bytes += cf->can_dlc; 920 921 priv->can.state = new_state; 922} 923 924/* 925 * interrupt handler 926 */ 927static irqreturn_t at91_irq(int irq, void *dev_id) 928{ 929 struct net_device *dev = dev_id; 930 struct at91_priv *priv = netdev_priv(dev); 931 irqreturn_t handled = IRQ_NONE; 932 u32 reg_sr, reg_imr; 933 934 reg_sr = at91_read(priv, AT91_SR); 935 reg_imr = at91_read(priv, AT91_IMR); 936 937 /* Ignore masked interrupts */ 938 reg_sr &= reg_imr; 939 if (!reg_sr) 940 goto exit; 941 942 handled = IRQ_HANDLED; 943 944 /* Receive or error interrupt? -> napi */ 945 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 946 /* 947 * The error bits are clear on read, 948 * save for later use. 949 */ 950 priv->reg_sr = reg_sr; 951 at91_write(priv, AT91_IDR, 952 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 953 napi_schedule(&priv->napi); 954 } 955 956 /* Transmission complete interrupt */ 957 if (reg_sr & AT91_IRQ_MB_TX) 958 at91_irq_tx(dev, reg_sr); 959 960 at91_irq_err(dev); 961 962 exit: 963 return handled; 964} 965 966static int at91_open(struct net_device *dev) 967{ 968 struct at91_priv *priv = netdev_priv(dev); 969 int err; 970 971 clk_enable(priv->clk); 972 973 /* check or determine and set bittime */ 974 err = open_candev(dev); 975 if (err) 976 goto out; 977 978 /* register interrupt handler */ 979 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 980 dev->name, dev)) { 981 err = -EAGAIN; 982 goto out_close; 983 } 984 985 /* start chip and queuing */ 986 at91_chip_start(dev); 987 napi_enable(&priv->napi); 988 netif_start_queue(dev); 989 990 return 0; 991 992 out_close: 993 close_candev(dev); 994 out: 995 clk_disable(priv->clk); 996 997 return err; 998} 999 1000/* 1001 * stop CAN bus activity 1002 */ 1003static int at91_close(struct net_device *dev) 1004{ 1005 struct at91_priv *priv = netdev_priv(dev); 1006 1007 netif_stop_queue(dev); 1008 napi_disable(&priv->napi); 1009 at91_chip_stop(dev, CAN_STATE_STOPPED); 1010 1011 free_irq(dev->irq, dev); 1012 clk_disable(priv->clk); 1013 1014 close_candev(dev); 1015 1016 return 0; 1017} 1018 1019static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1020{ 1021 switch (mode) { 1022 case CAN_MODE_START: 1023 at91_chip_start(dev); 1024 netif_wake_queue(dev); 1025 break; 1026 1027 default: 1028 return -EOPNOTSUPP; 1029 } 1030 1031 return 0; 1032} 1033 1034static const struct net_device_ops at91_netdev_ops = { 1035 .ndo_open = at91_open, 1036 .ndo_stop = at91_close, 1037 .ndo_start_xmit = at91_start_xmit, 1038}; 1039 1040static int __devinit at91_can_probe(struct platform_device *pdev) 1041{ 1042 struct net_device *dev; 1043 struct at91_priv *priv; 1044 struct resource *res; 1045 struct clk *clk; 1046 void __iomem *addr; 1047 int err, irq; 1048 1049 clk = clk_get(&pdev->dev, "can_clk"); 1050 if (IS_ERR(clk)) { 1051 dev_err(&pdev->dev, "no clock defined\n"); 1052 err = -ENODEV; 1053 goto exit; 1054 } 1055 1056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1057 irq = platform_get_irq(pdev, 0); 1058 if (!res || irq <= 0) { 1059 err = -ENODEV; 1060 goto exit_put; 1061 } 1062 1063 if (!request_mem_region(res->start, 1064 resource_size(res), 1065 pdev->name)) { 1066 err = -EBUSY; 1067 goto exit_put; 1068 } 1069 1070 addr = ioremap_nocache(res->start, resource_size(res)); 1071 if (!addr) { 1072 err = -ENOMEM; 1073 goto exit_release; 1074 } 1075 1076 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1077 if (!dev) { 1078 err = -ENOMEM; 1079 goto exit_iounmap; 1080 } 1081 1082 dev->netdev_ops = &at91_netdev_ops; 1083 dev->irq = irq; 1084 dev->flags |= IFF_ECHO; 1085 1086 priv = netdev_priv(dev); 1087 priv->can.clock.freq = clk_get_rate(clk); 1088 priv->can.bittiming_const = &at91_bittiming_const; 1089 priv->can.do_set_mode = at91_set_mode; 1090 priv->can.do_get_berr_counter = at91_get_berr_counter; 1091 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1092 priv->reg_base = addr; 1093 priv->dev = dev; 1094 priv->clk = clk; 1095 priv->pdata = pdev->dev.platform_data; 1096 1097 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1098 1099 dev_set_drvdata(&pdev->dev, dev); 1100 SET_NETDEV_DEV(dev, &pdev->dev); 1101 1102 err = register_candev(dev); 1103 if (err) { 1104 dev_err(&pdev->dev, "registering netdev failed\n"); 1105 goto exit_free; 1106 } 1107 1108 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1109 priv->reg_base, dev->irq); 1110 1111 return 0; 1112 1113 exit_free: 1114 free_candev(dev); 1115 exit_iounmap: 1116 iounmap(addr); 1117 exit_release: 1118 release_mem_region(res->start, resource_size(res)); 1119 exit_put: 1120 clk_put(clk); 1121 exit: 1122 return err; 1123} 1124 1125static int __devexit at91_can_remove(struct platform_device *pdev) 1126{ 1127 struct net_device *dev = platform_get_drvdata(pdev); 1128 struct at91_priv *priv = netdev_priv(dev); 1129 struct resource *res; 1130 1131 unregister_netdev(dev); 1132 1133 platform_set_drvdata(pdev, NULL); 1134 1135 iounmap(priv->reg_base); 1136 1137 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1138 release_mem_region(res->start, resource_size(res)); 1139 1140 clk_put(priv->clk); 1141 1142 free_candev(dev); 1143 1144 return 0; 1145} 1146 1147static struct platform_driver at91_can_driver = { 1148 .probe = at91_can_probe, 1149 .remove = __devexit_p(at91_can_remove), 1150 .driver = { 1151 .name = KBUILD_MODNAME, 1152 .owner = THIS_MODULE, 1153 }, 1154}; 1155 1156static int __init at91_can_module_init(void) 1157{ 1158 return platform_driver_register(&at91_can_driver); 1159} 1160 1161static void __exit at91_can_module_exit(void) 1162{ 1163 platform_driver_unregister(&at91_can_driver); 1164} 1165 1166module_init(at91_can_module_init); 1167module_exit(at91_can_module_exit); 1168 1169MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1170MODULE_LICENSE("GPL v2"); 1171MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1172