at91_can.c revision 79008997e232ad1d871bb6fedfb7fbd77ea95af8
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/rtnetlink.h> 34#include <linux/skbuff.h> 35#include <linux/spinlock.h> 36#include <linux/string.h> 37#include <linux/types.h> 38 39#include <linux/can/dev.h> 40#include <linux/can/error.h> 41 42#include <mach/board.h> 43 44#define AT91_NAPI_WEIGHT 11 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_TX_SHIFT 2 51 52#define AT91_MB_RX_FIRST 1 53#define AT91_MB_RX_LAST 11 54 55#define AT91_MB_MASK(i) ((1 << (i)) - 1) 56#define AT91_MB_RX_SPLIT 8 57 58 59/* Common registers */ 60enum at91_reg { 61 AT91_MR = 0x000, 62 AT91_IER = 0x004, 63 AT91_IDR = 0x008, 64 AT91_IMR = 0x00C, 65 AT91_SR = 0x010, 66 AT91_BR = 0x014, 67 AT91_TIM = 0x018, 68 AT91_TIMESTP = 0x01C, 69 AT91_ECR = 0x020, 70 AT91_TCR = 0x024, 71 AT91_ACR = 0x028, 72}; 73 74/* Mailbox registers (0 <= i <= 15) */ 75#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 76#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 77#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 78#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 79#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 80#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 81#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 82#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 83 84/* Register bits */ 85#define AT91_MR_CANEN BIT(0) 86#define AT91_MR_LPM BIT(1) 87#define AT91_MR_ABM BIT(2) 88#define AT91_MR_OVL BIT(3) 89#define AT91_MR_TEOF BIT(4) 90#define AT91_MR_TTM BIT(5) 91#define AT91_MR_TIMFRZ BIT(6) 92#define AT91_MR_DRPT BIT(7) 93 94#define AT91_SR_RBSY BIT(29) 95 96#define AT91_MMR_PRIO_SHIFT (16) 97 98#define AT91_MID_MIDE BIT(29) 99 100#define AT91_MSR_MRTR BIT(20) 101#define AT91_MSR_MABT BIT(22) 102#define AT91_MSR_MRDY BIT(23) 103#define AT91_MSR_MMI BIT(24) 104 105#define AT91_MCR_MRTR BIT(20) 106#define AT91_MCR_MTCR BIT(23) 107 108/* Mailbox Modes */ 109enum at91_mb_mode { 110 AT91_MB_MODE_DISABLED = 0, 111 AT91_MB_MODE_RX = 1, 112 AT91_MB_MODE_RX_OVRWR = 2, 113 AT91_MB_MODE_TX = 3, 114 AT91_MB_MODE_CONSUMER = 4, 115 AT91_MB_MODE_PRODUCER = 5, 116}; 117 118/* Interrupt mask bits */ 119#define AT91_IRQ_ERRA (1 << 16) 120#define AT91_IRQ_WARN (1 << 17) 121#define AT91_IRQ_ERRP (1 << 18) 122#define AT91_IRQ_BOFF (1 << 19) 123#define AT91_IRQ_SLEEP (1 << 20) 124#define AT91_IRQ_WAKEUP (1 << 21) 125#define AT91_IRQ_TOVF (1 << 22) 126#define AT91_IRQ_TSTP (1 << 23) 127#define AT91_IRQ_CERR (1 << 24) 128#define AT91_IRQ_SERR (1 << 25) 129#define AT91_IRQ_AERR (1 << 26) 130#define AT91_IRQ_FERR (1 << 27) 131#define AT91_IRQ_BERR (1 << 28) 132 133#define AT91_IRQ_ERR_ALL (0x1fff0000) 134#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 135 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 136#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 137 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 138 139#define AT91_IRQ_ALL (0x1fffffff) 140 141struct at91_priv { 142 struct can_priv can; /* must be the first member! */ 143 struct net_device *dev; 144 struct napi_struct napi; 145 146 void __iomem *reg_base; 147 148 u32 reg_sr; 149 unsigned int tx_next; 150 unsigned int tx_echo; 151 unsigned int rx_next; 152 153 struct clk *clk; 154 struct at91_can_data *pdata; 155 156 canid_t mb0_id; 157}; 158 159static struct can_bittiming_const at91_bittiming_const = { 160 .name = KBUILD_MODNAME, 161 .tseg1_min = 4, 162 .tseg1_max = 16, 163 .tseg2_min = 2, 164 .tseg2_max = 8, 165 .sjw_max = 4, 166 .brp_min = 2, 167 .brp_max = 128, 168 .brp_inc = 1, 169}; 170 171static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 172{ 173 return AT91_MB_RX_SPLIT - 1; 174} 175 176static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 177{ 178 return AT91_MB_MASK(AT91_MB_RX_SPLIT) & 179 ~AT91_MB_MASK(AT91_MB_RX_FIRST); 180} 181 182static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 183{ 184 return 1 << AT91_MB_TX_SHIFT; 185} 186 187static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 188{ 189 return AT91_MB_RX_LAST + 1; 190} 191 192static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 193{ 194 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 195} 196 197static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 198{ 199 return AT91_MB_TX_SHIFT; 200} 201 202static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 203{ 204 return 0xf << AT91_MB_TX_SHIFT; 205} 206 207static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 208{ 209 return AT91_MB_MASK(AT91_MB_TX_SHIFT); 210} 211 212static inline unsigned int get_next_mask(const struct at91_priv *priv) 213{ 214 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 215} 216 217static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 218{ 219 return AT91_MB_MASK(AT91_MB_RX_LAST + 1) & 220 ~AT91_MB_MASK(AT91_MB_RX_FIRST); 221} 222 223static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 224{ 225 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 226 ~AT91_MB_MASK(get_mb_tx_first(priv)); 227} 228 229static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 230{ 231 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 232} 233 234static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 235{ 236 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 237} 238 239static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 240{ 241 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 242} 243 244static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 245{ 246 return __raw_readl(priv->reg_base + reg); 247} 248 249static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 250 u32 value) 251{ 252 __raw_writel(value, priv->reg_base + reg); 253} 254 255static inline void set_mb_mode_prio(const struct at91_priv *priv, 256 unsigned int mb, enum at91_mb_mode mode, int prio) 257{ 258 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 259} 260 261static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 262 enum at91_mb_mode mode) 263{ 264 set_mb_mode_prio(priv, mb, mode, 0); 265} 266 267static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 268{ 269 u32 reg_mid; 270 271 if (can_id & CAN_EFF_FLAG) 272 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 273 else 274 reg_mid = (can_id & CAN_SFF_MASK) << 18; 275 276 return reg_mid; 277} 278 279/* 280 * Swtich transceiver on or off 281 */ 282static void at91_transceiver_switch(const struct at91_priv *priv, int on) 283{ 284 if (priv->pdata && priv->pdata->transceiver_switch) 285 priv->pdata->transceiver_switch(on); 286} 287 288static void at91_setup_mailboxes(struct net_device *dev) 289{ 290 struct at91_priv *priv = netdev_priv(dev); 291 unsigned int i; 292 u32 reg_mid; 293 294 /* 295 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 296 * mailbox is disabled. The next 11 mailboxes are used as a 297 * reception FIFO. The last mailbox is configured with 298 * overwrite option. The overwrite flag indicates a FIFO 299 * overflow. 300 */ 301 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 302 for (i = 0; i < AT91_MB_RX_FIRST; i++) { 303 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 304 at91_write(priv, AT91_MID(i), reg_mid); 305 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 306 } 307 308 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 309 set_mb_mode(priv, i, AT91_MB_MODE_RX); 310 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 311 312 /* reset acceptance mask and id register */ 313 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 314 at91_write(priv, AT91_MAM(i), 0x0); 315 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 316 } 317 318 /* The last 4 mailboxes are used for transmitting. */ 319 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 320 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 321 322 /* Reset tx and rx helper pointers */ 323 priv->tx_next = priv->tx_echo = 0; 324 priv->rx_next = AT91_MB_RX_FIRST; 325} 326 327static int at91_set_bittiming(struct net_device *dev) 328{ 329 const struct at91_priv *priv = netdev_priv(dev); 330 const struct can_bittiming *bt = &priv->can.bittiming; 331 u32 reg_br; 332 333 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 334 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 335 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 336 ((bt->phase_seg2 - 1) << 0); 337 338 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 339 340 at91_write(priv, AT91_BR, reg_br); 341 342 return 0; 343} 344 345static int at91_get_berr_counter(const struct net_device *dev, 346 struct can_berr_counter *bec) 347{ 348 const struct at91_priv *priv = netdev_priv(dev); 349 u32 reg_ecr = at91_read(priv, AT91_ECR); 350 351 bec->rxerr = reg_ecr & 0xff; 352 bec->txerr = reg_ecr >> 16; 353 354 return 0; 355} 356 357static void at91_chip_start(struct net_device *dev) 358{ 359 struct at91_priv *priv = netdev_priv(dev); 360 u32 reg_mr, reg_ier; 361 362 /* disable interrupts */ 363 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 364 365 /* disable chip */ 366 reg_mr = at91_read(priv, AT91_MR); 367 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 368 369 at91_set_bittiming(dev); 370 at91_setup_mailboxes(dev); 371 at91_transceiver_switch(priv, 1); 372 373 /* enable chip */ 374 at91_write(priv, AT91_MR, AT91_MR_CANEN); 375 376 priv->can.state = CAN_STATE_ERROR_ACTIVE; 377 378 /* Enable interrupts */ 379 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 380 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 381 at91_write(priv, AT91_IER, reg_ier); 382} 383 384static void at91_chip_stop(struct net_device *dev, enum can_state state) 385{ 386 struct at91_priv *priv = netdev_priv(dev); 387 u32 reg_mr; 388 389 /* disable interrupts */ 390 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 391 392 reg_mr = at91_read(priv, AT91_MR); 393 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 394 395 at91_transceiver_switch(priv, 0); 396 priv->can.state = state; 397} 398 399/* 400 * theory of operation: 401 * 402 * According to the datasheet priority 0 is the highest priority, 15 403 * is the lowest. If two mailboxes have the same priority level the 404 * message of the mailbox with the lowest number is sent first. 405 * 406 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 407 * the next mailbox with prio 0, and so on, until all mailboxes are 408 * used. Then we start from the beginning with mailbox 409 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 410 * prio 1. When we reach the last mailbox with prio 15, we have to 411 * stop sending, waiting for all messages to be delivered, then start 412 * again with mailbox AT91_MB_TX_FIRST prio 0. 413 * 414 * We use the priv->tx_next as counter for the next transmission 415 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 416 * encode the mailbox number, the upper 4 bits the mailbox priority: 417 * 418 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) | 419 * (mb - AT91_MB_TX_FIRST); 420 * 421 */ 422static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 423{ 424 struct at91_priv *priv = netdev_priv(dev); 425 struct net_device_stats *stats = &dev->stats; 426 struct can_frame *cf = (struct can_frame *)skb->data; 427 unsigned int mb, prio; 428 u32 reg_mid, reg_mcr; 429 430 if (can_dropped_invalid_skb(dev, skb)) 431 return NETDEV_TX_OK; 432 433 mb = get_tx_next_mb(priv); 434 prio = get_tx_next_prio(priv); 435 436 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 437 netif_stop_queue(dev); 438 439 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 440 return NETDEV_TX_BUSY; 441 } 442 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 443 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 444 (cf->can_dlc << 16) | AT91_MCR_MTCR; 445 446 /* disable MB while writing ID (see datasheet) */ 447 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 448 at91_write(priv, AT91_MID(mb), reg_mid); 449 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 450 451 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 452 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 453 454 /* This triggers transmission */ 455 at91_write(priv, AT91_MCR(mb), reg_mcr); 456 457 stats->tx_bytes += cf->can_dlc; 458 459 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 460 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv)); 461 462 /* 463 * we have to stop the queue and deliver all messages in case 464 * of a prio+mb counter wrap around. This is the case if 465 * tx_next buffer prio and mailbox equals 0. 466 * 467 * also stop the queue if next buffer is still in use 468 * (== not ready) 469 */ 470 priv->tx_next++; 471 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 472 AT91_MSR_MRDY) || 473 (priv->tx_next & get_next_mask(priv)) == 0) 474 netif_stop_queue(dev); 475 476 /* Enable interrupt for this mailbox */ 477 at91_write(priv, AT91_IER, 1 << mb); 478 479 return NETDEV_TX_OK; 480} 481 482/** 483 * at91_activate_rx_low - activate lower rx mailboxes 484 * @priv: a91 context 485 * 486 * Reenables the lower mailboxes for reception of new CAN messages 487 */ 488static inline void at91_activate_rx_low(const struct at91_priv *priv) 489{ 490 u32 mask = get_mb_rx_low_mask(priv); 491 at91_write(priv, AT91_TCR, mask); 492} 493 494/** 495 * at91_activate_rx_mb - reactive single rx mailbox 496 * @priv: a91 context 497 * @mb: mailbox to reactivate 498 * 499 * Reenables given mailbox for reception of new CAN messages 500 */ 501static inline void at91_activate_rx_mb(const struct at91_priv *priv, 502 unsigned int mb) 503{ 504 u32 mask = 1 << mb; 505 at91_write(priv, AT91_TCR, mask); 506} 507 508/** 509 * at91_rx_overflow_err - send error frame due to rx overflow 510 * @dev: net device 511 */ 512static void at91_rx_overflow_err(struct net_device *dev) 513{ 514 struct net_device_stats *stats = &dev->stats; 515 struct sk_buff *skb; 516 struct can_frame *cf; 517 518 netdev_dbg(dev, "RX buffer overflow\n"); 519 stats->rx_over_errors++; 520 stats->rx_errors++; 521 522 skb = alloc_can_err_skb(dev, &cf); 523 if (unlikely(!skb)) 524 return; 525 526 cf->can_id |= CAN_ERR_CRTL; 527 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 528 netif_receive_skb(skb); 529 530 stats->rx_packets++; 531 stats->rx_bytes += cf->can_dlc; 532} 533 534/** 535 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 536 * @dev: net device 537 * @mb: mailbox number to read from 538 * @cf: can frame where to store message 539 * 540 * Reads a CAN message from the given mailbox and stores data into 541 * given can frame. "mb" and "cf" must be valid. 542 */ 543static void at91_read_mb(struct net_device *dev, unsigned int mb, 544 struct can_frame *cf) 545{ 546 const struct at91_priv *priv = netdev_priv(dev); 547 u32 reg_msr, reg_mid; 548 549 reg_mid = at91_read(priv, AT91_MID(mb)); 550 if (reg_mid & AT91_MID_MIDE) 551 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 552 else 553 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 554 555 reg_msr = at91_read(priv, AT91_MSR(mb)); 556 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 557 558 if (reg_msr & AT91_MSR_MRTR) 559 cf->can_id |= CAN_RTR_FLAG; 560 else { 561 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 562 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 563 } 564 565 /* allow RX of extended frames */ 566 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 567 568 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 569 at91_rx_overflow_err(dev); 570} 571 572/** 573 * at91_read_msg - read CAN message from mailbox 574 * @dev: net device 575 * @mb: mail box to read from 576 * 577 * Reads a CAN message from given mailbox, and put into linux network 578 * RX queue, does all housekeeping chores (stats, ...) 579 */ 580static void at91_read_msg(struct net_device *dev, unsigned int mb) 581{ 582 struct net_device_stats *stats = &dev->stats; 583 struct can_frame *cf; 584 struct sk_buff *skb; 585 586 skb = alloc_can_skb(dev, &cf); 587 if (unlikely(!skb)) { 588 stats->rx_dropped++; 589 return; 590 } 591 592 at91_read_mb(dev, mb, cf); 593 netif_receive_skb(skb); 594 595 stats->rx_packets++; 596 stats->rx_bytes += cf->can_dlc; 597} 598 599/** 600 * at91_poll_rx - read multiple CAN messages from mailboxes 601 * @dev: net device 602 * @quota: max number of pkgs we're allowed to receive 603 * 604 * Theory of Operation: 605 * 606 * 11 of the 16 mailboxes on the chip are reserved for RX. we split 607 * them into 2 groups. The lower group holds 7 and upper 4 mailboxes. 608 * 609 * Like it or not, but the chip always saves a received CAN message 610 * into the first free mailbox it finds (starting with the 611 * lowest). This makes it very difficult to read the messages in the 612 * right order from the chip. This is how we work around that problem: 613 * 614 * The first message goes into mb nr. 1 and issues an interrupt. All 615 * rx ints are disabled in the interrupt handler and a napi poll is 616 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 617 * receive another message). 618 * 619 * lower mbxs upper 620 * ____^______ __^__ 621 * / \ / \ 622 * +-+-+-+-+-+-+-+-++-+-+-+-+ 623 * | |x|x|x|x|x|x|x|| | | | | 624 * +-+-+-+-+-+-+-+-++-+-+-+-+ 625 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 626 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 627 * ^ 628 * | 629 * \ 630 * unused, due to chip bug 631 * 632 * The variable priv->rx_next points to the next mailbox to read a 633 * message from. As long we're in the lower mailboxes we just read the 634 * mailbox but not reenable it. 635 * 636 * With completion of the last of the lower mailboxes, we reenable the 637 * whole first group, but continue to look for filled mailboxes in the 638 * upper mailboxes. Imagine the second group like overflow mailboxes, 639 * which takes CAN messages if the lower goup is full. While in the 640 * upper group we reenable the mailbox right after reading it. Giving 641 * the chip more room to store messages. 642 * 643 * After finishing we look again in the lower group if we've still 644 * quota. 645 * 646 */ 647static int at91_poll_rx(struct net_device *dev, int quota) 648{ 649 struct at91_priv *priv = netdev_priv(dev); 650 u32 reg_sr = at91_read(priv, AT91_SR); 651 const unsigned long *addr = (unsigned long *)®_sr; 652 unsigned int mb; 653 int received = 0; 654 655 if (priv->rx_next > get_mb_rx_low_last(priv) && 656 reg_sr & get_mb_rx_low_mask(priv)) 657 netdev_info(dev, 658 "order of incoming frames cannot be guaranteed\n"); 659 660 again: 661 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 662 mb < get_mb_tx_first(priv) && quota > 0; 663 reg_sr = at91_read(priv, AT91_SR), 664 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 665 at91_read_msg(dev, mb); 666 667 /* reactivate mailboxes */ 668 if (mb == get_mb_rx_low_last(priv)) 669 /* all lower mailboxed, if just finished it */ 670 at91_activate_rx_low(priv); 671 else if (mb > get_mb_rx_low_last(priv)) 672 /* only the mailbox we read */ 673 at91_activate_rx_mb(priv, mb); 674 675 received++; 676 quota--; 677 } 678 679 /* upper group completed, look again in lower */ 680 if (priv->rx_next > get_mb_rx_low_last(priv) && 681 quota > 0 && mb > AT91_MB_RX_LAST) { 682 priv->rx_next = AT91_MB_RX_FIRST; 683 goto again; 684 } 685 686 return received; 687} 688 689static void at91_poll_err_frame(struct net_device *dev, 690 struct can_frame *cf, u32 reg_sr) 691{ 692 struct at91_priv *priv = netdev_priv(dev); 693 694 /* CRC error */ 695 if (reg_sr & AT91_IRQ_CERR) { 696 netdev_dbg(dev, "CERR irq\n"); 697 dev->stats.rx_errors++; 698 priv->can.can_stats.bus_error++; 699 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 700 } 701 702 /* Stuffing Error */ 703 if (reg_sr & AT91_IRQ_SERR) { 704 netdev_dbg(dev, "SERR irq\n"); 705 dev->stats.rx_errors++; 706 priv->can.can_stats.bus_error++; 707 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 708 cf->data[2] |= CAN_ERR_PROT_STUFF; 709 } 710 711 /* Acknowledgement Error */ 712 if (reg_sr & AT91_IRQ_AERR) { 713 netdev_dbg(dev, "AERR irq\n"); 714 dev->stats.tx_errors++; 715 cf->can_id |= CAN_ERR_ACK; 716 } 717 718 /* Form error */ 719 if (reg_sr & AT91_IRQ_FERR) { 720 netdev_dbg(dev, "FERR irq\n"); 721 dev->stats.rx_errors++; 722 priv->can.can_stats.bus_error++; 723 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 724 cf->data[2] |= CAN_ERR_PROT_FORM; 725 } 726 727 /* Bit Error */ 728 if (reg_sr & AT91_IRQ_BERR) { 729 netdev_dbg(dev, "BERR irq\n"); 730 dev->stats.tx_errors++; 731 priv->can.can_stats.bus_error++; 732 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 733 cf->data[2] |= CAN_ERR_PROT_BIT; 734 } 735} 736 737static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 738{ 739 struct sk_buff *skb; 740 struct can_frame *cf; 741 742 if (quota == 0) 743 return 0; 744 745 skb = alloc_can_err_skb(dev, &cf); 746 if (unlikely(!skb)) 747 return 0; 748 749 at91_poll_err_frame(dev, cf, reg_sr); 750 netif_receive_skb(skb); 751 752 dev->stats.rx_packets++; 753 dev->stats.rx_bytes += cf->can_dlc; 754 755 return 1; 756} 757 758static int at91_poll(struct napi_struct *napi, int quota) 759{ 760 struct net_device *dev = napi->dev; 761 const struct at91_priv *priv = netdev_priv(dev); 762 u32 reg_sr = at91_read(priv, AT91_SR); 763 int work_done = 0; 764 765 if (reg_sr & get_irq_mb_rx(priv)) 766 work_done += at91_poll_rx(dev, quota - work_done); 767 768 /* 769 * The error bits are clear on read, 770 * so use saved value from irq handler. 771 */ 772 reg_sr |= priv->reg_sr; 773 if (reg_sr & AT91_IRQ_ERR_FRAME) 774 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 775 776 if (work_done < quota) { 777 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 778 u32 reg_ier = AT91_IRQ_ERR_FRAME; 779 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 780 781 napi_complete(napi); 782 at91_write(priv, AT91_IER, reg_ier); 783 } 784 785 return work_done; 786} 787 788/* 789 * theory of operation: 790 * 791 * priv->tx_echo holds the number of the oldest can_frame put for 792 * transmission into the hardware, but not yet ACKed by the CAN tx 793 * complete IRQ. 794 * 795 * We iterate from priv->tx_echo to priv->tx_next and check if the 796 * packet has been transmitted, echo it back to the CAN framework. If 797 * we discover a not yet transmitted package, stop looking for more. 798 * 799 */ 800static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 801{ 802 struct at91_priv *priv = netdev_priv(dev); 803 u32 reg_msr; 804 unsigned int mb; 805 806 /* masking of reg_sr not needed, already done by at91_irq */ 807 808 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 809 mb = get_tx_echo_mb(priv); 810 811 /* no event in mailbox? */ 812 if (!(reg_sr & (1 << mb))) 813 break; 814 815 /* Disable irq for this TX mailbox */ 816 at91_write(priv, AT91_IDR, 1 << mb); 817 818 /* 819 * only echo if mailbox signals us a transfer 820 * complete (MSR_MRDY). Otherwise it's a tansfer 821 * abort. "can_bus_off()" takes care about the skbs 822 * parked in the echo queue. 823 */ 824 reg_msr = at91_read(priv, AT91_MSR(mb)); 825 if (likely(reg_msr & AT91_MSR_MRDY && 826 ~reg_msr & AT91_MSR_MABT)) { 827 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 828 can_get_echo_skb(dev, mb - get_mb_tx_first(priv)); 829 dev->stats.tx_packets++; 830 } 831 } 832 833 /* 834 * restart queue if we don't have a wrap around but restart if 835 * we get a TX int for the last can frame directly before a 836 * wrap around. 837 */ 838 if ((priv->tx_next & get_next_mask(priv)) != 0 || 839 (priv->tx_echo & get_next_mask(priv)) == 0) 840 netif_wake_queue(dev); 841} 842 843static void at91_irq_err_state(struct net_device *dev, 844 struct can_frame *cf, enum can_state new_state) 845{ 846 struct at91_priv *priv = netdev_priv(dev); 847 u32 reg_idr = 0, reg_ier = 0; 848 struct can_berr_counter bec; 849 850 at91_get_berr_counter(dev, &bec); 851 852 switch (priv->can.state) { 853 case CAN_STATE_ERROR_ACTIVE: 854 /* 855 * from: ERROR_ACTIVE 856 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 857 * => : there was a warning int 858 */ 859 if (new_state >= CAN_STATE_ERROR_WARNING && 860 new_state <= CAN_STATE_BUS_OFF) { 861 netdev_dbg(dev, "Error Warning IRQ\n"); 862 priv->can.can_stats.error_warning++; 863 864 cf->can_id |= CAN_ERR_CRTL; 865 cf->data[1] = (bec.txerr > bec.rxerr) ? 866 CAN_ERR_CRTL_TX_WARNING : 867 CAN_ERR_CRTL_RX_WARNING; 868 } 869 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 870 /* 871 * from: ERROR_ACTIVE, ERROR_WARNING 872 * to : ERROR_PASSIVE, BUS_OFF 873 * => : error passive int 874 */ 875 if (new_state >= CAN_STATE_ERROR_PASSIVE && 876 new_state <= CAN_STATE_BUS_OFF) { 877 netdev_dbg(dev, "Error Passive IRQ\n"); 878 priv->can.can_stats.error_passive++; 879 880 cf->can_id |= CAN_ERR_CRTL; 881 cf->data[1] = (bec.txerr > bec.rxerr) ? 882 CAN_ERR_CRTL_TX_PASSIVE : 883 CAN_ERR_CRTL_RX_PASSIVE; 884 } 885 break; 886 case CAN_STATE_BUS_OFF: 887 /* 888 * from: BUS_OFF 889 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 890 */ 891 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 892 cf->can_id |= CAN_ERR_RESTARTED; 893 894 netdev_dbg(dev, "restarted\n"); 895 priv->can.can_stats.restarts++; 896 897 netif_carrier_on(dev); 898 netif_wake_queue(dev); 899 } 900 break; 901 default: 902 break; 903 } 904 905 906 /* process state changes depending on the new state */ 907 switch (new_state) { 908 case CAN_STATE_ERROR_ACTIVE: 909 /* 910 * actually we want to enable AT91_IRQ_WARN here, but 911 * it screws up the system under certain 912 * circumstances. so just enable AT91_IRQ_ERRP, thus 913 * the "fallthrough" 914 */ 915 netdev_dbg(dev, "Error Active\n"); 916 cf->can_id |= CAN_ERR_PROT; 917 cf->data[2] = CAN_ERR_PROT_ACTIVE; 918 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 919 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 920 reg_ier = AT91_IRQ_ERRP; 921 break; 922 case CAN_STATE_ERROR_PASSIVE: 923 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 924 reg_ier = AT91_IRQ_BOFF; 925 break; 926 case CAN_STATE_BUS_OFF: 927 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 928 AT91_IRQ_WARN | AT91_IRQ_BOFF; 929 reg_ier = 0; 930 931 cf->can_id |= CAN_ERR_BUSOFF; 932 933 netdev_dbg(dev, "bus-off\n"); 934 netif_carrier_off(dev); 935 priv->can.can_stats.bus_off++; 936 937 /* turn off chip, if restart is disabled */ 938 if (!priv->can.restart_ms) { 939 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 940 return; 941 } 942 break; 943 default: 944 break; 945 } 946 947 at91_write(priv, AT91_IDR, reg_idr); 948 at91_write(priv, AT91_IER, reg_ier); 949} 950 951static void at91_irq_err(struct net_device *dev) 952{ 953 struct at91_priv *priv = netdev_priv(dev); 954 struct sk_buff *skb; 955 struct can_frame *cf; 956 enum can_state new_state; 957 u32 reg_sr; 958 959 reg_sr = at91_read(priv, AT91_SR); 960 961 /* we need to look at the unmasked reg_sr */ 962 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 963 new_state = CAN_STATE_BUS_OFF; 964 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 965 new_state = CAN_STATE_ERROR_PASSIVE; 966 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 967 new_state = CAN_STATE_ERROR_WARNING; 968 else if (likely(reg_sr & AT91_IRQ_ERRA)) 969 new_state = CAN_STATE_ERROR_ACTIVE; 970 else { 971 netdev_err(dev, "BUG! hardware in undefined state\n"); 972 return; 973 } 974 975 /* state hasn't changed */ 976 if (likely(new_state == priv->can.state)) 977 return; 978 979 skb = alloc_can_err_skb(dev, &cf); 980 if (unlikely(!skb)) 981 return; 982 983 at91_irq_err_state(dev, cf, new_state); 984 netif_rx(skb); 985 986 dev->stats.rx_packets++; 987 dev->stats.rx_bytes += cf->can_dlc; 988 989 priv->can.state = new_state; 990} 991 992/* 993 * interrupt handler 994 */ 995static irqreturn_t at91_irq(int irq, void *dev_id) 996{ 997 struct net_device *dev = dev_id; 998 struct at91_priv *priv = netdev_priv(dev); 999 irqreturn_t handled = IRQ_NONE; 1000 u32 reg_sr, reg_imr; 1001 1002 reg_sr = at91_read(priv, AT91_SR); 1003 reg_imr = at91_read(priv, AT91_IMR); 1004 1005 /* Ignore masked interrupts */ 1006 reg_sr &= reg_imr; 1007 if (!reg_sr) 1008 goto exit; 1009 1010 handled = IRQ_HANDLED; 1011 1012 /* Receive or error interrupt? -> napi */ 1013 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1014 /* 1015 * The error bits are clear on read, 1016 * save for later use. 1017 */ 1018 priv->reg_sr = reg_sr; 1019 at91_write(priv, AT91_IDR, 1020 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1021 napi_schedule(&priv->napi); 1022 } 1023 1024 /* Transmission complete interrupt */ 1025 if (reg_sr & get_irq_mb_tx(priv)) 1026 at91_irq_tx(dev, reg_sr); 1027 1028 at91_irq_err(dev); 1029 1030 exit: 1031 return handled; 1032} 1033 1034static int at91_open(struct net_device *dev) 1035{ 1036 struct at91_priv *priv = netdev_priv(dev); 1037 int err; 1038 1039 clk_enable(priv->clk); 1040 1041 /* check or determine and set bittime */ 1042 err = open_candev(dev); 1043 if (err) 1044 goto out; 1045 1046 /* register interrupt handler */ 1047 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1048 dev->name, dev)) { 1049 err = -EAGAIN; 1050 goto out_close; 1051 } 1052 1053 /* start chip and queuing */ 1054 at91_chip_start(dev); 1055 napi_enable(&priv->napi); 1056 netif_start_queue(dev); 1057 1058 return 0; 1059 1060 out_close: 1061 close_candev(dev); 1062 out: 1063 clk_disable(priv->clk); 1064 1065 return err; 1066} 1067 1068/* 1069 * stop CAN bus activity 1070 */ 1071static int at91_close(struct net_device *dev) 1072{ 1073 struct at91_priv *priv = netdev_priv(dev); 1074 1075 netif_stop_queue(dev); 1076 napi_disable(&priv->napi); 1077 at91_chip_stop(dev, CAN_STATE_STOPPED); 1078 1079 free_irq(dev->irq, dev); 1080 clk_disable(priv->clk); 1081 1082 close_candev(dev); 1083 1084 return 0; 1085} 1086 1087static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1088{ 1089 switch (mode) { 1090 case CAN_MODE_START: 1091 at91_chip_start(dev); 1092 netif_wake_queue(dev); 1093 break; 1094 1095 default: 1096 return -EOPNOTSUPP; 1097 } 1098 1099 return 0; 1100} 1101 1102static const struct net_device_ops at91_netdev_ops = { 1103 .ndo_open = at91_open, 1104 .ndo_stop = at91_close, 1105 .ndo_start_xmit = at91_start_xmit, 1106}; 1107 1108static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1109 struct device_attribute *attr, char *buf) 1110{ 1111 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1112 1113 if (priv->mb0_id & CAN_EFF_FLAG) 1114 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1115 else 1116 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1117} 1118 1119static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1120 struct device_attribute *attr, const char *buf, size_t count) 1121{ 1122 struct net_device *ndev = to_net_dev(dev); 1123 struct at91_priv *priv = netdev_priv(ndev); 1124 unsigned long can_id; 1125 ssize_t ret; 1126 int err; 1127 1128 rtnl_lock(); 1129 1130 if (ndev->flags & IFF_UP) { 1131 ret = -EBUSY; 1132 goto out; 1133 } 1134 1135 err = strict_strtoul(buf, 0, &can_id); 1136 if (err) { 1137 ret = err; 1138 goto out; 1139 } 1140 1141 if (can_id & CAN_EFF_FLAG) 1142 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1143 else 1144 can_id &= CAN_SFF_MASK; 1145 1146 priv->mb0_id = can_id; 1147 ret = count; 1148 1149 out: 1150 rtnl_unlock(); 1151 return ret; 1152} 1153 1154static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1155 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1156 1157static struct attribute *at91_sysfs_attrs[] = { 1158 &dev_attr_mb0_id.attr, 1159 NULL, 1160}; 1161 1162static struct attribute_group at91_sysfs_attr_group = { 1163 .attrs = at91_sysfs_attrs, 1164}; 1165 1166static int __devinit at91_can_probe(struct platform_device *pdev) 1167{ 1168 struct net_device *dev; 1169 struct at91_priv *priv; 1170 struct resource *res; 1171 struct clk *clk; 1172 void __iomem *addr; 1173 int err, irq; 1174 1175 clk = clk_get(&pdev->dev, "can_clk"); 1176 if (IS_ERR(clk)) { 1177 dev_err(&pdev->dev, "no clock defined\n"); 1178 err = -ENODEV; 1179 goto exit; 1180 } 1181 1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1183 irq = platform_get_irq(pdev, 0); 1184 if (!res || irq <= 0) { 1185 err = -ENODEV; 1186 goto exit_put; 1187 } 1188 1189 if (!request_mem_region(res->start, 1190 resource_size(res), 1191 pdev->name)) { 1192 err = -EBUSY; 1193 goto exit_put; 1194 } 1195 1196 addr = ioremap_nocache(res->start, resource_size(res)); 1197 if (!addr) { 1198 err = -ENOMEM; 1199 goto exit_release; 1200 } 1201 1202 dev = alloc_candev(sizeof(struct at91_priv), 1 << AT91_MB_TX_SHIFT); 1203 if (!dev) { 1204 err = -ENOMEM; 1205 goto exit_iounmap; 1206 } 1207 1208 dev->netdev_ops = &at91_netdev_ops; 1209 dev->irq = irq; 1210 dev->flags |= IFF_ECHO; 1211 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1212 1213 priv = netdev_priv(dev); 1214 priv->can.clock.freq = clk_get_rate(clk); 1215 priv->can.bittiming_const = &at91_bittiming_const; 1216 priv->can.do_set_mode = at91_set_mode; 1217 priv->can.do_get_berr_counter = at91_get_berr_counter; 1218 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1219 priv->reg_base = addr; 1220 priv->dev = dev; 1221 priv->clk = clk; 1222 priv->pdata = pdev->dev.platform_data; 1223 priv->mb0_id = 0x7ff; 1224 1225 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1226 1227 dev_set_drvdata(&pdev->dev, dev); 1228 SET_NETDEV_DEV(dev, &pdev->dev); 1229 1230 err = register_candev(dev); 1231 if (err) { 1232 dev_err(&pdev->dev, "registering netdev failed\n"); 1233 goto exit_free; 1234 } 1235 1236 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1237 priv->reg_base, dev->irq); 1238 1239 return 0; 1240 1241 exit_free: 1242 free_candev(dev); 1243 exit_iounmap: 1244 iounmap(addr); 1245 exit_release: 1246 release_mem_region(res->start, resource_size(res)); 1247 exit_put: 1248 clk_put(clk); 1249 exit: 1250 return err; 1251} 1252 1253static int __devexit at91_can_remove(struct platform_device *pdev) 1254{ 1255 struct net_device *dev = platform_get_drvdata(pdev); 1256 struct at91_priv *priv = netdev_priv(dev); 1257 struct resource *res; 1258 1259 unregister_netdev(dev); 1260 1261 platform_set_drvdata(pdev, NULL); 1262 1263 iounmap(priv->reg_base); 1264 1265 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1266 release_mem_region(res->start, resource_size(res)); 1267 1268 clk_put(priv->clk); 1269 1270 free_candev(dev); 1271 1272 return 0; 1273} 1274 1275static struct platform_driver at91_can_driver = { 1276 .probe = at91_can_probe, 1277 .remove = __devexit_p(at91_can_remove), 1278 .driver = { 1279 .name = KBUILD_MODNAME, 1280 .owner = THIS_MODULE, 1281 }, 1282}; 1283 1284static int __init at91_can_module_init(void) 1285{ 1286 return platform_driver_register(&at91_can_driver); 1287} 1288 1289static void __exit at91_can_module_exit(void) 1290{ 1291 platform_driver_unregister(&at91_can_driver); 1292} 1293 1294module_init(at91_can_module_init); 1295module_exit(at91_can_module_exit); 1296 1297MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1298MODULE_LICENSE("GPL v2"); 1299MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1300