at91_can.c revision 871d33725545ca2e402b4526f38f89d041ba930f 
1/*
2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
3 *
4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
6 *
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
10 *
11 *
12 * Your platform definition file should specify something like:
13 *
14 * static struct at91_can_data ek_can_data = {
15 *	transceiver_switch = sam9263ek_transceiver_switch,
16 * };
17 *
18 * at91_add_device_can(&ek_can_data);
19 *
20 */
21
22#include <linux/clk.h>
23#include <linux/errno.h>
24#include <linux/if_arp.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
30#include <linux/platform_device.h>
31#include <linux/rtnetlink.h>
32#include <linux/skbuff.h>
33#include <linux/spinlock.h>
34#include <linux/string.h>
35#include <linux/types.h>
36
37#include <linux/can/dev.h>
38#include <linux/can/error.h>
39
40#include <mach/board.h>
41
42#define AT91_MB_MASK(i)		((1 << (i)) - 1)
43
44/* Common registers */
45enum at91_reg {
46	AT91_MR		= 0x000,
47	AT91_IER	= 0x004,
48	AT91_IDR	= 0x008,
49	AT91_IMR	= 0x00C,
50	AT91_SR		= 0x010,
51	AT91_BR		= 0x014,
52	AT91_TIM	= 0x018,
53	AT91_TIMESTP	= 0x01C,
54	AT91_ECR	= 0x020,
55	AT91_TCR	= 0x024,
56	AT91_ACR	= 0x028,
57};
58
59/* Mailbox registers (0 <= i <= 15) */
60#define AT91_MMR(i)		(enum at91_reg)(0x200 + ((i) * 0x20))
61#define AT91_MAM(i)		(enum at91_reg)(0x204 + ((i) * 0x20))
62#define AT91_MID(i)		(enum at91_reg)(0x208 + ((i) * 0x20))
63#define AT91_MFID(i)		(enum at91_reg)(0x20C + ((i) * 0x20))
64#define AT91_MSR(i)		(enum at91_reg)(0x210 + ((i) * 0x20))
65#define AT91_MDL(i)		(enum at91_reg)(0x214 + ((i) * 0x20))
66#define AT91_MDH(i)		(enum at91_reg)(0x218 + ((i) * 0x20))
67#define AT91_MCR(i)		(enum at91_reg)(0x21C + ((i) * 0x20))
68
69/* Register bits */
70#define AT91_MR_CANEN		BIT(0)
71#define AT91_MR_LPM		BIT(1)
72#define AT91_MR_ABM		BIT(2)
73#define AT91_MR_OVL		BIT(3)
74#define AT91_MR_TEOF		BIT(4)
75#define AT91_MR_TTM		BIT(5)
76#define AT91_MR_TIMFRZ		BIT(6)
77#define AT91_MR_DRPT		BIT(7)
78
79#define AT91_SR_RBSY		BIT(29)
80
81#define AT91_MMR_PRIO_SHIFT	(16)
82
83#define AT91_MID_MIDE		BIT(29)
84
85#define AT91_MSR_MRTR		BIT(20)
86#define AT91_MSR_MABT		BIT(22)
87#define AT91_MSR_MRDY		BIT(23)
88#define AT91_MSR_MMI		BIT(24)
89
90#define AT91_MCR_MRTR		BIT(20)
91#define AT91_MCR_MTCR		BIT(23)
92
93/* Mailbox Modes */
94enum at91_mb_mode {
95	AT91_MB_MODE_DISABLED	= 0,
96	AT91_MB_MODE_RX		= 1,
97	AT91_MB_MODE_RX_OVRWR	= 2,
98	AT91_MB_MODE_TX		= 3,
99	AT91_MB_MODE_CONSUMER	= 4,
100	AT91_MB_MODE_PRODUCER	= 5,
101};
102
103/* Interrupt mask bits */
104#define AT91_IRQ_ERRA		(1 << 16)
105#define AT91_IRQ_WARN		(1 << 17)
106#define AT91_IRQ_ERRP		(1 << 18)
107#define AT91_IRQ_BOFF		(1 << 19)
108#define AT91_IRQ_SLEEP		(1 << 20)
109#define AT91_IRQ_WAKEUP		(1 << 21)
110#define AT91_IRQ_TOVF		(1 << 22)
111#define AT91_IRQ_TSTP		(1 << 23)
112#define AT91_IRQ_CERR		(1 << 24)
113#define AT91_IRQ_SERR		(1 << 25)
114#define AT91_IRQ_AERR		(1 << 26)
115#define AT91_IRQ_FERR		(1 << 27)
116#define AT91_IRQ_BERR		(1 << 28)
117
118#define AT91_IRQ_ERR_ALL	(0x1fff0000)
119#define AT91_IRQ_ERR_FRAME	(AT91_IRQ_CERR | AT91_IRQ_SERR | \
120				 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
121#define AT91_IRQ_ERR_LINE	(AT91_IRQ_ERRA | AT91_IRQ_WARN | \
122				 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
123
124#define AT91_IRQ_ALL		(0x1fffffff)
125
126enum at91_devtype {
127	AT91_DEVTYPE_SAM9263,
128	AT91_DEVTYPE_SAM9X5,
129};
130
131struct at91_devtype_data {
132	unsigned int rx_first;
133	unsigned int rx_split;
134	unsigned int rx_last;
135	unsigned int tx_shift;
136	enum at91_devtype type;
137};
138
139struct at91_priv {
140	struct can_priv can;		/* must be the first member! */
141	struct net_device *dev;
142	struct napi_struct napi;
143
144	void __iomem *reg_base;
145
146	u32 reg_sr;
147	unsigned int tx_next;
148	unsigned int tx_echo;
149	unsigned int rx_next;
150	struct at91_devtype_data devtype_data;
151
152	struct clk *clk;
153	struct at91_can_data *pdata;
154
155	canid_t mb0_id;
156};
157
158static const struct at91_devtype_data at91_devtype_data[] __devinitconst = {
159	[AT91_DEVTYPE_SAM9263] = {
160		.rx_first = 1,
161		.rx_split = 8,
162		.rx_last = 11,
163		.tx_shift = 2,
164	},
165	[AT91_DEVTYPE_SAM9X5] = {
166		.rx_first = 0,
167		.rx_split = 4,
168		.rx_last = 5,
169		.tx_shift = 1,
170	},
171};
172
173static struct can_bittiming_const at91_bittiming_const = {
174	.name		= KBUILD_MODNAME,
175	.tseg1_min	= 4,
176	.tseg1_max	= 16,
177	.tseg2_min	= 2,
178	.tseg2_max	= 8,
179	.sjw_max	= 4,
180	.brp_min 	= 2,
181	.brp_max	= 128,
182	.brp_inc	= 1,
183};
184
185#define AT91_IS(_model) \
186static inline int at91_is_sam##_model(const struct at91_priv *priv) \
187{ \
188	return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
189}
190
191AT91_IS(9263);
192AT91_IS(9X5);
193
194static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
195{
196	return priv->devtype_data.rx_first;
197}
198
199static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
200{
201	return priv->devtype_data.rx_last;
202}
203
204static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
205{
206	return priv->devtype_data.rx_split;
207}
208
209static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
210{
211	return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
212}
213
214static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
215{
216	return get_mb_rx_split(priv) - 1;
217}
218
219static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
220{
221	return AT91_MB_MASK(get_mb_rx_split(priv)) &
222		~AT91_MB_MASK(get_mb_rx_first(priv));
223}
224
225static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
226{
227	return priv->devtype_data.tx_shift;
228}
229
230static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
231{
232	return 1 << get_mb_tx_shift(priv);
233}
234
235static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
236{
237	return get_mb_rx_last(priv) + 1;
238}
239
240static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
241{
242	return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
243}
244
245static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
246{
247	return get_mb_tx_shift(priv);
248}
249
250static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
251{
252	return 0xf << get_mb_tx_shift(priv);
253}
254
255static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
256{
257	return AT91_MB_MASK(get_mb_tx_shift(priv));
258}
259
260static inline unsigned int get_next_mask(const struct at91_priv *priv)
261{
262	return get_next_mb_mask(priv) | get_next_prio_mask(priv);
263}
264
265static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
266{
267	return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
268		~AT91_MB_MASK(get_mb_rx_first(priv));
269}
270
271static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
272{
273	return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
274		~AT91_MB_MASK(get_mb_tx_first(priv));
275}
276
277static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
278{
279	return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
280}
281
282static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
283{
284	return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
285}
286
287static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
288{
289	return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
290}
291
292static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
293{
294	return __raw_readl(priv->reg_base + reg);
295}
296
297static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
298		u32 value)
299{
300	__raw_writel(value, priv->reg_base + reg);
301}
302
303static inline void set_mb_mode_prio(const struct at91_priv *priv,
304		unsigned int mb, enum at91_mb_mode mode, int prio)
305{
306	at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
307}
308
309static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
310		enum at91_mb_mode mode)
311{
312	set_mb_mode_prio(priv, mb, mode, 0);
313}
314
315static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
316{
317	u32 reg_mid;
318
319	if (can_id & CAN_EFF_FLAG)
320		reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
321	else
322		reg_mid = (can_id & CAN_SFF_MASK) << 18;
323
324	return reg_mid;
325}
326
327/*
328 * Swtich transceiver on or off
329 */
330static void at91_transceiver_switch(const struct at91_priv *priv, int on)
331{
332	if (priv->pdata && priv->pdata->transceiver_switch)
333		priv->pdata->transceiver_switch(on);
334}
335
336static void at91_setup_mailboxes(struct net_device *dev)
337{
338	struct at91_priv *priv = netdev_priv(dev);
339	unsigned int i;
340	u32 reg_mid;
341
342	/*
343	 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
344	 * mailbox is disabled. The next 11 mailboxes are used as a
345	 * reception FIFO. The last mailbox is configured with
346	 * overwrite option. The overwrite flag indicates a FIFO
347	 * overflow.
348	 */
349	reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
350	for (i = 0; i < get_mb_rx_first(priv); i++) {
351		set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
352		at91_write(priv, AT91_MID(i), reg_mid);
353		at91_write(priv, AT91_MCR(i), 0x0);	/* clear dlc */
354	}
355
356	for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
357		set_mb_mode(priv, i, AT91_MB_MODE_RX);
358	set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
359
360	/* reset acceptance mask and id register */
361	for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
362		at91_write(priv, AT91_MAM(i), 0x0);
363		at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
364	}
365
366	/* The last 4 mailboxes are used for transmitting. */
367	for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
368		set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
369
370	/* Reset tx and rx helper pointers */
371	priv->tx_next = priv->tx_echo = 0;
372	priv->rx_next = get_mb_rx_first(priv);
373}
374
375static int at91_set_bittiming(struct net_device *dev)
376{
377	const struct at91_priv *priv = netdev_priv(dev);
378	const struct can_bittiming *bt = &priv->can.bittiming;
379	u32 reg_br;
380
381	reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
382		((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
383		((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
384		((bt->phase_seg2 - 1) << 0);
385
386	netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
387
388	at91_write(priv, AT91_BR, reg_br);
389
390	return 0;
391}
392
393static int at91_get_berr_counter(const struct net_device *dev,
394		struct can_berr_counter *bec)
395{
396	const struct at91_priv *priv = netdev_priv(dev);
397	u32 reg_ecr = at91_read(priv, AT91_ECR);
398
399	bec->rxerr = reg_ecr & 0xff;
400	bec->txerr = reg_ecr >> 16;
401
402	return 0;
403}
404
405static void at91_chip_start(struct net_device *dev)
406{
407	struct at91_priv *priv = netdev_priv(dev);
408	u32 reg_mr, reg_ier;
409
410	/* disable interrupts */
411	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
412
413	/* disable chip */
414	reg_mr = at91_read(priv, AT91_MR);
415	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
416
417	at91_set_bittiming(dev);
418	at91_setup_mailboxes(dev);
419	at91_transceiver_switch(priv, 1);
420
421	/* enable chip */
422	at91_write(priv, AT91_MR, AT91_MR_CANEN);
423
424	priv->can.state = CAN_STATE_ERROR_ACTIVE;
425
426	/* Enable interrupts */
427	reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
428	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
429	at91_write(priv, AT91_IER, reg_ier);
430}
431
432static void at91_chip_stop(struct net_device *dev, enum can_state state)
433{
434	struct at91_priv *priv = netdev_priv(dev);
435	u32 reg_mr;
436
437	/* disable interrupts */
438	at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
439
440	reg_mr = at91_read(priv, AT91_MR);
441	at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
442
443	at91_transceiver_switch(priv, 0);
444	priv->can.state = state;
445}
446
447/*
448 * theory of operation:
449 *
450 * According to the datasheet priority 0 is the highest priority, 15
451 * is the lowest. If two mailboxes have the same priority level the
452 * message of the mailbox with the lowest number is sent first.
453 *
454 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
455 * the next mailbox with prio 0, and so on, until all mailboxes are
456 * used. Then we start from the beginning with mailbox
457 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
458 * prio 1. When we reach the last mailbox with prio 15, we have to
459 * stop sending, waiting for all messages to be delivered, then start
460 * again with mailbox AT91_MB_TX_FIRST prio 0.
461 *
462 * We use the priv->tx_next as counter for the next transmission
463 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
464 * encode the mailbox number, the upper 4 bits the mailbox priority:
465 *
466 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
467 *                 (mb - get_mb_tx_first(priv));
468 *
469 */
470static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
471{
472	struct at91_priv *priv = netdev_priv(dev);
473	struct net_device_stats *stats = &dev->stats;
474	struct can_frame *cf = (struct can_frame *)skb->data;
475	unsigned int mb, prio;
476	u32 reg_mid, reg_mcr;
477
478	if (can_dropped_invalid_skb(dev, skb))
479		return NETDEV_TX_OK;
480
481	mb = get_tx_next_mb(priv);
482	prio = get_tx_next_prio(priv);
483
484	if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
485		netif_stop_queue(dev);
486
487		netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
488		return NETDEV_TX_BUSY;
489	}
490	reg_mid = at91_can_id_to_reg_mid(cf->can_id);
491	reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
492		(cf->can_dlc << 16) | AT91_MCR_MTCR;
493
494	/* disable MB while writing ID (see datasheet) */
495	set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
496	at91_write(priv, AT91_MID(mb), reg_mid);
497	set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
498
499	at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
500	at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
501
502	/* This triggers transmission */
503	at91_write(priv, AT91_MCR(mb), reg_mcr);
504
505	stats->tx_bytes += cf->can_dlc;
506
507	/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
508	can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv));
509
510	/*
511	 * we have to stop the queue and deliver all messages in case
512	 * of a prio+mb counter wrap around. This is the case if
513	 * tx_next buffer prio and mailbox equals 0.
514	 *
515	 * also stop the queue if next buffer is still in use
516	 * (== not ready)
517	 */
518	priv->tx_next++;
519	if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
520	      AT91_MSR_MRDY) ||
521	    (priv->tx_next & get_next_mask(priv)) == 0)
522		netif_stop_queue(dev);
523
524	/* Enable interrupt for this mailbox */
525	at91_write(priv, AT91_IER, 1 << mb);
526
527	return NETDEV_TX_OK;
528}
529
530/**
531 * at91_activate_rx_low - activate lower rx mailboxes
532 * @priv: a91 context
533 *
534 * Reenables the lower mailboxes for reception of new CAN messages
535 */
536static inline void at91_activate_rx_low(const struct at91_priv *priv)
537{
538	u32 mask = get_mb_rx_low_mask(priv);
539	at91_write(priv, AT91_TCR, mask);
540}
541
542/**
543 * at91_activate_rx_mb - reactive single rx mailbox
544 * @priv: a91 context
545 * @mb: mailbox to reactivate
546 *
547 * Reenables given mailbox for reception of new CAN messages
548 */
549static inline void at91_activate_rx_mb(const struct at91_priv *priv,
550		unsigned int mb)
551{
552	u32 mask = 1 << mb;
553	at91_write(priv, AT91_TCR, mask);
554}
555
556/**
557 * at91_rx_overflow_err - send error frame due to rx overflow
558 * @dev: net device
559 */
560static void at91_rx_overflow_err(struct net_device *dev)
561{
562	struct net_device_stats *stats = &dev->stats;
563	struct sk_buff *skb;
564	struct can_frame *cf;
565
566	netdev_dbg(dev, "RX buffer overflow\n");
567	stats->rx_over_errors++;
568	stats->rx_errors++;
569
570	skb = alloc_can_err_skb(dev, &cf);
571	if (unlikely(!skb))
572		return;
573
574	cf->can_id |= CAN_ERR_CRTL;
575	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
576	netif_receive_skb(skb);
577
578	stats->rx_packets++;
579	stats->rx_bytes += cf->can_dlc;
580}
581
582/**
583 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
584 * @dev: net device
585 * @mb: mailbox number to read from
586 * @cf: can frame where to store message
587 *
588 * Reads a CAN message from the given mailbox and stores data into
589 * given can frame. "mb" and "cf" must be valid.
590 */
591static void at91_read_mb(struct net_device *dev, unsigned int mb,
592		struct can_frame *cf)
593{
594	const struct at91_priv *priv = netdev_priv(dev);
595	u32 reg_msr, reg_mid;
596
597	reg_mid = at91_read(priv, AT91_MID(mb));
598	if (reg_mid & AT91_MID_MIDE)
599		cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
600	else
601		cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
602
603	reg_msr = at91_read(priv, AT91_MSR(mb));
604	cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
605
606	if (reg_msr & AT91_MSR_MRTR)
607		cf->can_id |= CAN_RTR_FLAG;
608	else {
609		*(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
610		*(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
611	}
612
613	/* allow RX of extended frames */
614	at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
615
616	if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
617		at91_rx_overflow_err(dev);
618}
619
620/**
621 * at91_read_msg - read CAN message from mailbox
622 * @dev: net device
623 * @mb: mail box to read from
624 *
625 * Reads a CAN message from given mailbox, and put into linux network
626 * RX queue, does all housekeeping chores (stats, ...)
627 */
628static void at91_read_msg(struct net_device *dev, unsigned int mb)
629{
630	struct net_device_stats *stats = &dev->stats;
631	struct can_frame *cf;
632	struct sk_buff *skb;
633
634	skb = alloc_can_skb(dev, &cf);
635	if (unlikely(!skb)) {
636		stats->rx_dropped++;
637		return;
638	}
639
640	at91_read_mb(dev, mb, cf);
641	netif_receive_skb(skb);
642
643	stats->rx_packets++;
644	stats->rx_bytes += cf->can_dlc;
645}
646
647/**
648 * at91_poll_rx - read multiple CAN messages from mailboxes
649 * @dev: net device
650 * @quota: max number of pkgs we're allowed to receive
651 *
652 * Theory of Operation:
653 *
654 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
655 * on the chip are reserved for RX. We split them into 2 groups. The
656 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
657 *
658 * Like it or not, but the chip always saves a received CAN message
659 * into the first free mailbox it finds (starting with the
660 * lowest). This makes it very difficult to read the messages in the
661 * right order from the chip. This is how we work around that problem:
662 *
663 * The first message goes into mb nr. 1 and issues an interrupt. All
664 * rx ints are disabled in the interrupt handler and a napi poll is
665 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
666 * receive another message).
667 *
668 *    lower mbxs      upper
669 *     ____^______    __^__
670 *    /           \  /     \
671 * +-+-+-+-+-+-+-+-++-+-+-+-+
672 * | |x|x|x|x|x|x|x|| | | | |
673 * +-+-+-+-+-+-+-+-++-+-+-+-+
674 *  0 0 0 0 0 0  0 0 0 0 1 1  \ mail
675 *  0 1 2 3 4 5  6 7 8 9 0 1  / box
676 *  ^
677 *  |
678 *   \
679 *     unused, due to chip bug
680 *
681 * The variable priv->rx_next points to the next mailbox to read a
682 * message from. As long we're in the lower mailboxes we just read the
683 * mailbox but not reenable it.
684 *
685 * With completion of the last of the lower mailboxes, we reenable the
686 * whole first group, but continue to look for filled mailboxes in the
687 * upper mailboxes. Imagine the second group like overflow mailboxes,
688 * which takes CAN messages if the lower goup is full. While in the
689 * upper group we reenable the mailbox right after reading it. Giving
690 * the chip more room to store messages.
691 *
692 * After finishing we look again in the lower group if we've still
693 * quota.
694 *
695 */
696static int at91_poll_rx(struct net_device *dev, int quota)
697{
698	struct at91_priv *priv = netdev_priv(dev);
699	u32 reg_sr = at91_read(priv, AT91_SR);
700	const unsigned long *addr = (unsigned long *)&reg_sr;
701	unsigned int mb;
702	int received = 0;
703
704	if (priv->rx_next > get_mb_rx_low_last(priv) &&
705	    reg_sr & get_mb_rx_low_mask(priv))
706		netdev_info(dev,
707			"order of incoming frames cannot be guaranteed\n");
708
709 again:
710	for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
711	     mb < get_mb_tx_first(priv) && quota > 0;
712	     reg_sr = at91_read(priv, AT91_SR),
713	     mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
714		at91_read_msg(dev, mb);
715
716		/* reactivate mailboxes */
717		if (mb == get_mb_rx_low_last(priv))
718			/* all lower mailboxed, if just finished it */
719			at91_activate_rx_low(priv);
720		else if (mb > get_mb_rx_low_last(priv))
721			/* only the mailbox we read */
722			at91_activate_rx_mb(priv, mb);
723
724		received++;
725		quota--;
726	}
727
728	/* upper group completed, look again in lower */
729	if (priv->rx_next > get_mb_rx_low_last(priv) &&
730	    quota > 0 && mb > get_mb_rx_last(priv)) {
731		priv->rx_next = get_mb_rx_first(priv);
732		goto again;
733	}
734
735	return received;
736}
737
738static void at91_poll_err_frame(struct net_device *dev,
739		struct can_frame *cf, u32 reg_sr)
740{
741	struct at91_priv *priv = netdev_priv(dev);
742
743	/* CRC error */
744	if (reg_sr & AT91_IRQ_CERR) {
745		netdev_dbg(dev, "CERR irq\n");
746		dev->stats.rx_errors++;
747		priv->can.can_stats.bus_error++;
748		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
749	}
750
751	/* Stuffing Error */
752	if (reg_sr & AT91_IRQ_SERR) {
753		netdev_dbg(dev, "SERR irq\n");
754		dev->stats.rx_errors++;
755		priv->can.can_stats.bus_error++;
756		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
757		cf->data[2] |= CAN_ERR_PROT_STUFF;
758	}
759
760	/* Acknowledgement Error */
761	if (reg_sr & AT91_IRQ_AERR) {
762		netdev_dbg(dev, "AERR irq\n");
763		dev->stats.tx_errors++;
764		cf->can_id |= CAN_ERR_ACK;
765	}
766
767	/* Form error */
768	if (reg_sr & AT91_IRQ_FERR) {
769		netdev_dbg(dev, "FERR irq\n");
770		dev->stats.rx_errors++;
771		priv->can.can_stats.bus_error++;
772		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
773		cf->data[2] |= CAN_ERR_PROT_FORM;
774	}
775
776	/* Bit Error */
777	if (reg_sr & AT91_IRQ_BERR) {
778		netdev_dbg(dev, "BERR irq\n");
779		dev->stats.tx_errors++;
780		priv->can.can_stats.bus_error++;
781		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
782		cf->data[2] |= CAN_ERR_PROT_BIT;
783	}
784}
785
786static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
787{
788	struct sk_buff *skb;
789	struct can_frame *cf;
790
791	if (quota == 0)
792		return 0;
793
794	skb = alloc_can_err_skb(dev, &cf);
795	if (unlikely(!skb))
796		return 0;
797
798	at91_poll_err_frame(dev, cf, reg_sr);
799	netif_receive_skb(skb);
800
801	dev->stats.rx_packets++;
802	dev->stats.rx_bytes += cf->can_dlc;
803
804	return 1;
805}
806
807static int at91_poll(struct napi_struct *napi, int quota)
808{
809	struct net_device *dev = napi->dev;
810	const struct at91_priv *priv = netdev_priv(dev);
811	u32 reg_sr = at91_read(priv, AT91_SR);
812	int work_done = 0;
813
814	if (reg_sr & get_irq_mb_rx(priv))
815		work_done += at91_poll_rx(dev, quota - work_done);
816
817	/*
818	 * The error bits are clear on read,
819	 * so use saved value from irq handler.
820	 */
821	reg_sr |= priv->reg_sr;
822	if (reg_sr & AT91_IRQ_ERR_FRAME)
823		work_done += at91_poll_err(dev, quota - work_done, reg_sr);
824
825	if (work_done < quota) {
826		/* enable IRQs for frame errors and all mailboxes >= rx_next */
827		u32 reg_ier = AT91_IRQ_ERR_FRAME;
828		reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
829
830		napi_complete(napi);
831		at91_write(priv, AT91_IER, reg_ier);
832	}
833
834	return work_done;
835}
836
837/*
838 * theory of operation:
839 *
840 * priv->tx_echo holds the number of the oldest can_frame put for
841 * transmission into the hardware, but not yet ACKed by the CAN tx
842 * complete IRQ.
843 *
844 * We iterate from priv->tx_echo to priv->tx_next and check if the
845 * packet has been transmitted, echo it back to the CAN framework. If
846 * we discover a not yet transmitted package, stop looking for more.
847 *
848 */
849static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
850{
851	struct at91_priv *priv = netdev_priv(dev);
852	u32 reg_msr;
853	unsigned int mb;
854
855	/* masking of reg_sr not needed, already done by at91_irq */
856
857	for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
858		mb = get_tx_echo_mb(priv);
859
860		/* no event in mailbox? */
861		if (!(reg_sr & (1 << mb)))
862			break;
863
864		/* Disable irq for this TX mailbox */
865		at91_write(priv, AT91_IDR, 1 << mb);
866
867		/*
868		 * only echo if mailbox signals us a transfer
869		 * complete (MSR_MRDY). Otherwise it's a tansfer
870		 * abort. "can_bus_off()" takes care about the skbs
871		 * parked in the echo queue.
872		 */
873		reg_msr = at91_read(priv, AT91_MSR(mb));
874		if (likely(reg_msr & AT91_MSR_MRDY &&
875			   ~reg_msr & AT91_MSR_MABT)) {
876			/* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
877			can_get_echo_skb(dev, mb - get_mb_tx_first(priv));
878			dev->stats.tx_packets++;
879		}
880	}
881
882	/*
883	 * restart queue if we don't have a wrap around but restart if
884	 * we get a TX int for the last can frame directly before a
885	 * wrap around.
886	 */
887	if ((priv->tx_next & get_next_mask(priv)) != 0 ||
888	    (priv->tx_echo & get_next_mask(priv)) == 0)
889		netif_wake_queue(dev);
890}
891
892static void at91_irq_err_state(struct net_device *dev,
893		struct can_frame *cf, enum can_state new_state)
894{
895	struct at91_priv *priv = netdev_priv(dev);
896	u32 reg_idr = 0, reg_ier = 0;
897	struct can_berr_counter bec;
898
899	at91_get_berr_counter(dev, &bec);
900
901	switch (priv->can.state) {
902	case CAN_STATE_ERROR_ACTIVE:
903		/*
904		 * from: ERROR_ACTIVE
905		 * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
906		 * =>  : there was a warning int
907		 */
908		if (new_state >= CAN_STATE_ERROR_WARNING &&
909		    new_state <= CAN_STATE_BUS_OFF) {
910			netdev_dbg(dev, "Error Warning IRQ\n");
911			priv->can.can_stats.error_warning++;
912
913			cf->can_id |= CAN_ERR_CRTL;
914			cf->data[1] = (bec.txerr > bec.rxerr) ?
915				CAN_ERR_CRTL_TX_WARNING :
916				CAN_ERR_CRTL_RX_WARNING;
917		}
918	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
919		/*
920		 * from: ERROR_ACTIVE, ERROR_WARNING
921		 * to  : ERROR_PASSIVE, BUS_OFF
922		 * =>  : error passive int
923		 */
924		if (new_state >= CAN_STATE_ERROR_PASSIVE &&
925		    new_state <= CAN_STATE_BUS_OFF) {
926			netdev_dbg(dev, "Error Passive IRQ\n");
927			priv->can.can_stats.error_passive++;
928
929			cf->can_id |= CAN_ERR_CRTL;
930			cf->data[1] = (bec.txerr > bec.rxerr) ?
931				CAN_ERR_CRTL_TX_PASSIVE :
932				CAN_ERR_CRTL_RX_PASSIVE;
933		}
934		break;
935	case CAN_STATE_BUS_OFF:
936		/*
937		 * from: BUS_OFF
938		 * to  : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
939		 */
940		if (new_state <= CAN_STATE_ERROR_PASSIVE) {
941			cf->can_id |= CAN_ERR_RESTARTED;
942
943			netdev_dbg(dev, "restarted\n");
944			priv->can.can_stats.restarts++;
945
946			netif_carrier_on(dev);
947			netif_wake_queue(dev);
948		}
949		break;
950	default:
951		break;
952	}
953
954
955	/* process state changes depending on the new state */
956	switch (new_state) {
957	case CAN_STATE_ERROR_ACTIVE:
958		/*
959		 * actually we want to enable AT91_IRQ_WARN here, but
960		 * it screws up the system under certain
961		 * circumstances. so just enable AT91_IRQ_ERRP, thus
962		 * the "fallthrough"
963		 */
964		netdev_dbg(dev, "Error Active\n");
965		cf->can_id |= CAN_ERR_PROT;
966		cf->data[2] = CAN_ERR_PROT_ACTIVE;
967	case CAN_STATE_ERROR_WARNING:	/* fallthrough */
968		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
969		reg_ier = AT91_IRQ_ERRP;
970		break;
971	case CAN_STATE_ERROR_PASSIVE:
972		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
973		reg_ier = AT91_IRQ_BOFF;
974		break;
975	case CAN_STATE_BUS_OFF:
976		reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
977			AT91_IRQ_WARN | AT91_IRQ_BOFF;
978		reg_ier = 0;
979
980		cf->can_id |= CAN_ERR_BUSOFF;
981
982		netdev_dbg(dev, "bus-off\n");
983		netif_carrier_off(dev);
984		priv->can.can_stats.bus_off++;
985
986		/* turn off chip, if restart is disabled */
987		if (!priv->can.restart_ms) {
988			at91_chip_stop(dev, CAN_STATE_BUS_OFF);
989			return;
990		}
991		break;
992	default:
993		break;
994	}
995
996	at91_write(priv, AT91_IDR, reg_idr);
997	at91_write(priv, AT91_IER, reg_ier);
998}
999
1000static int at91_get_state_by_bec(const struct net_device *dev,
1001		enum can_state *state)
1002{
1003	struct can_berr_counter bec;
1004	int err;
1005
1006	err = at91_get_berr_counter(dev, &bec);
1007	if (err)
1008		return err;
1009
1010	if (bec.txerr < 96 && bec.rxerr < 96)
1011		*state = CAN_STATE_ERROR_ACTIVE;
1012	else if (bec.txerr < 128 && bec.rxerr < 128)
1013		*state = CAN_STATE_ERROR_WARNING;
1014	else if (bec.txerr < 256 && bec.rxerr < 256)
1015		*state = CAN_STATE_ERROR_PASSIVE;
1016	else
1017		*state = CAN_STATE_BUS_OFF;
1018
1019	return 0;
1020}
1021
1022
1023static void at91_irq_err(struct net_device *dev)
1024{
1025	struct at91_priv *priv = netdev_priv(dev);
1026	struct sk_buff *skb;
1027	struct can_frame *cf;
1028	enum can_state new_state;
1029	u32 reg_sr;
1030	int err;
1031
1032	if (at91_is_sam9263(priv)) {
1033		reg_sr = at91_read(priv, AT91_SR);
1034
1035		/* we need to look at the unmasked reg_sr */
1036		if (unlikely(reg_sr & AT91_IRQ_BOFF))
1037			new_state = CAN_STATE_BUS_OFF;
1038		else if (unlikely(reg_sr & AT91_IRQ_ERRP))
1039			new_state = CAN_STATE_ERROR_PASSIVE;
1040		else if (unlikely(reg_sr & AT91_IRQ_WARN))
1041			new_state = CAN_STATE_ERROR_WARNING;
1042		else if (likely(reg_sr & AT91_IRQ_ERRA))
1043			new_state = CAN_STATE_ERROR_ACTIVE;
1044		else {
1045			netdev_err(dev, "BUG! hardware in undefined state\n");
1046			return;
1047		}
1048	} else {
1049		err = at91_get_state_by_bec(dev, &new_state);
1050		if (err)
1051			return;
1052	}
1053
1054	/* state hasn't changed */
1055	if (likely(new_state == priv->can.state))
1056		return;
1057
1058	skb = alloc_can_err_skb(dev, &cf);
1059	if (unlikely(!skb))
1060		return;
1061
1062	at91_irq_err_state(dev, cf, new_state);
1063	netif_rx(skb);
1064
1065	dev->stats.rx_packets++;
1066	dev->stats.rx_bytes += cf->can_dlc;
1067
1068	priv->can.state = new_state;
1069}
1070
1071/*
1072 * interrupt handler
1073 */
1074static irqreturn_t at91_irq(int irq, void *dev_id)
1075{
1076	struct net_device *dev = dev_id;
1077	struct at91_priv *priv = netdev_priv(dev);
1078	irqreturn_t handled = IRQ_NONE;
1079	u32 reg_sr, reg_imr;
1080
1081	reg_sr = at91_read(priv, AT91_SR);
1082	reg_imr = at91_read(priv, AT91_IMR);
1083
1084	/* Ignore masked interrupts */
1085	reg_sr &= reg_imr;
1086	if (!reg_sr)
1087		goto exit;
1088
1089	handled = IRQ_HANDLED;
1090
1091	/* Receive or error interrupt? -> napi */
1092	if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1093		/*
1094		 * The error bits are clear on read,
1095		 * save for later use.
1096		 */
1097		priv->reg_sr = reg_sr;
1098		at91_write(priv, AT91_IDR,
1099			   get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1100		napi_schedule(&priv->napi);
1101	}
1102
1103	/* Transmission complete interrupt */
1104	if (reg_sr & get_irq_mb_tx(priv))
1105		at91_irq_tx(dev, reg_sr);
1106
1107	at91_irq_err(dev);
1108
1109 exit:
1110	return handled;
1111}
1112
1113static int at91_open(struct net_device *dev)
1114{
1115	struct at91_priv *priv = netdev_priv(dev);
1116	int err;
1117
1118	clk_enable(priv->clk);
1119
1120	/* check or determine and set bittime */
1121	err = open_candev(dev);
1122	if (err)
1123		goto out;
1124
1125	/* register interrupt handler */
1126	if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1127			dev->name, dev)) {
1128		err = -EAGAIN;
1129		goto out_close;
1130	}
1131
1132	/* start chip and queuing */
1133	at91_chip_start(dev);
1134	napi_enable(&priv->napi);
1135	netif_start_queue(dev);
1136
1137	return 0;
1138
1139 out_close:
1140	close_candev(dev);
1141 out:
1142	clk_disable(priv->clk);
1143
1144	return err;
1145}
1146
1147/*
1148 * stop CAN bus activity
1149 */
1150static int at91_close(struct net_device *dev)
1151{
1152	struct at91_priv *priv = netdev_priv(dev);
1153
1154	netif_stop_queue(dev);
1155	napi_disable(&priv->napi);
1156	at91_chip_stop(dev, CAN_STATE_STOPPED);
1157
1158	free_irq(dev->irq, dev);
1159	clk_disable(priv->clk);
1160
1161	close_candev(dev);
1162
1163	return 0;
1164}
1165
1166static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1167{
1168	switch (mode) {
1169	case CAN_MODE_START:
1170		at91_chip_start(dev);
1171		netif_wake_queue(dev);
1172		break;
1173
1174	default:
1175		return -EOPNOTSUPP;
1176	}
1177
1178	return 0;
1179}
1180
1181static const struct net_device_ops at91_netdev_ops = {
1182	.ndo_open	= at91_open,
1183	.ndo_stop	= at91_close,
1184	.ndo_start_xmit	= at91_start_xmit,
1185};
1186
1187static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
1188		struct device_attribute *attr, char *buf)
1189{
1190	struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1191
1192	if (priv->mb0_id & CAN_EFF_FLAG)
1193		return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
1194	else
1195		return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
1196}
1197
1198static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
1199		struct device_attribute *attr, const char *buf, size_t count)
1200{
1201	struct net_device *ndev = to_net_dev(dev);
1202	struct at91_priv *priv = netdev_priv(ndev);
1203	unsigned long can_id;
1204	ssize_t ret;
1205	int err;
1206
1207	rtnl_lock();
1208
1209	if (ndev->flags & IFF_UP) {
1210		ret = -EBUSY;
1211		goto out;
1212	}
1213
1214	err = strict_strtoul(buf, 0, &can_id);
1215	if (err) {
1216		ret = err;
1217		goto out;
1218	}
1219
1220	if (can_id & CAN_EFF_FLAG)
1221		can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1222	else
1223		can_id &= CAN_SFF_MASK;
1224
1225	priv->mb0_id = can_id;
1226	ret = count;
1227
1228 out:
1229	rtnl_unlock();
1230	return ret;
1231}
1232
1233static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
1234	at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
1235
1236static struct attribute *at91_sysfs_attrs[] = {
1237	&dev_attr_mb0_id.attr,
1238	NULL,
1239};
1240
1241static struct attribute_group at91_sysfs_attr_group = {
1242	.attrs = at91_sysfs_attrs,
1243};
1244
1245static int __devinit at91_can_probe(struct platform_device *pdev)
1246{
1247	const struct at91_devtype_data *devtype_data;
1248	enum at91_devtype devtype;
1249	struct net_device *dev;
1250	struct at91_priv *priv;
1251	struct resource *res;
1252	struct clk *clk;
1253	void __iomem *addr;
1254	int err, irq;
1255
1256	devtype = pdev->id_entry->driver_data;
1257	devtype_data = &at91_devtype_data[devtype];
1258
1259	clk = clk_get(&pdev->dev, "can_clk");
1260	if (IS_ERR(clk)) {
1261		dev_err(&pdev->dev, "no clock defined\n");
1262		err = -ENODEV;
1263		goto exit;
1264	}
1265
1266	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267	irq = platform_get_irq(pdev, 0);
1268	if (!res || irq <= 0) {
1269		err = -ENODEV;
1270		goto exit_put;
1271	}
1272
1273	if (!request_mem_region(res->start,
1274				resource_size(res),
1275				pdev->name)) {
1276		err = -EBUSY;
1277		goto exit_put;
1278	}
1279
1280	addr = ioremap_nocache(res->start, resource_size(res));
1281	if (!addr) {
1282		err = -ENOMEM;
1283		goto exit_release;
1284	}
1285
1286	dev = alloc_candev(sizeof(struct at91_priv),
1287			   1 << devtype_data->tx_shift);
1288	if (!dev) {
1289		err = -ENOMEM;
1290		goto exit_iounmap;
1291	}
1292
1293	dev->netdev_ops	= &at91_netdev_ops;
1294	dev->irq = irq;
1295	dev->flags |= IFF_ECHO;
1296
1297	priv = netdev_priv(dev);
1298	priv->can.clock.freq = clk_get_rate(clk);
1299	priv->can.bittiming_const = &at91_bittiming_const;
1300	priv->can.do_set_mode = at91_set_mode;
1301	priv->can.do_get_berr_counter = at91_get_berr_counter;
1302	priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
1303	priv->dev = dev;
1304	priv->reg_base = addr;
1305	priv->devtype_data = *devtype_data;
1306	priv->devtype_data.type = devtype;
1307	priv->clk = clk;
1308	priv->pdata = pdev->dev.platform_data;
1309	priv->mb0_id = 0x7ff;
1310
1311	netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1312
1313	if (at91_is_sam9263(priv))
1314		dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1315
1316	dev_set_drvdata(&pdev->dev, dev);
1317	SET_NETDEV_DEV(dev, &pdev->dev);
1318
1319	err = register_candev(dev);
1320	if (err) {
1321		dev_err(&pdev->dev, "registering netdev failed\n");
1322		goto exit_free;
1323	}
1324
1325	dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1326		 priv->reg_base, dev->irq);
1327
1328	return 0;
1329
1330 exit_free:
1331	free_candev(dev);
1332 exit_iounmap:
1333	iounmap(addr);
1334 exit_release:
1335	release_mem_region(res->start, resource_size(res));
1336 exit_put:
1337	clk_put(clk);
1338 exit:
1339	return err;
1340}
1341
1342static int __devexit at91_can_remove(struct platform_device *pdev)
1343{
1344	struct net_device *dev = platform_get_drvdata(pdev);
1345	struct at91_priv *priv = netdev_priv(dev);
1346	struct resource *res;
1347
1348	unregister_netdev(dev);
1349
1350	platform_set_drvdata(pdev, NULL);
1351
1352	iounmap(priv->reg_base);
1353
1354	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1355	release_mem_region(res->start, resource_size(res));
1356
1357	clk_put(priv->clk);
1358
1359	free_candev(dev);
1360
1361	return 0;
1362}
1363
1364static const struct platform_device_id at91_can_id_table[] = {
1365	{
1366		.name = "at91_can",
1367		.driver_data = AT91_DEVTYPE_SAM9263,
1368	}, {
1369		.name = "at91sam9x5_can",
1370		.driver_data = AT91_DEVTYPE_SAM9X5,
1371	}, {
1372		/* sentinel */
1373	}
1374};
1375
1376static struct platform_driver at91_can_driver = {
1377	.probe = at91_can_probe,
1378	.remove = __devexit_p(at91_can_remove),
1379	.driver = {
1380		.name = KBUILD_MODNAME,
1381		.owner = THIS_MODULE,
1382	},
1383	.id_table = at91_can_id_table,
1384};
1385
1386module_platform_driver(at91_can_driver);
1387
1388MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1389MODULE_LICENSE("GPL v2");
1390MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");
1391