at91_can.c revision 9e0a2d1ca3de6e284e99ad5cae1ae33ecb74c479
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define AT91_NAPI_WEIGHT 11 44 45/* 46 * RX/TX Mailbox split 47 * don't dare to touch 48 */ 49#define AT91_MB_RX_NUM 11 50#define AT91_MB_TX_SHIFT 2 51 52#define AT91_MB_RX_FIRST 1 53#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 54 55#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 56#define AT91_MB_RX_SPLIT 8 57#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 58#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \ 59 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 131 - (1 << AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 133 - (1 << AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172}; 173 174static struct can_bittiming_const at91_bittiming_const = { 175 .name = KBUILD_MODNAME, 176 .tseg1_min = 4, 177 .tseg1_max = 16, 178 .tseg2_min = 2, 179 .tseg2_max = 8, 180 .sjw_max = 4, 181 .brp_min = 2, 182 .brp_max = 128, 183 .brp_inc = 1, 184}; 185 186static inline int get_tx_next_mb(const struct at91_priv *priv) 187{ 188 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 189} 190 191static inline int get_tx_next_prio(const struct at91_priv *priv) 192{ 193 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 194} 195 196static inline int get_tx_echo_mb(const struct at91_priv *priv) 197{ 198 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 199} 200 201static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 202{ 203 return __raw_readl(priv->reg_base + reg); 204} 205 206static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 207 u32 value) 208{ 209 __raw_writel(value, priv->reg_base + reg); 210} 211 212static inline void set_mb_mode_prio(const struct at91_priv *priv, 213 unsigned int mb, enum at91_mb_mode mode, int prio) 214{ 215 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 216} 217 218static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 219 enum at91_mb_mode mode) 220{ 221 set_mb_mode_prio(priv, mb, mode, 0); 222} 223 224/* 225 * Swtich transceiver on or off 226 */ 227static void at91_transceiver_switch(const struct at91_priv *priv, int on) 228{ 229 if (priv->pdata && priv->pdata->transceiver_switch) 230 priv->pdata->transceiver_switch(on); 231} 232 233static void at91_setup_mailboxes(struct net_device *dev) 234{ 235 struct at91_priv *priv = netdev_priv(dev); 236 unsigned int i; 237 238 /* 239 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 240 * mailbox is disabled. The next 11 mailboxes are used as a 241 * reception FIFO. The last mailbox is configured with 242 * overwrite option. The overwrite flag indicates a FIFO 243 * overflow. 244 */ 245 for (i = 0; i < AT91_MB_RX_FIRST; i++) 246 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 247 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 248 set_mb_mode(priv, i, AT91_MB_MODE_RX); 249 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 250 251 /* reset acceptance mask and id register */ 252 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 253 at91_write(priv, AT91_MAM(i), 0x0 ); 254 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 255 } 256 257 /* The last 4 mailboxes are used for transmitting. */ 258 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 259 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 260 261 /* Reset tx and rx helper pointers */ 262 priv->tx_next = priv->tx_echo = 0; 263 priv->rx_next = AT91_MB_RX_FIRST; 264} 265 266static int at91_set_bittiming(struct net_device *dev) 267{ 268 const struct at91_priv *priv = netdev_priv(dev); 269 const struct can_bittiming *bt = &priv->can.bittiming; 270 u32 reg_br; 271 272 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 273 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 274 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 275 ((bt->phase_seg2 - 1) << 0); 276 277 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 278 279 at91_write(priv, AT91_BR, reg_br); 280 281 return 0; 282} 283 284static int at91_get_berr_counter(const struct net_device *dev, 285 struct can_berr_counter *bec) 286{ 287 const struct at91_priv *priv = netdev_priv(dev); 288 u32 reg_ecr = at91_read(priv, AT91_ECR); 289 290 bec->rxerr = reg_ecr & 0xff; 291 bec->txerr = reg_ecr >> 16; 292 293 return 0; 294} 295 296static void at91_chip_start(struct net_device *dev) 297{ 298 struct at91_priv *priv = netdev_priv(dev); 299 u32 reg_mr, reg_ier; 300 301 /* disable interrupts */ 302 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 303 304 /* disable chip */ 305 reg_mr = at91_read(priv, AT91_MR); 306 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 307 308 at91_set_bittiming(dev); 309 at91_setup_mailboxes(dev); 310 at91_transceiver_switch(priv, 1); 311 312 /* enable chip */ 313 at91_write(priv, AT91_MR, AT91_MR_CANEN); 314 315 priv->can.state = CAN_STATE_ERROR_ACTIVE; 316 317 /* Enable interrupts */ 318 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 319 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 320 at91_write(priv, AT91_IER, reg_ier); 321} 322 323static void at91_chip_stop(struct net_device *dev, enum can_state state) 324{ 325 struct at91_priv *priv = netdev_priv(dev); 326 u32 reg_mr; 327 328 /* disable interrupts */ 329 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 330 331 reg_mr = at91_read(priv, AT91_MR); 332 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 333 334 at91_transceiver_switch(priv, 0); 335 priv->can.state = state; 336} 337 338/* 339 * theory of operation: 340 * 341 * According to the datasheet priority 0 is the highest priority, 15 342 * is the lowest. If two mailboxes have the same priority level the 343 * message of the mailbox with the lowest number is sent first. 344 * 345 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 346 * the next mailbox with prio 0, and so on, until all mailboxes are 347 * used. Then we start from the beginning with mailbox 348 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 349 * prio 1. When we reach the last mailbox with prio 15, we have to 350 * stop sending, waiting for all messages to be delivered, then start 351 * again with mailbox AT91_MB_TX_FIRST prio 0. 352 * 353 * We use the priv->tx_next as counter for the next transmission 354 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 355 * encode the mailbox number, the upper 4 bits the mailbox priority: 356 * 357 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 358 * (mb - AT91_MB_TX_FIRST); 359 * 360 */ 361static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 362{ 363 struct at91_priv *priv = netdev_priv(dev); 364 struct net_device_stats *stats = &dev->stats; 365 struct can_frame *cf = (struct can_frame *)skb->data; 366 unsigned int mb, prio; 367 u32 reg_mid, reg_mcr; 368 369 if (can_dropped_invalid_skb(dev, skb)) 370 return NETDEV_TX_OK; 371 372 mb = get_tx_next_mb(priv); 373 prio = get_tx_next_prio(priv); 374 375 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 376 netif_stop_queue(dev); 377 378 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 379 return NETDEV_TX_BUSY; 380 } 381 382 if (cf->can_id & CAN_EFF_FLAG) 383 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 384 else 385 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 386 387 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 388 (cf->can_dlc << 16) | AT91_MCR_MTCR; 389 390 /* disable MB while writing ID (see datasheet) */ 391 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 392 at91_write(priv, AT91_MID(mb), reg_mid); 393 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 394 395 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 396 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 397 398 /* This triggers transmission */ 399 at91_write(priv, AT91_MCR(mb), reg_mcr); 400 401 stats->tx_bytes += cf->can_dlc; 402 403 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 404 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 405 406 /* 407 * we have to stop the queue and deliver all messages in case 408 * of a prio+mb counter wrap around. This is the case if 409 * tx_next buffer prio and mailbox equals 0. 410 * 411 * also stop the queue if next buffer is still in use 412 * (== not ready) 413 */ 414 priv->tx_next++; 415 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 416 AT91_MSR_MRDY) || 417 (priv->tx_next & AT91_NEXT_MASK) == 0) 418 netif_stop_queue(dev); 419 420 /* Enable interrupt for this mailbox */ 421 at91_write(priv, AT91_IER, 1 << mb); 422 423 return NETDEV_TX_OK; 424} 425 426/** 427 * at91_activate_rx_low - activate lower rx mailboxes 428 * @priv: a91 context 429 * 430 * Reenables the lower mailboxes for reception of new CAN messages 431 */ 432static inline void at91_activate_rx_low(const struct at91_priv *priv) 433{ 434 u32 mask = AT91_MB_RX_LOW_MASK; 435 at91_write(priv, AT91_TCR, mask); 436} 437 438/** 439 * at91_activate_rx_mb - reactive single rx mailbox 440 * @priv: a91 context 441 * @mb: mailbox to reactivate 442 * 443 * Reenables given mailbox for reception of new CAN messages 444 */ 445static inline void at91_activate_rx_mb(const struct at91_priv *priv, 446 unsigned int mb) 447{ 448 u32 mask = 1 << mb; 449 at91_write(priv, AT91_TCR, mask); 450} 451 452/** 453 * at91_rx_overflow_err - send error frame due to rx overflow 454 * @dev: net device 455 */ 456static void at91_rx_overflow_err(struct net_device *dev) 457{ 458 struct net_device_stats *stats = &dev->stats; 459 struct sk_buff *skb; 460 struct can_frame *cf; 461 462 netdev_dbg(dev, "RX buffer overflow\n"); 463 stats->rx_over_errors++; 464 stats->rx_errors++; 465 466 skb = alloc_can_err_skb(dev, &cf); 467 if (unlikely(!skb)) 468 return; 469 470 cf->can_id |= CAN_ERR_CRTL; 471 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 472 netif_receive_skb(skb); 473 474 stats->rx_packets++; 475 stats->rx_bytes += cf->can_dlc; 476} 477 478/** 479 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 480 * @dev: net device 481 * @mb: mailbox number to read from 482 * @cf: can frame where to store message 483 * 484 * Reads a CAN message from the given mailbox and stores data into 485 * given can frame. "mb" and "cf" must be valid. 486 */ 487static void at91_read_mb(struct net_device *dev, unsigned int mb, 488 struct can_frame *cf) 489{ 490 const struct at91_priv *priv = netdev_priv(dev); 491 u32 reg_msr, reg_mid; 492 493 reg_mid = at91_read(priv, AT91_MID(mb)); 494 if (reg_mid & AT91_MID_MIDE) 495 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 496 else 497 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 498 499 reg_msr = at91_read(priv, AT91_MSR(mb)); 500 if (reg_msr & AT91_MSR_MRTR) 501 cf->can_id |= CAN_RTR_FLAG; 502 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 503 504 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 505 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 506 507 /* allow RX of extended frames */ 508 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 509 510 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 511 at91_rx_overflow_err(dev); 512} 513 514/** 515 * at91_read_msg - read CAN message from mailbox 516 * @dev: net device 517 * @mb: mail box to read from 518 * 519 * Reads a CAN message from given mailbox, and put into linux network 520 * RX queue, does all housekeeping chores (stats, ...) 521 */ 522static void at91_read_msg(struct net_device *dev, unsigned int mb) 523{ 524 struct net_device_stats *stats = &dev->stats; 525 struct can_frame *cf; 526 struct sk_buff *skb; 527 528 skb = alloc_can_skb(dev, &cf); 529 if (unlikely(!skb)) { 530 stats->rx_dropped++; 531 return; 532 } 533 534 at91_read_mb(dev, mb, cf); 535 netif_receive_skb(skb); 536 537 stats->rx_packets++; 538 stats->rx_bytes += cf->can_dlc; 539} 540 541/** 542 * at91_poll_rx - read multiple CAN messages from mailboxes 543 * @dev: net device 544 * @quota: max number of pkgs we're allowed to receive 545 * 546 * Theory of Operation: 547 * 548 * 11 of the 16 mailboxes on the chip are reserved for RX. we split 549 * them into 2 groups. The lower group holds 7 and upper 4 mailboxes. 550 * 551 * Like it or not, but the chip always saves a received CAN message 552 * into the first free mailbox it finds (starting with the 553 * lowest). This makes it very difficult to read the messages in the 554 * right order from the chip. This is how we work around that problem: 555 * 556 * The first message goes into mb nr. 1 and issues an interrupt. All 557 * rx ints are disabled in the interrupt handler and a napi poll is 558 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 559 * receive another message). 560 * 561 * lower mbxs upper 562 * ____^______ __^__ 563 * / \ / \ 564 * +-+-+-+-+-+-+-+-++-+-+-+-+ 565 * | |x|x|x|x|x|x|x|| | | | | 566 * +-+-+-+-+-+-+-+-++-+-+-+-+ 567 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 568 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 569 * ^ 570 * | 571 * \ 572 * unused, due to chip bug 573 * 574 * The variable priv->rx_next points to the next mailbox to read a 575 * message from. As long we're in the lower mailboxes we just read the 576 * mailbox but not reenable it. 577 * 578 * With completion of the last of the lower mailboxes, we reenable the 579 * whole first group, but continue to look for filled mailboxes in the 580 * upper mailboxes. Imagine the second group like overflow mailboxes, 581 * which takes CAN messages if the lower goup is full. While in the 582 * upper group we reenable the mailbox right after reading it. Giving 583 * the chip more room to store messages. 584 * 585 * After finishing we look again in the lower group if we've still 586 * quota. 587 * 588 */ 589static int at91_poll_rx(struct net_device *dev, int quota) 590{ 591 struct at91_priv *priv = netdev_priv(dev); 592 u32 reg_sr = at91_read(priv, AT91_SR); 593 const unsigned long *addr = (unsigned long *)®_sr; 594 unsigned int mb; 595 int received = 0; 596 597 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 598 reg_sr & AT91_MB_RX_LOW_MASK) 599 netdev_info(dev, 600 "order of incoming frames cannot be guaranteed\n"); 601 602 again: 603 for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next); 604 mb < AT91_MB_RX_LAST + 1 && quota > 0; 605 reg_sr = at91_read(priv, AT91_SR), 606 mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) { 607 at91_read_msg(dev, mb); 608 609 /* reactivate mailboxes */ 610 if (mb == AT91_MB_RX_LOW_LAST) 611 /* all lower mailboxed, if just finished it */ 612 at91_activate_rx_low(priv); 613 else if (mb > AT91_MB_RX_LOW_LAST) 614 /* only the mailbox we read */ 615 at91_activate_rx_mb(priv, mb); 616 617 received++; 618 quota--; 619 } 620 621 /* upper group completed, look again in lower */ 622 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 623 quota > 0 && mb > AT91_MB_RX_LAST) { 624 priv->rx_next = AT91_MB_RX_FIRST; 625 goto again; 626 } 627 628 return received; 629} 630 631static void at91_poll_err_frame(struct net_device *dev, 632 struct can_frame *cf, u32 reg_sr) 633{ 634 struct at91_priv *priv = netdev_priv(dev); 635 636 /* CRC error */ 637 if (reg_sr & AT91_IRQ_CERR) { 638 netdev_dbg(dev, "CERR irq\n"); 639 dev->stats.rx_errors++; 640 priv->can.can_stats.bus_error++; 641 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 642 } 643 644 /* Stuffing Error */ 645 if (reg_sr & AT91_IRQ_SERR) { 646 netdev_dbg(dev, "SERR irq\n"); 647 dev->stats.rx_errors++; 648 priv->can.can_stats.bus_error++; 649 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 650 cf->data[2] |= CAN_ERR_PROT_STUFF; 651 } 652 653 /* Acknowledgement Error */ 654 if (reg_sr & AT91_IRQ_AERR) { 655 netdev_dbg(dev, "AERR irq\n"); 656 dev->stats.tx_errors++; 657 cf->can_id |= CAN_ERR_ACK; 658 } 659 660 /* Form error */ 661 if (reg_sr & AT91_IRQ_FERR) { 662 netdev_dbg(dev, "FERR irq\n"); 663 dev->stats.rx_errors++; 664 priv->can.can_stats.bus_error++; 665 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 666 cf->data[2] |= CAN_ERR_PROT_FORM; 667 } 668 669 /* Bit Error */ 670 if (reg_sr & AT91_IRQ_BERR) { 671 netdev_dbg(dev, "BERR irq\n"); 672 dev->stats.tx_errors++; 673 priv->can.can_stats.bus_error++; 674 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 675 cf->data[2] |= CAN_ERR_PROT_BIT; 676 } 677} 678 679static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 680{ 681 struct sk_buff *skb; 682 struct can_frame *cf; 683 684 if (quota == 0) 685 return 0; 686 687 skb = alloc_can_err_skb(dev, &cf); 688 if (unlikely(!skb)) 689 return 0; 690 691 at91_poll_err_frame(dev, cf, reg_sr); 692 netif_receive_skb(skb); 693 694 dev->stats.rx_packets++; 695 dev->stats.rx_bytes += cf->can_dlc; 696 697 return 1; 698} 699 700static int at91_poll(struct napi_struct *napi, int quota) 701{ 702 struct net_device *dev = napi->dev; 703 const struct at91_priv *priv = netdev_priv(dev); 704 u32 reg_sr = at91_read(priv, AT91_SR); 705 int work_done = 0; 706 707 if (reg_sr & AT91_IRQ_MB_RX) 708 work_done += at91_poll_rx(dev, quota - work_done); 709 710 /* 711 * The error bits are clear on read, 712 * so use saved value from irq handler. 713 */ 714 reg_sr |= priv->reg_sr; 715 if (reg_sr & AT91_IRQ_ERR_FRAME) 716 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 717 718 if (work_done < quota) { 719 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 720 u32 reg_ier = AT91_IRQ_ERR_FRAME; 721 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 722 723 napi_complete(napi); 724 at91_write(priv, AT91_IER, reg_ier); 725 } 726 727 return work_done; 728} 729 730/* 731 * theory of operation: 732 * 733 * priv->tx_echo holds the number of the oldest can_frame put for 734 * transmission into the hardware, but not yet ACKed by the CAN tx 735 * complete IRQ. 736 * 737 * We iterate from priv->tx_echo to priv->tx_next and check if the 738 * packet has been transmitted, echo it back to the CAN framework. If 739 * we discover a not yet transmitted package, stop looking for more. 740 * 741 */ 742static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 743{ 744 struct at91_priv *priv = netdev_priv(dev); 745 u32 reg_msr; 746 unsigned int mb; 747 748 /* masking of reg_sr not needed, already done by at91_irq */ 749 750 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 751 mb = get_tx_echo_mb(priv); 752 753 /* no event in mailbox? */ 754 if (!(reg_sr & (1 << mb))) 755 break; 756 757 /* Disable irq for this TX mailbox */ 758 at91_write(priv, AT91_IDR, 1 << mb); 759 760 /* 761 * only echo if mailbox signals us a transfer 762 * complete (MSR_MRDY). Otherwise it's a tansfer 763 * abort. "can_bus_off()" takes care about the skbs 764 * parked in the echo queue. 765 */ 766 reg_msr = at91_read(priv, AT91_MSR(mb)); 767 if (likely(reg_msr & AT91_MSR_MRDY && 768 ~reg_msr & AT91_MSR_MABT)) { 769 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 770 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 771 dev->stats.tx_packets++; 772 } 773 } 774 775 /* 776 * restart queue if we don't have a wrap around but restart if 777 * we get a TX int for the last can frame directly before a 778 * wrap around. 779 */ 780 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 781 (priv->tx_echo & AT91_NEXT_MASK) == 0) 782 netif_wake_queue(dev); 783} 784 785static void at91_irq_err_state(struct net_device *dev, 786 struct can_frame *cf, enum can_state new_state) 787{ 788 struct at91_priv *priv = netdev_priv(dev); 789 u32 reg_idr = 0, reg_ier = 0; 790 struct can_berr_counter bec; 791 792 at91_get_berr_counter(dev, &bec); 793 794 switch (priv->can.state) { 795 case CAN_STATE_ERROR_ACTIVE: 796 /* 797 * from: ERROR_ACTIVE 798 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 799 * => : there was a warning int 800 */ 801 if (new_state >= CAN_STATE_ERROR_WARNING && 802 new_state <= CAN_STATE_BUS_OFF) { 803 netdev_dbg(dev, "Error Warning IRQ\n"); 804 priv->can.can_stats.error_warning++; 805 806 cf->can_id |= CAN_ERR_CRTL; 807 cf->data[1] = (bec.txerr > bec.rxerr) ? 808 CAN_ERR_CRTL_TX_WARNING : 809 CAN_ERR_CRTL_RX_WARNING; 810 } 811 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 812 /* 813 * from: ERROR_ACTIVE, ERROR_WARNING 814 * to : ERROR_PASSIVE, BUS_OFF 815 * => : error passive int 816 */ 817 if (new_state >= CAN_STATE_ERROR_PASSIVE && 818 new_state <= CAN_STATE_BUS_OFF) { 819 netdev_dbg(dev, "Error Passive IRQ\n"); 820 priv->can.can_stats.error_passive++; 821 822 cf->can_id |= CAN_ERR_CRTL; 823 cf->data[1] = (bec.txerr > bec.rxerr) ? 824 CAN_ERR_CRTL_TX_PASSIVE : 825 CAN_ERR_CRTL_RX_PASSIVE; 826 } 827 break; 828 case CAN_STATE_BUS_OFF: 829 /* 830 * from: BUS_OFF 831 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 832 */ 833 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 834 cf->can_id |= CAN_ERR_RESTARTED; 835 836 netdev_dbg(dev, "restarted\n"); 837 priv->can.can_stats.restarts++; 838 839 netif_carrier_on(dev); 840 netif_wake_queue(dev); 841 } 842 break; 843 default: 844 break; 845 } 846 847 848 /* process state changes depending on the new state */ 849 switch (new_state) { 850 case CAN_STATE_ERROR_ACTIVE: 851 /* 852 * actually we want to enable AT91_IRQ_WARN here, but 853 * it screws up the system under certain 854 * circumstances. so just enable AT91_IRQ_ERRP, thus 855 * the "fallthrough" 856 */ 857 netdev_dbg(dev, "Error Active\n"); 858 cf->can_id |= CAN_ERR_PROT; 859 cf->data[2] = CAN_ERR_PROT_ACTIVE; 860 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 861 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 862 reg_ier = AT91_IRQ_ERRP; 863 break; 864 case CAN_STATE_ERROR_PASSIVE: 865 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 866 reg_ier = AT91_IRQ_BOFF; 867 break; 868 case CAN_STATE_BUS_OFF: 869 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 870 AT91_IRQ_WARN | AT91_IRQ_BOFF; 871 reg_ier = 0; 872 873 cf->can_id |= CAN_ERR_BUSOFF; 874 875 netdev_dbg(dev, "bus-off\n"); 876 netif_carrier_off(dev); 877 priv->can.can_stats.bus_off++; 878 879 /* turn off chip, if restart is disabled */ 880 if (!priv->can.restart_ms) { 881 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 882 return; 883 } 884 break; 885 default: 886 break; 887 } 888 889 at91_write(priv, AT91_IDR, reg_idr); 890 at91_write(priv, AT91_IER, reg_ier); 891} 892 893static void at91_irq_err(struct net_device *dev) 894{ 895 struct at91_priv *priv = netdev_priv(dev); 896 struct sk_buff *skb; 897 struct can_frame *cf; 898 enum can_state new_state; 899 u32 reg_sr; 900 901 reg_sr = at91_read(priv, AT91_SR); 902 903 /* we need to look at the unmasked reg_sr */ 904 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 905 new_state = CAN_STATE_BUS_OFF; 906 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 907 new_state = CAN_STATE_ERROR_PASSIVE; 908 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 909 new_state = CAN_STATE_ERROR_WARNING; 910 else if (likely(reg_sr & AT91_IRQ_ERRA)) 911 new_state = CAN_STATE_ERROR_ACTIVE; 912 else { 913 netdev_err(dev, "BUG! hardware in undefined state\n"); 914 return; 915 } 916 917 /* state hasn't changed */ 918 if (likely(new_state == priv->can.state)) 919 return; 920 921 skb = alloc_can_err_skb(dev, &cf); 922 if (unlikely(!skb)) 923 return; 924 925 at91_irq_err_state(dev, cf, new_state); 926 netif_rx(skb); 927 928 dev->stats.rx_packets++; 929 dev->stats.rx_bytes += cf->can_dlc; 930 931 priv->can.state = new_state; 932} 933 934/* 935 * interrupt handler 936 */ 937static irqreturn_t at91_irq(int irq, void *dev_id) 938{ 939 struct net_device *dev = dev_id; 940 struct at91_priv *priv = netdev_priv(dev); 941 irqreturn_t handled = IRQ_NONE; 942 u32 reg_sr, reg_imr; 943 944 reg_sr = at91_read(priv, AT91_SR); 945 reg_imr = at91_read(priv, AT91_IMR); 946 947 /* Ignore masked interrupts */ 948 reg_sr &= reg_imr; 949 if (!reg_sr) 950 goto exit; 951 952 handled = IRQ_HANDLED; 953 954 /* Receive or error interrupt? -> napi */ 955 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 956 /* 957 * The error bits are clear on read, 958 * save for later use. 959 */ 960 priv->reg_sr = reg_sr; 961 at91_write(priv, AT91_IDR, 962 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 963 napi_schedule(&priv->napi); 964 } 965 966 /* Transmission complete interrupt */ 967 if (reg_sr & AT91_IRQ_MB_TX) 968 at91_irq_tx(dev, reg_sr); 969 970 at91_irq_err(dev); 971 972 exit: 973 return handled; 974} 975 976static int at91_open(struct net_device *dev) 977{ 978 struct at91_priv *priv = netdev_priv(dev); 979 int err; 980 981 clk_enable(priv->clk); 982 983 /* check or determine and set bittime */ 984 err = open_candev(dev); 985 if (err) 986 goto out; 987 988 /* register interrupt handler */ 989 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 990 dev->name, dev)) { 991 err = -EAGAIN; 992 goto out_close; 993 } 994 995 /* start chip and queuing */ 996 at91_chip_start(dev); 997 napi_enable(&priv->napi); 998 netif_start_queue(dev); 999 1000 return 0; 1001 1002 out_close: 1003 close_candev(dev); 1004 out: 1005 clk_disable(priv->clk); 1006 1007 return err; 1008} 1009 1010/* 1011 * stop CAN bus activity 1012 */ 1013static int at91_close(struct net_device *dev) 1014{ 1015 struct at91_priv *priv = netdev_priv(dev); 1016 1017 netif_stop_queue(dev); 1018 napi_disable(&priv->napi); 1019 at91_chip_stop(dev, CAN_STATE_STOPPED); 1020 1021 free_irq(dev->irq, dev); 1022 clk_disable(priv->clk); 1023 1024 close_candev(dev); 1025 1026 return 0; 1027} 1028 1029static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1030{ 1031 switch (mode) { 1032 case CAN_MODE_START: 1033 at91_chip_start(dev); 1034 netif_wake_queue(dev); 1035 break; 1036 1037 default: 1038 return -EOPNOTSUPP; 1039 } 1040 1041 return 0; 1042} 1043 1044static const struct net_device_ops at91_netdev_ops = { 1045 .ndo_open = at91_open, 1046 .ndo_stop = at91_close, 1047 .ndo_start_xmit = at91_start_xmit, 1048}; 1049 1050static int __devinit at91_can_probe(struct platform_device *pdev) 1051{ 1052 struct net_device *dev; 1053 struct at91_priv *priv; 1054 struct resource *res; 1055 struct clk *clk; 1056 void __iomem *addr; 1057 int err, irq; 1058 1059 clk = clk_get(&pdev->dev, "can_clk"); 1060 if (IS_ERR(clk)) { 1061 dev_err(&pdev->dev, "no clock defined\n"); 1062 err = -ENODEV; 1063 goto exit; 1064 } 1065 1066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1067 irq = platform_get_irq(pdev, 0); 1068 if (!res || irq <= 0) { 1069 err = -ENODEV; 1070 goto exit_put; 1071 } 1072 1073 if (!request_mem_region(res->start, 1074 resource_size(res), 1075 pdev->name)) { 1076 err = -EBUSY; 1077 goto exit_put; 1078 } 1079 1080 addr = ioremap_nocache(res->start, resource_size(res)); 1081 if (!addr) { 1082 err = -ENOMEM; 1083 goto exit_release; 1084 } 1085 1086 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1087 if (!dev) { 1088 err = -ENOMEM; 1089 goto exit_iounmap; 1090 } 1091 1092 dev->netdev_ops = &at91_netdev_ops; 1093 dev->irq = irq; 1094 dev->flags |= IFF_ECHO; 1095 1096 priv = netdev_priv(dev); 1097 priv->can.clock.freq = clk_get_rate(clk); 1098 priv->can.bittiming_const = &at91_bittiming_const; 1099 priv->can.do_set_mode = at91_set_mode; 1100 priv->can.do_get_berr_counter = at91_get_berr_counter; 1101 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1102 priv->reg_base = addr; 1103 priv->dev = dev; 1104 priv->clk = clk; 1105 priv->pdata = pdev->dev.platform_data; 1106 1107 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1108 1109 dev_set_drvdata(&pdev->dev, dev); 1110 SET_NETDEV_DEV(dev, &pdev->dev); 1111 1112 err = register_candev(dev); 1113 if (err) { 1114 dev_err(&pdev->dev, "registering netdev failed\n"); 1115 goto exit_free; 1116 } 1117 1118 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1119 priv->reg_base, dev->irq); 1120 1121 return 0; 1122 1123 exit_free: 1124 free_candev(dev); 1125 exit_iounmap: 1126 iounmap(addr); 1127 exit_release: 1128 release_mem_region(res->start, resource_size(res)); 1129 exit_put: 1130 clk_put(clk); 1131 exit: 1132 return err; 1133} 1134 1135static int __devexit at91_can_remove(struct platform_device *pdev) 1136{ 1137 struct net_device *dev = platform_get_drvdata(pdev); 1138 struct at91_priv *priv = netdev_priv(dev); 1139 struct resource *res; 1140 1141 unregister_netdev(dev); 1142 1143 platform_set_drvdata(pdev, NULL); 1144 1145 iounmap(priv->reg_base); 1146 1147 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1148 release_mem_region(res->start, resource_size(res)); 1149 1150 clk_put(priv->clk); 1151 1152 free_candev(dev); 1153 1154 return 0; 1155} 1156 1157static struct platform_driver at91_can_driver = { 1158 .probe = at91_can_probe, 1159 .remove = __devexit_p(at91_can_remove), 1160 .driver = { 1161 .name = KBUILD_MODNAME, 1162 .owner = THIS_MODULE, 1163 }, 1164}; 1165 1166static int __init at91_can_module_init(void) 1167{ 1168 return platform_driver_register(&at91_can_driver); 1169} 1170 1171static void __exit at91_can_module_exit(void) 1172{ 1173 platform_driver_unregister(&at91_can_driver); 1174} 1175 1176module_init(at91_can_module_init); 1177module_exit(at91_can_module_exit); 1178 1179MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1180MODULE_LICENSE("GPL v2"); 1181MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1182