at91_can.c revision b049994d0f3a19c1706627117a7269ce5bd335ab
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/rtnetlink.h> 34#include <linux/skbuff.h> 35#include <linux/spinlock.h> 36#include <linux/string.h> 37#include <linux/types.h> 38 39#include <linux/can/dev.h> 40#include <linux/can/error.h> 41 42#include <mach/board.h> 43 44#define AT91_NAPI_WEIGHT 11 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_TX_SHIFT 2 51 52#define AT91_MB_RX_FIRST 1 53#define AT91_MB_RX_LAST 11 54 55#define AT91_MB_MASK(i) ((1 << (i)) - 1) 56#define AT91_MB_RX_SPLIT 8 57#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 58#define AT91_MB_RX_LOW_MASK (AT91_MB_MASK(AT91_MB_RX_SPLIT) & \ 59 ~AT91_MB_MASK(AT91_MB_RX_FIRST)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_MASK(AT91_MB_TX_SHIFT)) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX (AT91_MB_MASK(AT91_MB_RX_LAST + 1) & \ 131 ~AT91_MB_MASK(AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX (AT91_MB_MASK(AT91_MB_TX_LAST + 1) & \ 133 ~AT91_MB_MASK(AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172 173 canid_t mb0_id; 174}; 175 176static struct can_bittiming_const at91_bittiming_const = { 177 .name = KBUILD_MODNAME, 178 .tseg1_min = 4, 179 .tseg1_max = 16, 180 .tseg2_min = 2, 181 .tseg2_max = 8, 182 .sjw_max = 4, 183 .brp_min = 2, 184 .brp_max = 128, 185 .brp_inc = 1, 186}; 187 188static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 189{ 190 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 191} 192 193static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 194{ 195 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 196} 197 198static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 199{ 200 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 201} 202 203static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 204{ 205 return __raw_readl(priv->reg_base + reg); 206} 207 208static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 209 u32 value) 210{ 211 __raw_writel(value, priv->reg_base + reg); 212} 213 214static inline void set_mb_mode_prio(const struct at91_priv *priv, 215 unsigned int mb, enum at91_mb_mode mode, int prio) 216{ 217 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 218} 219 220static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 221 enum at91_mb_mode mode) 222{ 223 set_mb_mode_prio(priv, mb, mode, 0); 224} 225 226static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 227{ 228 u32 reg_mid; 229 230 if (can_id & CAN_EFF_FLAG) 231 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 232 else 233 reg_mid = (can_id & CAN_SFF_MASK) << 18; 234 235 return reg_mid; 236} 237 238/* 239 * Swtich transceiver on or off 240 */ 241static void at91_transceiver_switch(const struct at91_priv *priv, int on) 242{ 243 if (priv->pdata && priv->pdata->transceiver_switch) 244 priv->pdata->transceiver_switch(on); 245} 246 247static void at91_setup_mailboxes(struct net_device *dev) 248{ 249 struct at91_priv *priv = netdev_priv(dev); 250 unsigned int i; 251 u32 reg_mid; 252 253 /* 254 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 255 * mailbox is disabled. The next 11 mailboxes are used as a 256 * reception FIFO. The last mailbox is configured with 257 * overwrite option. The overwrite flag indicates a FIFO 258 * overflow. 259 */ 260 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 261 for (i = 0; i < AT91_MB_RX_FIRST; i++) { 262 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 263 at91_write(priv, AT91_MID(i), reg_mid); 264 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 265 } 266 267 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 268 set_mb_mode(priv, i, AT91_MB_MODE_RX); 269 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 270 271 /* reset acceptance mask and id register */ 272 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 273 at91_write(priv, AT91_MAM(i), 0x0); 274 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 275 } 276 277 /* The last 4 mailboxes are used for transmitting. */ 278 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 279 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 280 281 /* Reset tx and rx helper pointers */ 282 priv->tx_next = priv->tx_echo = 0; 283 priv->rx_next = AT91_MB_RX_FIRST; 284} 285 286static int at91_set_bittiming(struct net_device *dev) 287{ 288 const struct at91_priv *priv = netdev_priv(dev); 289 const struct can_bittiming *bt = &priv->can.bittiming; 290 u32 reg_br; 291 292 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 293 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 294 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 295 ((bt->phase_seg2 - 1) << 0); 296 297 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 298 299 at91_write(priv, AT91_BR, reg_br); 300 301 return 0; 302} 303 304static int at91_get_berr_counter(const struct net_device *dev, 305 struct can_berr_counter *bec) 306{ 307 const struct at91_priv *priv = netdev_priv(dev); 308 u32 reg_ecr = at91_read(priv, AT91_ECR); 309 310 bec->rxerr = reg_ecr & 0xff; 311 bec->txerr = reg_ecr >> 16; 312 313 return 0; 314} 315 316static void at91_chip_start(struct net_device *dev) 317{ 318 struct at91_priv *priv = netdev_priv(dev); 319 u32 reg_mr, reg_ier; 320 321 /* disable interrupts */ 322 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 323 324 /* disable chip */ 325 reg_mr = at91_read(priv, AT91_MR); 326 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 327 328 at91_set_bittiming(dev); 329 at91_setup_mailboxes(dev); 330 at91_transceiver_switch(priv, 1); 331 332 /* enable chip */ 333 at91_write(priv, AT91_MR, AT91_MR_CANEN); 334 335 priv->can.state = CAN_STATE_ERROR_ACTIVE; 336 337 /* Enable interrupts */ 338 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 339 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 340 at91_write(priv, AT91_IER, reg_ier); 341} 342 343static void at91_chip_stop(struct net_device *dev, enum can_state state) 344{ 345 struct at91_priv *priv = netdev_priv(dev); 346 u32 reg_mr; 347 348 /* disable interrupts */ 349 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 350 351 reg_mr = at91_read(priv, AT91_MR); 352 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 353 354 at91_transceiver_switch(priv, 0); 355 priv->can.state = state; 356} 357 358/* 359 * theory of operation: 360 * 361 * According to the datasheet priority 0 is the highest priority, 15 362 * is the lowest. If two mailboxes have the same priority level the 363 * message of the mailbox with the lowest number is sent first. 364 * 365 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 366 * the next mailbox with prio 0, and so on, until all mailboxes are 367 * used. Then we start from the beginning with mailbox 368 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 369 * prio 1. When we reach the last mailbox with prio 15, we have to 370 * stop sending, waiting for all messages to be delivered, then start 371 * again with mailbox AT91_MB_TX_FIRST prio 0. 372 * 373 * We use the priv->tx_next as counter for the next transmission 374 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 375 * encode the mailbox number, the upper 4 bits the mailbox priority: 376 * 377 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) | 378 * (mb - AT91_MB_TX_FIRST); 379 * 380 */ 381static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 382{ 383 struct at91_priv *priv = netdev_priv(dev); 384 struct net_device_stats *stats = &dev->stats; 385 struct can_frame *cf = (struct can_frame *)skb->data; 386 unsigned int mb, prio; 387 u32 reg_mid, reg_mcr; 388 389 if (can_dropped_invalid_skb(dev, skb)) 390 return NETDEV_TX_OK; 391 392 mb = get_tx_next_mb(priv); 393 prio = get_tx_next_prio(priv); 394 395 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 396 netif_stop_queue(dev); 397 398 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 399 return NETDEV_TX_BUSY; 400 } 401 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 402 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 403 (cf->can_dlc << 16) | AT91_MCR_MTCR; 404 405 /* disable MB while writing ID (see datasheet) */ 406 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 407 at91_write(priv, AT91_MID(mb), reg_mid); 408 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 409 410 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 411 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 412 413 /* This triggers transmission */ 414 at91_write(priv, AT91_MCR(mb), reg_mcr); 415 416 stats->tx_bytes += cf->can_dlc; 417 418 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 419 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 420 421 /* 422 * we have to stop the queue and deliver all messages in case 423 * of a prio+mb counter wrap around. This is the case if 424 * tx_next buffer prio and mailbox equals 0. 425 * 426 * also stop the queue if next buffer is still in use 427 * (== not ready) 428 */ 429 priv->tx_next++; 430 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 431 AT91_MSR_MRDY) || 432 (priv->tx_next & AT91_NEXT_MASK) == 0) 433 netif_stop_queue(dev); 434 435 /* Enable interrupt for this mailbox */ 436 at91_write(priv, AT91_IER, 1 << mb); 437 438 return NETDEV_TX_OK; 439} 440 441/** 442 * at91_activate_rx_low - activate lower rx mailboxes 443 * @priv: a91 context 444 * 445 * Reenables the lower mailboxes for reception of new CAN messages 446 */ 447static inline void at91_activate_rx_low(const struct at91_priv *priv) 448{ 449 u32 mask = AT91_MB_RX_LOW_MASK; 450 at91_write(priv, AT91_TCR, mask); 451} 452 453/** 454 * at91_activate_rx_mb - reactive single rx mailbox 455 * @priv: a91 context 456 * @mb: mailbox to reactivate 457 * 458 * Reenables given mailbox for reception of new CAN messages 459 */ 460static inline void at91_activate_rx_mb(const struct at91_priv *priv, 461 unsigned int mb) 462{ 463 u32 mask = 1 << mb; 464 at91_write(priv, AT91_TCR, mask); 465} 466 467/** 468 * at91_rx_overflow_err - send error frame due to rx overflow 469 * @dev: net device 470 */ 471static void at91_rx_overflow_err(struct net_device *dev) 472{ 473 struct net_device_stats *stats = &dev->stats; 474 struct sk_buff *skb; 475 struct can_frame *cf; 476 477 netdev_dbg(dev, "RX buffer overflow\n"); 478 stats->rx_over_errors++; 479 stats->rx_errors++; 480 481 skb = alloc_can_err_skb(dev, &cf); 482 if (unlikely(!skb)) 483 return; 484 485 cf->can_id |= CAN_ERR_CRTL; 486 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 487 netif_receive_skb(skb); 488 489 stats->rx_packets++; 490 stats->rx_bytes += cf->can_dlc; 491} 492 493/** 494 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 495 * @dev: net device 496 * @mb: mailbox number to read from 497 * @cf: can frame where to store message 498 * 499 * Reads a CAN message from the given mailbox and stores data into 500 * given can frame. "mb" and "cf" must be valid. 501 */ 502static void at91_read_mb(struct net_device *dev, unsigned int mb, 503 struct can_frame *cf) 504{ 505 const struct at91_priv *priv = netdev_priv(dev); 506 u32 reg_msr, reg_mid; 507 508 reg_mid = at91_read(priv, AT91_MID(mb)); 509 if (reg_mid & AT91_MID_MIDE) 510 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 511 else 512 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 513 514 reg_msr = at91_read(priv, AT91_MSR(mb)); 515 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 516 517 if (reg_msr & AT91_MSR_MRTR) 518 cf->can_id |= CAN_RTR_FLAG; 519 else { 520 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 521 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 522 } 523 524 /* allow RX of extended frames */ 525 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 526 527 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 528 at91_rx_overflow_err(dev); 529} 530 531/** 532 * at91_read_msg - read CAN message from mailbox 533 * @dev: net device 534 * @mb: mail box to read from 535 * 536 * Reads a CAN message from given mailbox, and put into linux network 537 * RX queue, does all housekeeping chores (stats, ...) 538 */ 539static void at91_read_msg(struct net_device *dev, unsigned int mb) 540{ 541 struct net_device_stats *stats = &dev->stats; 542 struct can_frame *cf; 543 struct sk_buff *skb; 544 545 skb = alloc_can_skb(dev, &cf); 546 if (unlikely(!skb)) { 547 stats->rx_dropped++; 548 return; 549 } 550 551 at91_read_mb(dev, mb, cf); 552 netif_receive_skb(skb); 553 554 stats->rx_packets++; 555 stats->rx_bytes += cf->can_dlc; 556} 557 558/** 559 * at91_poll_rx - read multiple CAN messages from mailboxes 560 * @dev: net device 561 * @quota: max number of pkgs we're allowed to receive 562 * 563 * Theory of Operation: 564 * 565 * 11 of the 16 mailboxes on the chip are reserved for RX. we split 566 * them into 2 groups. The lower group holds 7 and upper 4 mailboxes. 567 * 568 * Like it or not, but the chip always saves a received CAN message 569 * into the first free mailbox it finds (starting with the 570 * lowest). This makes it very difficult to read the messages in the 571 * right order from the chip. This is how we work around that problem: 572 * 573 * The first message goes into mb nr. 1 and issues an interrupt. All 574 * rx ints are disabled in the interrupt handler and a napi poll is 575 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 576 * receive another message). 577 * 578 * lower mbxs upper 579 * ____^______ __^__ 580 * / \ / \ 581 * +-+-+-+-+-+-+-+-++-+-+-+-+ 582 * | |x|x|x|x|x|x|x|| | | | | 583 * +-+-+-+-+-+-+-+-++-+-+-+-+ 584 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 585 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 586 * ^ 587 * | 588 * \ 589 * unused, due to chip bug 590 * 591 * The variable priv->rx_next points to the next mailbox to read a 592 * message from. As long we're in the lower mailboxes we just read the 593 * mailbox but not reenable it. 594 * 595 * With completion of the last of the lower mailboxes, we reenable the 596 * whole first group, but continue to look for filled mailboxes in the 597 * upper mailboxes. Imagine the second group like overflow mailboxes, 598 * which takes CAN messages if the lower goup is full. While in the 599 * upper group we reenable the mailbox right after reading it. Giving 600 * the chip more room to store messages. 601 * 602 * After finishing we look again in the lower group if we've still 603 * quota. 604 * 605 */ 606static int at91_poll_rx(struct net_device *dev, int quota) 607{ 608 struct at91_priv *priv = netdev_priv(dev); 609 u32 reg_sr = at91_read(priv, AT91_SR); 610 const unsigned long *addr = (unsigned long *)®_sr; 611 unsigned int mb; 612 int received = 0; 613 614 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 615 reg_sr & AT91_MB_RX_LOW_MASK) 616 netdev_info(dev, 617 "order of incoming frames cannot be guaranteed\n"); 618 619 again: 620 for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next); 621 mb < AT91_MB_RX_LAST + 1 && quota > 0; 622 reg_sr = at91_read(priv, AT91_SR), 623 mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) { 624 at91_read_msg(dev, mb); 625 626 /* reactivate mailboxes */ 627 if (mb == AT91_MB_RX_LOW_LAST) 628 /* all lower mailboxed, if just finished it */ 629 at91_activate_rx_low(priv); 630 else if (mb > AT91_MB_RX_LOW_LAST) 631 /* only the mailbox we read */ 632 at91_activate_rx_mb(priv, mb); 633 634 received++; 635 quota--; 636 } 637 638 /* upper group completed, look again in lower */ 639 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 640 quota > 0 && mb > AT91_MB_RX_LAST) { 641 priv->rx_next = AT91_MB_RX_FIRST; 642 goto again; 643 } 644 645 return received; 646} 647 648static void at91_poll_err_frame(struct net_device *dev, 649 struct can_frame *cf, u32 reg_sr) 650{ 651 struct at91_priv *priv = netdev_priv(dev); 652 653 /* CRC error */ 654 if (reg_sr & AT91_IRQ_CERR) { 655 netdev_dbg(dev, "CERR irq\n"); 656 dev->stats.rx_errors++; 657 priv->can.can_stats.bus_error++; 658 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 659 } 660 661 /* Stuffing Error */ 662 if (reg_sr & AT91_IRQ_SERR) { 663 netdev_dbg(dev, "SERR irq\n"); 664 dev->stats.rx_errors++; 665 priv->can.can_stats.bus_error++; 666 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 667 cf->data[2] |= CAN_ERR_PROT_STUFF; 668 } 669 670 /* Acknowledgement Error */ 671 if (reg_sr & AT91_IRQ_AERR) { 672 netdev_dbg(dev, "AERR irq\n"); 673 dev->stats.tx_errors++; 674 cf->can_id |= CAN_ERR_ACK; 675 } 676 677 /* Form error */ 678 if (reg_sr & AT91_IRQ_FERR) { 679 netdev_dbg(dev, "FERR irq\n"); 680 dev->stats.rx_errors++; 681 priv->can.can_stats.bus_error++; 682 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 683 cf->data[2] |= CAN_ERR_PROT_FORM; 684 } 685 686 /* Bit Error */ 687 if (reg_sr & AT91_IRQ_BERR) { 688 netdev_dbg(dev, "BERR irq\n"); 689 dev->stats.tx_errors++; 690 priv->can.can_stats.bus_error++; 691 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 692 cf->data[2] |= CAN_ERR_PROT_BIT; 693 } 694} 695 696static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 697{ 698 struct sk_buff *skb; 699 struct can_frame *cf; 700 701 if (quota == 0) 702 return 0; 703 704 skb = alloc_can_err_skb(dev, &cf); 705 if (unlikely(!skb)) 706 return 0; 707 708 at91_poll_err_frame(dev, cf, reg_sr); 709 netif_receive_skb(skb); 710 711 dev->stats.rx_packets++; 712 dev->stats.rx_bytes += cf->can_dlc; 713 714 return 1; 715} 716 717static int at91_poll(struct napi_struct *napi, int quota) 718{ 719 struct net_device *dev = napi->dev; 720 const struct at91_priv *priv = netdev_priv(dev); 721 u32 reg_sr = at91_read(priv, AT91_SR); 722 int work_done = 0; 723 724 if (reg_sr & AT91_IRQ_MB_RX) 725 work_done += at91_poll_rx(dev, quota - work_done); 726 727 /* 728 * The error bits are clear on read, 729 * so use saved value from irq handler. 730 */ 731 reg_sr |= priv->reg_sr; 732 if (reg_sr & AT91_IRQ_ERR_FRAME) 733 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 734 735 if (work_done < quota) { 736 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 737 u32 reg_ier = AT91_IRQ_ERR_FRAME; 738 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_MASK(priv->rx_next); 739 740 napi_complete(napi); 741 at91_write(priv, AT91_IER, reg_ier); 742 } 743 744 return work_done; 745} 746 747/* 748 * theory of operation: 749 * 750 * priv->tx_echo holds the number of the oldest can_frame put for 751 * transmission into the hardware, but not yet ACKed by the CAN tx 752 * complete IRQ. 753 * 754 * We iterate from priv->tx_echo to priv->tx_next and check if the 755 * packet has been transmitted, echo it back to the CAN framework. If 756 * we discover a not yet transmitted package, stop looking for more. 757 * 758 */ 759static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 760{ 761 struct at91_priv *priv = netdev_priv(dev); 762 u32 reg_msr; 763 unsigned int mb; 764 765 /* masking of reg_sr not needed, already done by at91_irq */ 766 767 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 768 mb = get_tx_echo_mb(priv); 769 770 /* no event in mailbox? */ 771 if (!(reg_sr & (1 << mb))) 772 break; 773 774 /* Disable irq for this TX mailbox */ 775 at91_write(priv, AT91_IDR, 1 << mb); 776 777 /* 778 * only echo if mailbox signals us a transfer 779 * complete (MSR_MRDY). Otherwise it's a tansfer 780 * abort. "can_bus_off()" takes care about the skbs 781 * parked in the echo queue. 782 */ 783 reg_msr = at91_read(priv, AT91_MSR(mb)); 784 if (likely(reg_msr & AT91_MSR_MRDY && 785 ~reg_msr & AT91_MSR_MABT)) { 786 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 787 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 788 dev->stats.tx_packets++; 789 } 790 } 791 792 /* 793 * restart queue if we don't have a wrap around but restart if 794 * we get a TX int for the last can frame directly before a 795 * wrap around. 796 */ 797 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 798 (priv->tx_echo & AT91_NEXT_MASK) == 0) 799 netif_wake_queue(dev); 800} 801 802static void at91_irq_err_state(struct net_device *dev, 803 struct can_frame *cf, enum can_state new_state) 804{ 805 struct at91_priv *priv = netdev_priv(dev); 806 u32 reg_idr = 0, reg_ier = 0; 807 struct can_berr_counter bec; 808 809 at91_get_berr_counter(dev, &bec); 810 811 switch (priv->can.state) { 812 case CAN_STATE_ERROR_ACTIVE: 813 /* 814 * from: ERROR_ACTIVE 815 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 816 * => : there was a warning int 817 */ 818 if (new_state >= CAN_STATE_ERROR_WARNING && 819 new_state <= CAN_STATE_BUS_OFF) { 820 netdev_dbg(dev, "Error Warning IRQ\n"); 821 priv->can.can_stats.error_warning++; 822 823 cf->can_id |= CAN_ERR_CRTL; 824 cf->data[1] = (bec.txerr > bec.rxerr) ? 825 CAN_ERR_CRTL_TX_WARNING : 826 CAN_ERR_CRTL_RX_WARNING; 827 } 828 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 829 /* 830 * from: ERROR_ACTIVE, ERROR_WARNING 831 * to : ERROR_PASSIVE, BUS_OFF 832 * => : error passive int 833 */ 834 if (new_state >= CAN_STATE_ERROR_PASSIVE && 835 new_state <= CAN_STATE_BUS_OFF) { 836 netdev_dbg(dev, "Error Passive IRQ\n"); 837 priv->can.can_stats.error_passive++; 838 839 cf->can_id |= CAN_ERR_CRTL; 840 cf->data[1] = (bec.txerr > bec.rxerr) ? 841 CAN_ERR_CRTL_TX_PASSIVE : 842 CAN_ERR_CRTL_RX_PASSIVE; 843 } 844 break; 845 case CAN_STATE_BUS_OFF: 846 /* 847 * from: BUS_OFF 848 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 849 */ 850 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 851 cf->can_id |= CAN_ERR_RESTARTED; 852 853 netdev_dbg(dev, "restarted\n"); 854 priv->can.can_stats.restarts++; 855 856 netif_carrier_on(dev); 857 netif_wake_queue(dev); 858 } 859 break; 860 default: 861 break; 862 } 863 864 865 /* process state changes depending on the new state */ 866 switch (new_state) { 867 case CAN_STATE_ERROR_ACTIVE: 868 /* 869 * actually we want to enable AT91_IRQ_WARN here, but 870 * it screws up the system under certain 871 * circumstances. so just enable AT91_IRQ_ERRP, thus 872 * the "fallthrough" 873 */ 874 netdev_dbg(dev, "Error Active\n"); 875 cf->can_id |= CAN_ERR_PROT; 876 cf->data[2] = CAN_ERR_PROT_ACTIVE; 877 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 878 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 879 reg_ier = AT91_IRQ_ERRP; 880 break; 881 case CAN_STATE_ERROR_PASSIVE: 882 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 883 reg_ier = AT91_IRQ_BOFF; 884 break; 885 case CAN_STATE_BUS_OFF: 886 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 887 AT91_IRQ_WARN | AT91_IRQ_BOFF; 888 reg_ier = 0; 889 890 cf->can_id |= CAN_ERR_BUSOFF; 891 892 netdev_dbg(dev, "bus-off\n"); 893 netif_carrier_off(dev); 894 priv->can.can_stats.bus_off++; 895 896 /* turn off chip, if restart is disabled */ 897 if (!priv->can.restart_ms) { 898 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 899 return; 900 } 901 break; 902 default: 903 break; 904 } 905 906 at91_write(priv, AT91_IDR, reg_idr); 907 at91_write(priv, AT91_IER, reg_ier); 908} 909 910static void at91_irq_err(struct net_device *dev) 911{ 912 struct at91_priv *priv = netdev_priv(dev); 913 struct sk_buff *skb; 914 struct can_frame *cf; 915 enum can_state new_state; 916 u32 reg_sr; 917 918 reg_sr = at91_read(priv, AT91_SR); 919 920 /* we need to look at the unmasked reg_sr */ 921 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 922 new_state = CAN_STATE_BUS_OFF; 923 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 924 new_state = CAN_STATE_ERROR_PASSIVE; 925 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 926 new_state = CAN_STATE_ERROR_WARNING; 927 else if (likely(reg_sr & AT91_IRQ_ERRA)) 928 new_state = CAN_STATE_ERROR_ACTIVE; 929 else { 930 netdev_err(dev, "BUG! hardware in undefined state\n"); 931 return; 932 } 933 934 /* state hasn't changed */ 935 if (likely(new_state == priv->can.state)) 936 return; 937 938 skb = alloc_can_err_skb(dev, &cf); 939 if (unlikely(!skb)) 940 return; 941 942 at91_irq_err_state(dev, cf, new_state); 943 netif_rx(skb); 944 945 dev->stats.rx_packets++; 946 dev->stats.rx_bytes += cf->can_dlc; 947 948 priv->can.state = new_state; 949} 950 951/* 952 * interrupt handler 953 */ 954static irqreturn_t at91_irq(int irq, void *dev_id) 955{ 956 struct net_device *dev = dev_id; 957 struct at91_priv *priv = netdev_priv(dev); 958 irqreturn_t handled = IRQ_NONE; 959 u32 reg_sr, reg_imr; 960 961 reg_sr = at91_read(priv, AT91_SR); 962 reg_imr = at91_read(priv, AT91_IMR); 963 964 /* Ignore masked interrupts */ 965 reg_sr &= reg_imr; 966 if (!reg_sr) 967 goto exit; 968 969 handled = IRQ_HANDLED; 970 971 /* Receive or error interrupt? -> napi */ 972 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 973 /* 974 * The error bits are clear on read, 975 * save for later use. 976 */ 977 priv->reg_sr = reg_sr; 978 at91_write(priv, AT91_IDR, 979 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 980 napi_schedule(&priv->napi); 981 } 982 983 /* Transmission complete interrupt */ 984 if (reg_sr & AT91_IRQ_MB_TX) 985 at91_irq_tx(dev, reg_sr); 986 987 at91_irq_err(dev); 988 989 exit: 990 return handled; 991} 992 993static int at91_open(struct net_device *dev) 994{ 995 struct at91_priv *priv = netdev_priv(dev); 996 int err; 997 998 clk_enable(priv->clk); 999 1000 /* check or determine and set bittime */ 1001 err = open_candev(dev); 1002 if (err) 1003 goto out; 1004 1005 /* register interrupt handler */ 1006 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1007 dev->name, dev)) { 1008 err = -EAGAIN; 1009 goto out_close; 1010 } 1011 1012 /* start chip and queuing */ 1013 at91_chip_start(dev); 1014 napi_enable(&priv->napi); 1015 netif_start_queue(dev); 1016 1017 return 0; 1018 1019 out_close: 1020 close_candev(dev); 1021 out: 1022 clk_disable(priv->clk); 1023 1024 return err; 1025} 1026 1027/* 1028 * stop CAN bus activity 1029 */ 1030static int at91_close(struct net_device *dev) 1031{ 1032 struct at91_priv *priv = netdev_priv(dev); 1033 1034 netif_stop_queue(dev); 1035 napi_disable(&priv->napi); 1036 at91_chip_stop(dev, CAN_STATE_STOPPED); 1037 1038 free_irq(dev->irq, dev); 1039 clk_disable(priv->clk); 1040 1041 close_candev(dev); 1042 1043 return 0; 1044} 1045 1046static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1047{ 1048 switch (mode) { 1049 case CAN_MODE_START: 1050 at91_chip_start(dev); 1051 netif_wake_queue(dev); 1052 break; 1053 1054 default: 1055 return -EOPNOTSUPP; 1056 } 1057 1058 return 0; 1059} 1060 1061static const struct net_device_ops at91_netdev_ops = { 1062 .ndo_open = at91_open, 1063 .ndo_stop = at91_close, 1064 .ndo_start_xmit = at91_start_xmit, 1065}; 1066 1067static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1068 struct device_attribute *attr, char *buf) 1069{ 1070 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1071 1072 if (priv->mb0_id & CAN_EFF_FLAG) 1073 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1074 else 1075 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1076} 1077 1078static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1079 struct device_attribute *attr, const char *buf, size_t count) 1080{ 1081 struct net_device *ndev = to_net_dev(dev); 1082 struct at91_priv *priv = netdev_priv(ndev); 1083 unsigned long can_id; 1084 ssize_t ret; 1085 int err; 1086 1087 rtnl_lock(); 1088 1089 if (ndev->flags & IFF_UP) { 1090 ret = -EBUSY; 1091 goto out; 1092 } 1093 1094 err = strict_strtoul(buf, 0, &can_id); 1095 if (err) { 1096 ret = err; 1097 goto out; 1098 } 1099 1100 if (can_id & CAN_EFF_FLAG) 1101 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1102 else 1103 can_id &= CAN_SFF_MASK; 1104 1105 priv->mb0_id = can_id; 1106 ret = count; 1107 1108 out: 1109 rtnl_unlock(); 1110 return ret; 1111} 1112 1113static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1114 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1115 1116static struct attribute *at91_sysfs_attrs[] = { 1117 &dev_attr_mb0_id.attr, 1118 NULL, 1119}; 1120 1121static struct attribute_group at91_sysfs_attr_group = { 1122 .attrs = at91_sysfs_attrs, 1123}; 1124 1125static int __devinit at91_can_probe(struct platform_device *pdev) 1126{ 1127 struct net_device *dev; 1128 struct at91_priv *priv; 1129 struct resource *res; 1130 struct clk *clk; 1131 void __iomem *addr; 1132 int err, irq; 1133 1134 clk = clk_get(&pdev->dev, "can_clk"); 1135 if (IS_ERR(clk)) { 1136 dev_err(&pdev->dev, "no clock defined\n"); 1137 err = -ENODEV; 1138 goto exit; 1139 } 1140 1141 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1142 irq = platform_get_irq(pdev, 0); 1143 if (!res || irq <= 0) { 1144 err = -ENODEV; 1145 goto exit_put; 1146 } 1147 1148 if (!request_mem_region(res->start, 1149 resource_size(res), 1150 pdev->name)) { 1151 err = -EBUSY; 1152 goto exit_put; 1153 } 1154 1155 addr = ioremap_nocache(res->start, resource_size(res)); 1156 if (!addr) { 1157 err = -ENOMEM; 1158 goto exit_release; 1159 } 1160 1161 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1162 if (!dev) { 1163 err = -ENOMEM; 1164 goto exit_iounmap; 1165 } 1166 1167 dev->netdev_ops = &at91_netdev_ops; 1168 dev->irq = irq; 1169 dev->flags |= IFF_ECHO; 1170 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1171 1172 priv = netdev_priv(dev); 1173 priv->can.clock.freq = clk_get_rate(clk); 1174 priv->can.bittiming_const = &at91_bittiming_const; 1175 priv->can.do_set_mode = at91_set_mode; 1176 priv->can.do_get_berr_counter = at91_get_berr_counter; 1177 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1178 priv->reg_base = addr; 1179 priv->dev = dev; 1180 priv->clk = clk; 1181 priv->pdata = pdev->dev.platform_data; 1182 priv->mb0_id = 0x7ff; 1183 1184 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1185 1186 dev_set_drvdata(&pdev->dev, dev); 1187 SET_NETDEV_DEV(dev, &pdev->dev); 1188 1189 err = register_candev(dev); 1190 if (err) { 1191 dev_err(&pdev->dev, "registering netdev failed\n"); 1192 goto exit_free; 1193 } 1194 1195 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1196 priv->reg_base, dev->irq); 1197 1198 return 0; 1199 1200 exit_free: 1201 free_candev(dev); 1202 exit_iounmap: 1203 iounmap(addr); 1204 exit_release: 1205 release_mem_region(res->start, resource_size(res)); 1206 exit_put: 1207 clk_put(clk); 1208 exit: 1209 return err; 1210} 1211 1212static int __devexit at91_can_remove(struct platform_device *pdev) 1213{ 1214 struct net_device *dev = platform_get_drvdata(pdev); 1215 struct at91_priv *priv = netdev_priv(dev); 1216 struct resource *res; 1217 1218 unregister_netdev(dev); 1219 1220 platform_set_drvdata(pdev, NULL); 1221 1222 iounmap(priv->reg_base); 1223 1224 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1225 release_mem_region(res->start, resource_size(res)); 1226 1227 clk_put(priv->clk); 1228 1229 free_candev(dev); 1230 1231 return 0; 1232} 1233 1234static struct platform_driver at91_can_driver = { 1235 .probe = at91_can_probe, 1236 .remove = __devexit_p(at91_can_remove), 1237 .driver = { 1238 .name = KBUILD_MODNAME, 1239 .owner = THIS_MODULE, 1240 }, 1241}; 1242 1243static int __init at91_can_module_init(void) 1244{ 1245 return platform_driver_register(&at91_can_driver); 1246} 1247 1248static void __exit at91_can_module_exit(void) 1249{ 1250 platform_driver_unregister(&at91_can_driver); 1251} 1252 1253module_init(at91_can_module_init); 1254module_exit(at91_can_module_exit); 1255 1256MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1257MODULE_LICENSE("GPL v2"); 1258MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1259