at91_can.c revision b156fd0483c8f18b3cc544d9c400fe454458e16a
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de> 5 * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define DRV_NAME "at91_can" 44#define AT91_NAPI_WEIGHT 12 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_RX_NUM 12 51#define AT91_MB_TX_SHIFT 2 52 53#define AT91_MB_RX_FIRST 0 54#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 55 56#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 57#define AT91_MB_RX_SPLIT 8 58#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 59#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 131 - (1 << AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 133 - (1 << AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172}; 173 174static struct can_bittiming_const at91_bittiming_const = { 175 .tseg1_min = 4, 176 .tseg1_max = 16, 177 .tseg2_min = 2, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 2, 181 .brp_max = 128, 182 .brp_inc = 1, 183}; 184 185static inline int get_tx_next_mb(const struct at91_priv *priv) 186{ 187 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 188} 189 190static inline int get_tx_next_prio(const struct at91_priv *priv) 191{ 192 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 193} 194 195static inline int get_tx_echo_mb(const struct at91_priv *priv) 196{ 197 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 198} 199 200static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 201{ 202 return readl(priv->reg_base + reg); 203} 204 205static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 206 u32 value) 207{ 208 writel(value, priv->reg_base + reg); 209} 210 211static inline void set_mb_mode_prio(const struct at91_priv *priv, 212 unsigned int mb, enum at91_mb_mode mode, int prio) 213{ 214 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 215} 216 217static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 218 enum at91_mb_mode mode) 219{ 220 set_mb_mode_prio(priv, mb, mode, 0); 221} 222 223/* 224 * Swtich transceiver on or off 225 */ 226static void at91_transceiver_switch(const struct at91_priv *priv, int on) 227{ 228 if (priv->pdata && priv->pdata->transceiver_switch) 229 priv->pdata->transceiver_switch(on); 230} 231 232static void at91_setup_mailboxes(struct net_device *dev) 233{ 234 struct at91_priv *priv = netdev_priv(dev); 235 unsigned int i; 236 237 /* 238 * The first 12 mailboxes are used as a reception FIFO. The 239 * last mailbox is configured with overwrite option. The 240 * overwrite flag indicates a FIFO overflow. 241 */ 242 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 243 set_mb_mode(priv, i, AT91_MB_MODE_RX); 244 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 245 246 /* reset acceptance mask and id register */ 247 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 248 at91_write(priv, AT91_MAM(i), 0x0 ); 249 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 250 } 251 252 /* The last 4 mailboxes are used for transmitting. */ 253 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 254 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 255 256 /* Reset tx and rx helper pointers */ 257 priv->tx_next = priv->tx_echo = priv->rx_next = 0; 258} 259 260static int at91_set_bittiming(struct net_device *dev) 261{ 262 const struct at91_priv *priv = netdev_priv(dev); 263 const struct can_bittiming *bt = &priv->can.bittiming; 264 u32 reg_br; 265 266 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 267 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 268 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 269 ((bt->phase_seg2 - 1) << 0); 270 271 dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br); 272 273 at91_write(priv, AT91_BR, reg_br); 274 275 return 0; 276} 277 278static int at91_get_berr_counter(const struct net_device *dev, 279 struct can_berr_counter *bec) 280{ 281 const struct at91_priv *priv = netdev_priv(dev); 282 u32 reg_ecr = at91_read(priv, AT91_ECR); 283 284 bec->rxerr = reg_ecr & 0xff; 285 bec->txerr = reg_ecr >> 16; 286 287 return 0; 288} 289 290static void at91_chip_start(struct net_device *dev) 291{ 292 struct at91_priv *priv = netdev_priv(dev); 293 u32 reg_mr, reg_ier; 294 295 /* disable interrupts */ 296 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 297 298 /* disable chip */ 299 reg_mr = at91_read(priv, AT91_MR); 300 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 301 302 at91_set_bittiming(dev); 303 at91_setup_mailboxes(dev); 304 at91_transceiver_switch(priv, 1); 305 306 /* enable chip */ 307 at91_write(priv, AT91_MR, AT91_MR_CANEN); 308 309 priv->can.state = CAN_STATE_ERROR_ACTIVE; 310 311 /* Enable interrupts */ 312 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 313 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 314 at91_write(priv, AT91_IER, reg_ier); 315} 316 317static void at91_chip_stop(struct net_device *dev, enum can_state state) 318{ 319 struct at91_priv *priv = netdev_priv(dev); 320 u32 reg_mr; 321 322 /* disable interrupts */ 323 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 324 325 reg_mr = at91_read(priv, AT91_MR); 326 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 327 328 at91_transceiver_switch(priv, 0); 329 priv->can.state = state; 330} 331 332/* 333 * theory of operation: 334 * 335 * According to the datasheet priority 0 is the highest priority, 15 336 * is the lowest. If two mailboxes have the same priority level the 337 * message of the mailbox with the lowest number is sent first. 338 * 339 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 340 * the next mailbox with prio 0, and so on, until all mailboxes are 341 * used. Then we start from the beginning with mailbox 342 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 343 * prio 1. When we reach the last mailbox with prio 15, we have to 344 * stop sending, waiting for all messages to be delivered, then start 345 * again with mailbox AT91_MB_TX_FIRST prio 0. 346 * 347 * We use the priv->tx_next as counter for the next transmission 348 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 349 * encode the mailbox number, the upper 4 bits the mailbox priority: 350 * 351 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 352 * (mb - AT91_MB_TX_FIRST); 353 * 354 */ 355static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 356{ 357 struct at91_priv *priv = netdev_priv(dev); 358 struct net_device_stats *stats = &dev->stats; 359 struct can_frame *cf = (struct can_frame *)skb->data; 360 unsigned int mb, prio; 361 u32 reg_mid, reg_mcr; 362 363 if (can_dropped_invalid_skb(dev, skb)) 364 return NETDEV_TX_OK; 365 366 mb = get_tx_next_mb(priv); 367 prio = get_tx_next_prio(priv); 368 369 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 370 netif_stop_queue(dev); 371 372 dev_err(dev->dev.parent, 373 "BUG! TX buffer full when queue awake!\n"); 374 return NETDEV_TX_BUSY; 375 } 376 377 if (cf->can_id & CAN_EFF_FLAG) 378 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 379 else 380 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 381 382 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 383 (cf->can_dlc << 16) | AT91_MCR_MTCR; 384 385 /* disable MB while writing ID (see datasheet) */ 386 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 387 at91_write(priv, AT91_MID(mb), reg_mid); 388 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 389 390 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 391 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 392 393 /* This triggers transmission */ 394 at91_write(priv, AT91_MCR(mb), reg_mcr); 395 396 stats->tx_bytes += cf->can_dlc; 397 398 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 399 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 400 401 /* 402 * we have to stop the queue and deliver all messages in case 403 * of a prio+mb counter wrap around. This is the case if 404 * tx_next buffer prio and mailbox equals 0. 405 * 406 * also stop the queue if next buffer is still in use 407 * (== not ready) 408 */ 409 priv->tx_next++; 410 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 411 AT91_MSR_MRDY) || 412 (priv->tx_next & AT91_NEXT_MASK) == 0) 413 netif_stop_queue(dev); 414 415 /* Enable interrupt for this mailbox */ 416 at91_write(priv, AT91_IER, 1 << mb); 417 418 return NETDEV_TX_OK; 419} 420 421/** 422 * at91_activate_rx_low - activate lower rx mailboxes 423 * @priv: a91 context 424 * 425 * Reenables the lower mailboxes for reception of new CAN messages 426 */ 427static inline void at91_activate_rx_low(const struct at91_priv *priv) 428{ 429 u32 mask = AT91_MB_RX_LOW_MASK; 430 at91_write(priv, AT91_TCR, mask); 431} 432 433/** 434 * at91_activate_rx_mb - reactive single rx mailbox 435 * @priv: a91 context 436 * @mb: mailbox to reactivate 437 * 438 * Reenables given mailbox for reception of new CAN messages 439 */ 440static inline void at91_activate_rx_mb(const struct at91_priv *priv, 441 unsigned int mb) 442{ 443 u32 mask = 1 << mb; 444 at91_write(priv, AT91_TCR, mask); 445} 446 447/** 448 * at91_rx_overflow_err - send error frame due to rx overflow 449 * @dev: net device 450 */ 451static void at91_rx_overflow_err(struct net_device *dev) 452{ 453 struct net_device_stats *stats = &dev->stats; 454 struct sk_buff *skb; 455 struct can_frame *cf; 456 457 dev_dbg(dev->dev.parent, "RX buffer overflow\n"); 458 stats->rx_over_errors++; 459 stats->rx_errors++; 460 461 skb = alloc_can_err_skb(dev, &cf); 462 if (unlikely(!skb)) 463 return; 464 465 cf->can_id |= CAN_ERR_CRTL; 466 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 467 netif_receive_skb(skb); 468 469 stats->rx_packets++; 470 stats->rx_bytes += cf->can_dlc; 471} 472 473/** 474 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 475 * @dev: net device 476 * @mb: mailbox number to read from 477 * @cf: can frame where to store message 478 * 479 * Reads a CAN message from the given mailbox and stores data into 480 * given can frame. "mb" and "cf" must be valid. 481 */ 482static void at91_read_mb(struct net_device *dev, unsigned int mb, 483 struct can_frame *cf) 484{ 485 const struct at91_priv *priv = netdev_priv(dev); 486 u32 reg_msr, reg_mid; 487 488 reg_mid = at91_read(priv, AT91_MID(mb)); 489 if (reg_mid & AT91_MID_MIDE) 490 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 491 else 492 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 493 494 reg_msr = at91_read(priv, AT91_MSR(mb)); 495 if (reg_msr & AT91_MSR_MRTR) 496 cf->can_id |= CAN_RTR_FLAG; 497 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 498 499 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 500 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 501 502 /* allow RX of extended frames */ 503 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 504 505 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 506 at91_rx_overflow_err(dev); 507} 508 509/** 510 * at91_read_msg - read CAN message from mailbox 511 * @dev: net device 512 * @mb: mail box to read from 513 * 514 * Reads a CAN message from given mailbox, and put into linux network 515 * RX queue, does all housekeeping chores (stats, ...) 516 */ 517static void at91_read_msg(struct net_device *dev, unsigned int mb) 518{ 519 struct net_device_stats *stats = &dev->stats; 520 struct can_frame *cf; 521 struct sk_buff *skb; 522 523 skb = alloc_can_skb(dev, &cf); 524 if (unlikely(!skb)) { 525 stats->rx_dropped++; 526 return; 527 } 528 529 at91_read_mb(dev, mb, cf); 530 netif_receive_skb(skb); 531 532 stats->rx_packets++; 533 stats->rx_bytes += cf->can_dlc; 534} 535 536/** 537 * at91_poll_rx - read multiple CAN messages from mailboxes 538 * @dev: net device 539 * @quota: max number of pkgs we're allowed to receive 540 * 541 * Theory of Operation: 542 * 543 * 12 of the 16 mailboxes on the chip are reserved for RX. we split 544 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes. 545 * 546 * Like it or not, but the chip always saves a received CAN message 547 * into the first free mailbox it finds (starting with the 548 * lowest). This makes it very difficult to read the messages in the 549 * right order from the chip. This is how we work around that problem: 550 * 551 * The first message goes into mb nr. 0 and issues an interrupt. All 552 * rx ints are disabled in the interrupt handler and a napi poll is 553 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 554 * receive another message). 555 * 556 * lower mbxs upper 557 * ______^______ __^__ 558 * / \ / \ 559 * +-+-+-+-+-+-+-+-++-+-+-+-+ 560 * |x|x|x|x|x|x|x|x|| | | | | 561 * +-+-+-+-+-+-+-+-++-+-+-+-+ 562 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 563 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 564 * 565 * The variable priv->rx_next points to the next mailbox to read a 566 * message from. As long we're in the lower mailboxes we just read the 567 * mailbox but not reenable it. 568 * 569 * With completion of the last of the lower mailboxes, we reenable the 570 * whole first group, but continue to look for filled mailboxes in the 571 * upper mailboxes. Imagine the second group like overflow mailboxes, 572 * which takes CAN messages if the lower goup is full. While in the 573 * upper group we reenable the mailbox right after reading it. Giving 574 * the chip more room to store messages. 575 * 576 * After finishing we look again in the lower group if we've still 577 * quota. 578 * 579 */ 580static int at91_poll_rx(struct net_device *dev, int quota) 581{ 582 struct at91_priv *priv = netdev_priv(dev); 583 u32 reg_sr = at91_read(priv, AT91_SR); 584 const unsigned long *addr = (unsigned long *)®_sr; 585 unsigned int mb; 586 int received = 0; 587 588 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 589 reg_sr & AT91_MB_RX_LOW_MASK) 590 dev_info(dev->dev.parent, 591 "order of incoming frames cannot be guaranteed\n"); 592 593 again: 594 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next); 595 mb < AT91_MB_RX_NUM && quota > 0; 596 reg_sr = at91_read(priv, AT91_SR), 597 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) { 598 at91_read_msg(dev, mb); 599 600 /* reactivate mailboxes */ 601 if (mb == AT91_MB_RX_LOW_LAST) 602 /* all lower mailboxed, if just finished it */ 603 at91_activate_rx_low(priv); 604 else if (mb > AT91_MB_RX_LOW_LAST) 605 /* only the mailbox we read */ 606 at91_activate_rx_mb(priv, mb); 607 608 received++; 609 quota--; 610 } 611 612 /* upper group completed, look again in lower */ 613 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 614 quota > 0 && mb >= AT91_MB_RX_NUM) { 615 priv->rx_next = 0; 616 goto again; 617 } 618 619 return received; 620} 621 622static void at91_poll_err_frame(struct net_device *dev, 623 struct can_frame *cf, u32 reg_sr) 624{ 625 struct at91_priv *priv = netdev_priv(dev); 626 627 /* CRC error */ 628 if (reg_sr & AT91_IRQ_CERR) { 629 dev_dbg(dev->dev.parent, "CERR irq\n"); 630 dev->stats.rx_errors++; 631 priv->can.can_stats.bus_error++; 632 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 633 } 634 635 /* Stuffing Error */ 636 if (reg_sr & AT91_IRQ_SERR) { 637 dev_dbg(dev->dev.parent, "SERR irq\n"); 638 dev->stats.rx_errors++; 639 priv->can.can_stats.bus_error++; 640 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 641 cf->data[2] |= CAN_ERR_PROT_STUFF; 642 } 643 644 /* Acknowledgement Error */ 645 if (reg_sr & AT91_IRQ_AERR) { 646 dev_dbg(dev->dev.parent, "AERR irq\n"); 647 dev->stats.tx_errors++; 648 cf->can_id |= CAN_ERR_ACK; 649 } 650 651 /* Form error */ 652 if (reg_sr & AT91_IRQ_FERR) { 653 dev_dbg(dev->dev.parent, "FERR irq\n"); 654 dev->stats.rx_errors++; 655 priv->can.can_stats.bus_error++; 656 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 657 cf->data[2] |= CAN_ERR_PROT_FORM; 658 } 659 660 /* Bit Error */ 661 if (reg_sr & AT91_IRQ_BERR) { 662 dev_dbg(dev->dev.parent, "BERR irq\n"); 663 dev->stats.tx_errors++; 664 priv->can.can_stats.bus_error++; 665 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 666 cf->data[2] |= CAN_ERR_PROT_BIT; 667 } 668} 669 670static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 671{ 672 struct sk_buff *skb; 673 struct can_frame *cf; 674 675 if (quota == 0) 676 return 0; 677 678 skb = alloc_can_err_skb(dev, &cf); 679 if (unlikely(!skb)) 680 return 0; 681 682 at91_poll_err_frame(dev, cf, reg_sr); 683 netif_receive_skb(skb); 684 685 dev->stats.rx_packets++; 686 dev->stats.rx_bytes += cf->can_dlc; 687 688 return 1; 689} 690 691static int at91_poll(struct napi_struct *napi, int quota) 692{ 693 struct net_device *dev = napi->dev; 694 const struct at91_priv *priv = netdev_priv(dev); 695 u32 reg_sr = at91_read(priv, AT91_SR); 696 int work_done = 0; 697 698 if (reg_sr & AT91_IRQ_MB_RX) 699 work_done += at91_poll_rx(dev, quota - work_done); 700 701 /* 702 * The error bits are clear on read, 703 * so use saved value from irq handler. 704 */ 705 reg_sr |= priv->reg_sr; 706 if (reg_sr & AT91_IRQ_ERR_FRAME) 707 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 708 709 if (work_done < quota) { 710 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 711 u32 reg_ier = AT91_IRQ_ERR_FRAME; 712 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 713 714 napi_complete(napi); 715 at91_write(priv, AT91_IER, reg_ier); 716 } 717 718 return work_done; 719} 720 721/* 722 * theory of operation: 723 * 724 * priv->tx_echo holds the number of the oldest can_frame put for 725 * transmission into the hardware, but not yet ACKed by the CAN tx 726 * complete IRQ. 727 * 728 * We iterate from priv->tx_echo to priv->tx_next and check if the 729 * packet has been transmitted, echo it back to the CAN framework. If 730 * we discover a not yet transmitted package, stop looking for more. 731 * 732 */ 733static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 734{ 735 struct at91_priv *priv = netdev_priv(dev); 736 u32 reg_msr; 737 unsigned int mb; 738 739 /* masking of reg_sr not needed, already done by at91_irq */ 740 741 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 742 mb = get_tx_echo_mb(priv); 743 744 /* no event in mailbox? */ 745 if (!(reg_sr & (1 << mb))) 746 break; 747 748 /* Disable irq for this TX mailbox */ 749 at91_write(priv, AT91_IDR, 1 << mb); 750 751 /* 752 * only echo if mailbox signals us a transfer 753 * complete (MSR_MRDY). Otherwise it's a tansfer 754 * abort. "can_bus_off()" takes care about the skbs 755 * parked in the echo queue. 756 */ 757 reg_msr = at91_read(priv, AT91_MSR(mb)); 758 if (likely(reg_msr & AT91_MSR_MRDY && 759 ~reg_msr & AT91_MSR_MABT)) { 760 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 761 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 762 dev->stats.tx_packets++; 763 } 764 } 765 766 /* 767 * restart queue if we don't have a wrap around but restart if 768 * we get a TX int for the last can frame directly before a 769 * wrap around. 770 */ 771 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 772 (priv->tx_echo & AT91_NEXT_MASK) == 0) 773 netif_wake_queue(dev); 774} 775 776static void at91_irq_err_state(struct net_device *dev, 777 struct can_frame *cf, enum can_state new_state) 778{ 779 struct at91_priv *priv = netdev_priv(dev); 780 u32 reg_idr = 0, reg_ier = 0; 781 struct can_berr_counter bec; 782 783 at91_get_berr_counter(dev, &bec); 784 785 switch (priv->can.state) { 786 case CAN_STATE_ERROR_ACTIVE: 787 /* 788 * from: ERROR_ACTIVE 789 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 790 * => : there was a warning int 791 */ 792 if (new_state >= CAN_STATE_ERROR_WARNING && 793 new_state <= CAN_STATE_BUS_OFF) { 794 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 795 priv->can.can_stats.error_warning++; 796 797 cf->can_id |= CAN_ERR_CRTL; 798 cf->data[1] = (bec.txerr > bec.rxerr) ? 799 CAN_ERR_CRTL_TX_WARNING : 800 CAN_ERR_CRTL_RX_WARNING; 801 } 802 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 803 /* 804 * from: ERROR_ACTIVE, ERROR_WARNING 805 * to : ERROR_PASSIVE, BUS_OFF 806 * => : error passive int 807 */ 808 if (new_state >= CAN_STATE_ERROR_PASSIVE && 809 new_state <= CAN_STATE_BUS_OFF) { 810 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 811 priv->can.can_stats.error_passive++; 812 813 cf->can_id |= CAN_ERR_CRTL; 814 cf->data[1] = (bec.txerr > bec.rxerr) ? 815 CAN_ERR_CRTL_TX_PASSIVE : 816 CAN_ERR_CRTL_RX_PASSIVE; 817 } 818 break; 819 case CAN_STATE_BUS_OFF: 820 /* 821 * from: BUS_OFF 822 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 823 */ 824 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 825 cf->can_id |= CAN_ERR_RESTARTED; 826 827 dev_dbg(dev->dev.parent, "restarted\n"); 828 priv->can.can_stats.restarts++; 829 830 netif_carrier_on(dev); 831 netif_wake_queue(dev); 832 } 833 break; 834 default: 835 break; 836 } 837 838 839 /* process state changes depending on the new state */ 840 switch (new_state) { 841 case CAN_STATE_ERROR_ACTIVE: 842 /* 843 * actually we want to enable AT91_IRQ_WARN here, but 844 * it screws up the system under certain 845 * circumstances. so just enable AT91_IRQ_ERRP, thus 846 * the "fallthrough" 847 */ 848 dev_dbg(dev->dev.parent, "Error Active\n"); 849 cf->can_id |= CAN_ERR_PROT; 850 cf->data[2] = CAN_ERR_PROT_ACTIVE; 851 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 852 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 853 reg_ier = AT91_IRQ_ERRP; 854 break; 855 case CAN_STATE_ERROR_PASSIVE: 856 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 857 reg_ier = AT91_IRQ_BOFF; 858 break; 859 case CAN_STATE_BUS_OFF: 860 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 861 AT91_IRQ_WARN | AT91_IRQ_BOFF; 862 reg_ier = 0; 863 864 cf->can_id |= CAN_ERR_BUSOFF; 865 866 dev_dbg(dev->dev.parent, "bus-off\n"); 867 netif_carrier_off(dev); 868 priv->can.can_stats.bus_off++; 869 870 /* turn off chip, if restart is disabled */ 871 if (!priv->can.restart_ms) { 872 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 873 return; 874 } 875 break; 876 default: 877 break; 878 } 879 880 at91_write(priv, AT91_IDR, reg_idr); 881 at91_write(priv, AT91_IER, reg_ier); 882} 883 884static void at91_irq_err(struct net_device *dev) 885{ 886 struct at91_priv *priv = netdev_priv(dev); 887 struct sk_buff *skb; 888 struct can_frame *cf; 889 enum can_state new_state; 890 u32 reg_sr; 891 892 reg_sr = at91_read(priv, AT91_SR); 893 894 /* we need to look at the unmasked reg_sr */ 895 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 896 new_state = CAN_STATE_BUS_OFF; 897 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 898 new_state = CAN_STATE_ERROR_PASSIVE; 899 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 900 new_state = CAN_STATE_ERROR_WARNING; 901 else if (likely(reg_sr & AT91_IRQ_ERRA)) 902 new_state = CAN_STATE_ERROR_ACTIVE; 903 else { 904 dev_err(dev->dev.parent, "BUG! hardware in undefined state\n"); 905 return; 906 } 907 908 /* state hasn't changed */ 909 if (likely(new_state == priv->can.state)) 910 return; 911 912 skb = alloc_can_err_skb(dev, &cf); 913 if (unlikely(!skb)) 914 return; 915 916 at91_irq_err_state(dev, cf, new_state); 917 netif_rx(skb); 918 919 dev->stats.rx_packets++; 920 dev->stats.rx_bytes += cf->can_dlc; 921 922 priv->can.state = new_state; 923} 924 925/* 926 * interrupt handler 927 */ 928static irqreturn_t at91_irq(int irq, void *dev_id) 929{ 930 struct net_device *dev = dev_id; 931 struct at91_priv *priv = netdev_priv(dev); 932 irqreturn_t handled = IRQ_NONE; 933 u32 reg_sr, reg_imr; 934 935 reg_sr = at91_read(priv, AT91_SR); 936 reg_imr = at91_read(priv, AT91_IMR); 937 938 /* Ignore masked interrupts */ 939 reg_sr &= reg_imr; 940 if (!reg_sr) 941 goto exit; 942 943 handled = IRQ_HANDLED; 944 945 /* Receive or error interrupt? -> napi */ 946 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 947 /* 948 * The error bits are clear on read, 949 * save for later use. 950 */ 951 priv->reg_sr = reg_sr; 952 at91_write(priv, AT91_IDR, 953 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 954 napi_schedule(&priv->napi); 955 } 956 957 /* Transmission complete interrupt */ 958 if (reg_sr & AT91_IRQ_MB_TX) 959 at91_irq_tx(dev, reg_sr); 960 961 at91_irq_err(dev); 962 963 exit: 964 return handled; 965} 966 967static int at91_open(struct net_device *dev) 968{ 969 struct at91_priv *priv = netdev_priv(dev); 970 int err; 971 972 clk_enable(priv->clk); 973 974 /* check or determine and set bittime */ 975 err = open_candev(dev); 976 if (err) 977 goto out; 978 979 /* register interrupt handler */ 980 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 981 dev->name, dev)) { 982 err = -EAGAIN; 983 goto out_close; 984 } 985 986 /* start chip and queuing */ 987 at91_chip_start(dev); 988 napi_enable(&priv->napi); 989 netif_start_queue(dev); 990 991 return 0; 992 993 out_close: 994 close_candev(dev); 995 out: 996 clk_disable(priv->clk); 997 998 return err; 999} 1000 1001/* 1002 * stop CAN bus activity 1003 */ 1004static int at91_close(struct net_device *dev) 1005{ 1006 struct at91_priv *priv = netdev_priv(dev); 1007 1008 netif_stop_queue(dev); 1009 napi_disable(&priv->napi); 1010 at91_chip_stop(dev, CAN_STATE_STOPPED); 1011 1012 free_irq(dev->irq, dev); 1013 clk_disable(priv->clk); 1014 1015 close_candev(dev); 1016 1017 return 0; 1018} 1019 1020static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1021{ 1022 switch (mode) { 1023 case CAN_MODE_START: 1024 at91_chip_start(dev); 1025 netif_wake_queue(dev); 1026 break; 1027 1028 default: 1029 return -EOPNOTSUPP; 1030 } 1031 1032 return 0; 1033} 1034 1035static const struct net_device_ops at91_netdev_ops = { 1036 .ndo_open = at91_open, 1037 .ndo_stop = at91_close, 1038 .ndo_start_xmit = at91_start_xmit, 1039}; 1040 1041static int __devinit at91_can_probe(struct platform_device *pdev) 1042{ 1043 struct net_device *dev; 1044 struct at91_priv *priv; 1045 struct resource *res; 1046 struct clk *clk; 1047 void __iomem *addr; 1048 int err, irq; 1049 1050 clk = clk_get(&pdev->dev, "can_clk"); 1051 if (IS_ERR(clk)) { 1052 dev_err(&pdev->dev, "no clock defined\n"); 1053 err = -ENODEV; 1054 goto exit; 1055 } 1056 1057 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1058 irq = platform_get_irq(pdev, 0); 1059 if (!res || irq <= 0) { 1060 err = -ENODEV; 1061 goto exit_put; 1062 } 1063 1064 if (!request_mem_region(res->start, 1065 resource_size(res), 1066 pdev->name)) { 1067 err = -EBUSY; 1068 goto exit_put; 1069 } 1070 1071 addr = ioremap_nocache(res->start, resource_size(res)); 1072 if (!addr) { 1073 err = -ENOMEM; 1074 goto exit_release; 1075 } 1076 1077 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1078 if (!dev) { 1079 err = -ENOMEM; 1080 goto exit_iounmap; 1081 } 1082 1083 dev->netdev_ops = &at91_netdev_ops; 1084 dev->irq = irq; 1085 dev->flags |= IFF_ECHO; 1086 1087 priv = netdev_priv(dev); 1088 priv->can.clock.freq = clk_get_rate(clk); 1089 priv->can.bittiming_const = &at91_bittiming_const; 1090 priv->can.do_set_mode = at91_set_mode; 1091 priv->can.do_get_berr_counter = at91_get_berr_counter; 1092 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1093 priv->reg_base = addr; 1094 priv->dev = dev; 1095 priv->clk = clk; 1096 priv->pdata = pdev->dev.platform_data; 1097 1098 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1099 1100 dev_set_drvdata(&pdev->dev, dev); 1101 SET_NETDEV_DEV(dev, &pdev->dev); 1102 1103 err = register_candev(dev); 1104 if (err) { 1105 dev_err(&pdev->dev, "registering netdev failed\n"); 1106 goto exit_free; 1107 } 1108 1109 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1110 priv->reg_base, dev->irq); 1111 1112 return 0; 1113 1114 exit_free: 1115 free_candev(dev); 1116 exit_iounmap: 1117 iounmap(addr); 1118 exit_release: 1119 release_mem_region(res->start, resource_size(res)); 1120 exit_put: 1121 clk_put(clk); 1122 exit: 1123 return err; 1124} 1125 1126static int __devexit at91_can_remove(struct platform_device *pdev) 1127{ 1128 struct net_device *dev = platform_get_drvdata(pdev); 1129 struct at91_priv *priv = netdev_priv(dev); 1130 struct resource *res; 1131 1132 unregister_netdev(dev); 1133 1134 platform_set_drvdata(pdev, NULL); 1135 1136 iounmap(priv->reg_base); 1137 1138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1139 release_mem_region(res->start, resource_size(res)); 1140 1141 clk_put(priv->clk); 1142 1143 free_candev(dev); 1144 1145 return 0; 1146} 1147 1148static struct platform_driver at91_can_driver = { 1149 .probe = at91_can_probe, 1150 .remove = __devexit_p(at91_can_remove), 1151 .driver = { 1152 .name = DRV_NAME, 1153 .owner = THIS_MODULE, 1154 }, 1155}; 1156 1157static int __init at91_can_module_init(void) 1158{ 1159 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME); 1160 return platform_driver_register(&at91_can_driver); 1161} 1162 1163static void __exit at91_can_module_exit(void) 1164{ 1165 platform_driver_unregister(&at91_can_driver); 1166 printk(KERN_INFO "%s: driver removed\n", DRV_NAME); 1167} 1168 1169module_init(at91_can_module_init); 1170module_exit(at91_can_module_exit); 1171 1172MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1173MODULE_LICENSE("GPL v2"); 1174MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver"); 1175