at91_can.c revision dbe91325c2d6ad34c1ce4f2aeae4bbd11b7a3fff
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de> 5 * (C) 2008, 2009, 2010 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/skbuff.h> 34#include <linux/spinlock.h> 35#include <linux/string.h> 36#include <linux/types.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40 41#include <mach/board.h> 42 43#define DRV_NAME "at91_can" 44#define AT91_NAPI_WEIGHT 12 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_RX_NUM 12 51#define AT91_MB_TX_SHIFT 2 52 53#define AT91_MB_RX_FIRST 0 54#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 55 56#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 57#define AT91_MB_RX_SPLIT 8 58#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 59#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT)) 60 61#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 62#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 63#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 64 65#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 66#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 67#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 68#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 69 70/* Common registers */ 71enum at91_reg { 72 AT91_MR = 0x000, 73 AT91_IER = 0x004, 74 AT91_IDR = 0x008, 75 AT91_IMR = 0x00C, 76 AT91_SR = 0x010, 77 AT91_BR = 0x014, 78 AT91_TIM = 0x018, 79 AT91_TIMESTP = 0x01C, 80 AT91_ECR = 0x020, 81 AT91_TCR = 0x024, 82 AT91_ACR = 0x028, 83}; 84 85/* Mailbox registers (0 <= i <= 15) */ 86#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 87#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 88#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 89#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 90#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 91#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 92#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 93#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 94 95/* Register bits */ 96#define AT91_MR_CANEN BIT(0) 97#define AT91_MR_LPM BIT(1) 98#define AT91_MR_ABM BIT(2) 99#define AT91_MR_OVL BIT(3) 100#define AT91_MR_TEOF BIT(4) 101#define AT91_MR_TTM BIT(5) 102#define AT91_MR_TIMFRZ BIT(6) 103#define AT91_MR_DRPT BIT(7) 104 105#define AT91_SR_RBSY BIT(29) 106 107#define AT91_MMR_PRIO_SHIFT (16) 108 109#define AT91_MID_MIDE BIT(29) 110 111#define AT91_MSR_MRTR BIT(20) 112#define AT91_MSR_MABT BIT(22) 113#define AT91_MSR_MRDY BIT(23) 114#define AT91_MSR_MMI BIT(24) 115 116#define AT91_MCR_MRTR BIT(20) 117#define AT91_MCR_MTCR BIT(23) 118 119/* Mailbox Modes */ 120enum at91_mb_mode { 121 AT91_MB_MODE_DISABLED = 0, 122 AT91_MB_MODE_RX = 1, 123 AT91_MB_MODE_RX_OVRWR = 2, 124 AT91_MB_MODE_TX = 3, 125 AT91_MB_MODE_CONSUMER = 4, 126 AT91_MB_MODE_PRODUCER = 5, 127}; 128 129/* Interrupt mask bits */ 130#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 131 - (1 << AT91_MB_RX_FIRST)) 132#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 133 - (1 << AT91_MB_TX_FIRST)) 134#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 135 136#define AT91_IRQ_ERRA (1 << 16) 137#define AT91_IRQ_WARN (1 << 17) 138#define AT91_IRQ_ERRP (1 << 18) 139#define AT91_IRQ_BOFF (1 << 19) 140#define AT91_IRQ_SLEEP (1 << 20) 141#define AT91_IRQ_WAKEUP (1 << 21) 142#define AT91_IRQ_TOVF (1 << 22) 143#define AT91_IRQ_TSTP (1 << 23) 144#define AT91_IRQ_CERR (1 << 24) 145#define AT91_IRQ_SERR (1 << 25) 146#define AT91_IRQ_AERR (1 << 26) 147#define AT91_IRQ_FERR (1 << 27) 148#define AT91_IRQ_BERR (1 << 28) 149 150#define AT91_IRQ_ERR_ALL (0x1fff0000) 151#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 152 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 153#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 154 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 155 156#define AT91_IRQ_ALL (0x1fffffff) 157 158struct at91_priv { 159 struct can_priv can; /* must be the first member! */ 160 struct net_device *dev; 161 struct napi_struct napi; 162 163 void __iomem *reg_base; 164 165 u32 reg_sr; 166 unsigned int tx_next; 167 unsigned int tx_echo; 168 unsigned int rx_next; 169 170 struct clk *clk; 171 struct at91_can_data *pdata; 172}; 173 174static struct can_bittiming_const at91_bittiming_const = { 175 .tseg1_min = 4, 176 .tseg1_max = 16, 177 .tseg2_min = 2, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 2, 181 .brp_max = 128, 182 .brp_inc = 1, 183}; 184 185static inline int get_tx_next_mb(const struct at91_priv *priv) 186{ 187 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 188} 189 190static inline int get_tx_next_prio(const struct at91_priv *priv) 191{ 192 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 193} 194 195static inline int get_tx_echo_mb(const struct at91_priv *priv) 196{ 197 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 198} 199 200static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 201{ 202 return readl(priv->reg_base + reg); 203} 204 205static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 206 u32 value) 207{ 208 writel(value, priv->reg_base + reg); 209} 210 211static inline void set_mb_mode_prio(const struct at91_priv *priv, 212 unsigned int mb, enum at91_mb_mode mode, int prio) 213{ 214 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 215} 216 217static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 218 enum at91_mb_mode mode) 219{ 220 set_mb_mode_prio(priv, mb, mode, 0); 221} 222 223/* 224 * Swtich transceiver on or off 225 */ 226static void at91_transceiver_switch(const struct at91_priv *priv, int on) 227{ 228 if (priv->pdata && priv->pdata->transceiver_switch) 229 priv->pdata->transceiver_switch(on); 230} 231 232static void at91_setup_mailboxes(struct net_device *dev) 233{ 234 struct at91_priv *priv = netdev_priv(dev); 235 unsigned int i; 236 237 /* 238 * The first 12 mailboxes are used as a reception FIFO. The 239 * last mailbox is configured with overwrite option. The 240 * overwrite flag indicates a FIFO overflow. 241 */ 242 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 243 set_mb_mode(priv, i, AT91_MB_MODE_RX); 244 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 245 246 /* The last 4 mailboxes are used for transmitting. */ 247 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 248 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 249 250 /* Reset tx and rx helper pointers */ 251 priv->tx_next = priv->tx_echo = priv->rx_next = 0; 252} 253 254static int at91_set_bittiming(struct net_device *dev) 255{ 256 const struct at91_priv *priv = netdev_priv(dev); 257 const struct can_bittiming *bt = &priv->can.bittiming; 258 u32 reg_br; 259 260 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 261 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 262 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 263 ((bt->phase_seg2 - 1) << 0); 264 265 dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br); 266 267 at91_write(priv, AT91_BR, reg_br); 268 269 return 0; 270} 271 272static void at91_chip_start(struct net_device *dev) 273{ 274 struct at91_priv *priv = netdev_priv(dev); 275 u32 reg_mr, reg_ier; 276 277 /* disable interrupts */ 278 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 279 280 /* disable chip */ 281 reg_mr = at91_read(priv, AT91_MR); 282 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 283 284 at91_setup_mailboxes(dev); 285 at91_transceiver_switch(priv, 1); 286 287 /* enable chip */ 288 at91_write(priv, AT91_MR, AT91_MR_CANEN); 289 290 priv->can.state = CAN_STATE_ERROR_ACTIVE; 291 292 /* Enable interrupts */ 293 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 294 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 295 at91_write(priv, AT91_IER, reg_ier); 296} 297 298static void at91_chip_stop(struct net_device *dev, enum can_state state) 299{ 300 struct at91_priv *priv = netdev_priv(dev); 301 u32 reg_mr; 302 303 /* disable interrupts */ 304 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 305 306 reg_mr = at91_read(priv, AT91_MR); 307 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 308 309 at91_transceiver_switch(priv, 0); 310 priv->can.state = state; 311} 312 313/* 314 * theory of operation: 315 * 316 * According to the datasheet priority 0 is the highest priority, 15 317 * is the lowest. If two mailboxes have the same priority level the 318 * message of the mailbox with the lowest number is sent first. 319 * 320 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 321 * the next mailbox with prio 0, and so on, until all mailboxes are 322 * used. Then we start from the beginning with mailbox 323 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 324 * prio 1. When we reach the last mailbox with prio 15, we have to 325 * stop sending, waiting for all messages to be delivered, then start 326 * again with mailbox AT91_MB_TX_FIRST prio 0. 327 * 328 * We use the priv->tx_next as counter for the next transmission 329 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 330 * encode the mailbox number, the upper 4 bits the mailbox priority: 331 * 332 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) || 333 * (mb - AT91_MB_TX_FIRST); 334 * 335 */ 336static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 337{ 338 struct at91_priv *priv = netdev_priv(dev); 339 struct net_device_stats *stats = &dev->stats; 340 struct can_frame *cf = (struct can_frame *)skb->data; 341 unsigned int mb, prio; 342 u32 reg_mid, reg_mcr; 343 344 if (can_dropped_invalid_skb(dev, skb)) 345 return NETDEV_TX_OK; 346 347 mb = get_tx_next_mb(priv); 348 prio = get_tx_next_prio(priv); 349 350 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 351 netif_stop_queue(dev); 352 353 dev_err(dev->dev.parent, 354 "BUG! TX buffer full when queue awake!\n"); 355 return NETDEV_TX_BUSY; 356 } 357 358 if (cf->can_id & CAN_EFF_FLAG) 359 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 360 else 361 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18; 362 363 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 364 (cf->can_dlc << 16) | AT91_MCR_MTCR; 365 366 /* disable MB while writing ID (see datasheet) */ 367 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 368 at91_write(priv, AT91_MID(mb), reg_mid); 369 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 370 371 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 372 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 373 374 /* This triggers transmission */ 375 at91_write(priv, AT91_MCR(mb), reg_mcr); 376 377 stats->tx_bytes += cf->can_dlc; 378 379 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 380 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 381 382 /* 383 * we have to stop the queue and deliver all messages in case 384 * of a prio+mb counter wrap around. This is the case if 385 * tx_next buffer prio and mailbox equals 0. 386 * 387 * also stop the queue if next buffer is still in use 388 * (== not ready) 389 */ 390 priv->tx_next++; 391 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 392 AT91_MSR_MRDY) || 393 (priv->tx_next & AT91_NEXT_MASK) == 0) 394 netif_stop_queue(dev); 395 396 /* Enable interrupt for this mailbox */ 397 at91_write(priv, AT91_IER, 1 << mb); 398 399 return NETDEV_TX_OK; 400} 401 402/** 403 * at91_activate_rx_low - activate lower rx mailboxes 404 * @priv: a91 context 405 * 406 * Reenables the lower mailboxes for reception of new CAN messages 407 */ 408static inline void at91_activate_rx_low(const struct at91_priv *priv) 409{ 410 u32 mask = AT91_MB_RX_LOW_MASK; 411 at91_write(priv, AT91_TCR, mask); 412} 413 414/** 415 * at91_activate_rx_mb - reactive single rx mailbox 416 * @priv: a91 context 417 * @mb: mailbox to reactivate 418 * 419 * Reenables given mailbox for reception of new CAN messages 420 */ 421static inline void at91_activate_rx_mb(const struct at91_priv *priv, 422 unsigned int mb) 423{ 424 u32 mask = 1 << mb; 425 at91_write(priv, AT91_TCR, mask); 426} 427 428/** 429 * at91_rx_overflow_err - send error frame due to rx overflow 430 * @dev: net device 431 */ 432static void at91_rx_overflow_err(struct net_device *dev) 433{ 434 struct net_device_stats *stats = &dev->stats; 435 struct sk_buff *skb; 436 struct can_frame *cf; 437 438 dev_dbg(dev->dev.parent, "RX buffer overflow\n"); 439 stats->rx_over_errors++; 440 stats->rx_errors++; 441 442 skb = alloc_can_err_skb(dev, &cf); 443 if (unlikely(!skb)) 444 return; 445 446 cf->can_id |= CAN_ERR_CRTL; 447 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 448 netif_receive_skb(skb); 449 450 stats->rx_packets++; 451 stats->rx_bytes += cf->can_dlc; 452} 453 454/** 455 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 456 * @dev: net device 457 * @mb: mailbox number to read from 458 * @cf: can frame where to store message 459 * 460 * Reads a CAN message from the given mailbox and stores data into 461 * given can frame. "mb" and "cf" must be valid. 462 */ 463static void at91_read_mb(struct net_device *dev, unsigned int mb, 464 struct can_frame *cf) 465{ 466 const struct at91_priv *priv = netdev_priv(dev); 467 u32 reg_msr, reg_mid; 468 469 reg_mid = at91_read(priv, AT91_MID(mb)); 470 if (reg_mid & AT91_MID_MIDE) 471 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 472 else 473 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 474 475 reg_msr = at91_read(priv, AT91_MSR(mb)); 476 if (reg_msr & AT91_MSR_MRTR) 477 cf->can_id |= CAN_RTR_FLAG; 478 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 479 480 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 481 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 482 483 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 484 at91_rx_overflow_err(dev); 485} 486 487/** 488 * at91_read_msg - read CAN message from mailbox 489 * @dev: net device 490 * @mb: mail box to read from 491 * 492 * Reads a CAN message from given mailbox, and put into linux network 493 * RX queue, does all housekeeping chores (stats, ...) 494 */ 495static void at91_read_msg(struct net_device *dev, unsigned int mb) 496{ 497 struct net_device_stats *stats = &dev->stats; 498 struct can_frame *cf; 499 struct sk_buff *skb; 500 501 skb = alloc_can_skb(dev, &cf); 502 if (unlikely(!skb)) { 503 stats->rx_dropped++; 504 return; 505 } 506 507 at91_read_mb(dev, mb, cf); 508 netif_receive_skb(skb); 509 510 stats->rx_packets++; 511 stats->rx_bytes += cf->can_dlc; 512} 513 514/** 515 * at91_poll_rx - read multiple CAN messages from mailboxes 516 * @dev: net device 517 * @quota: max number of pkgs we're allowed to receive 518 * 519 * Theory of Operation: 520 * 521 * 12 of the 16 mailboxes on the chip are reserved for RX. we split 522 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes. 523 * 524 * Like it or not, but the chip always saves a received CAN message 525 * into the first free mailbox it finds (starting with the 526 * lowest). This makes it very difficult to read the messages in the 527 * right order from the chip. This is how we work around that problem: 528 * 529 * The first message goes into mb nr. 0 and issues an interrupt. All 530 * rx ints are disabled in the interrupt handler and a napi poll is 531 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 532 * receive another message). 533 * 534 * lower mbxs upper 535 * ______^______ __^__ 536 * / \ / \ 537 * +-+-+-+-+-+-+-+-++-+-+-+-+ 538 * |x|x|x|x|x|x|x|x|| | | | | 539 * +-+-+-+-+-+-+-+-++-+-+-+-+ 540 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 541 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 542 * 543 * The variable priv->rx_next points to the next mailbox to read a 544 * message from. As long we're in the lower mailboxes we just read the 545 * mailbox but not reenable it. 546 * 547 * With completion of the last of the lower mailboxes, we reenable the 548 * whole first group, but continue to look for filled mailboxes in the 549 * upper mailboxes. Imagine the second group like overflow mailboxes, 550 * which takes CAN messages if the lower goup is full. While in the 551 * upper group we reenable the mailbox right after reading it. Giving 552 * the chip more room to store messages. 553 * 554 * After finishing we look again in the lower group if we've still 555 * quota. 556 * 557 */ 558static int at91_poll_rx(struct net_device *dev, int quota) 559{ 560 struct at91_priv *priv = netdev_priv(dev); 561 u32 reg_sr = at91_read(priv, AT91_SR); 562 const unsigned long *addr = (unsigned long *)®_sr; 563 unsigned int mb; 564 int received = 0; 565 566 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 567 reg_sr & AT91_MB_RX_LOW_MASK) 568 dev_info(dev->dev.parent, 569 "order of incoming frames cannot be guaranteed\n"); 570 571 again: 572 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next); 573 mb < AT91_MB_RX_NUM && quota > 0; 574 reg_sr = at91_read(priv, AT91_SR), 575 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) { 576 at91_read_msg(dev, mb); 577 578 /* reactivate mailboxes */ 579 if (mb == AT91_MB_RX_LOW_LAST) 580 /* all lower mailboxed, if just finished it */ 581 at91_activate_rx_low(priv); 582 else if (mb > AT91_MB_RX_LOW_LAST) 583 /* only the mailbox we read */ 584 at91_activate_rx_mb(priv, mb); 585 586 received++; 587 quota--; 588 } 589 590 /* upper group completed, look again in lower */ 591 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 592 quota > 0 && mb >= AT91_MB_RX_NUM) { 593 priv->rx_next = 0; 594 goto again; 595 } 596 597 return received; 598} 599 600static void at91_poll_err_frame(struct net_device *dev, 601 struct can_frame *cf, u32 reg_sr) 602{ 603 struct at91_priv *priv = netdev_priv(dev); 604 605 /* CRC error */ 606 if (reg_sr & AT91_IRQ_CERR) { 607 dev_dbg(dev->dev.parent, "CERR irq\n"); 608 dev->stats.rx_errors++; 609 priv->can.can_stats.bus_error++; 610 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 611 } 612 613 /* Stuffing Error */ 614 if (reg_sr & AT91_IRQ_SERR) { 615 dev_dbg(dev->dev.parent, "SERR irq\n"); 616 dev->stats.rx_errors++; 617 priv->can.can_stats.bus_error++; 618 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 619 cf->data[2] |= CAN_ERR_PROT_STUFF; 620 } 621 622 /* Acknowledgement Error */ 623 if (reg_sr & AT91_IRQ_AERR) { 624 dev_dbg(dev->dev.parent, "AERR irq\n"); 625 dev->stats.tx_errors++; 626 cf->can_id |= CAN_ERR_ACK; 627 } 628 629 /* Form error */ 630 if (reg_sr & AT91_IRQ_FERR) { 631 dev_dbg(dev->dev.parent, "FERR irq\n"); 632 dev->stats.rx_errors++; 633 priv->can.can_stats.bus_error++; 634 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 635 cf->data[2] |= CAN_ERR_PROT_FORM; 636 } 637 638 /* Bit Error */ 639 if (reg_sr & AT91_IRQ_BERR) { 640 dev_dbg(dev->dev.parent, "BERR irq\n"); 641 dev->stats.tx_errors++; 642 priv->can.can_stats.bus_error++; 643 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 644 cf->data[2] |= CAN_ERR_PROT_BIT; 645 } 646} 647 648static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 649{ 650 struct sk_buff *skb; 651 struct can_frame *cf; 652 653 if (quota == 0) 654 return 0; 655 656 skb = alloc_can_err_skb(dev, &cf); 657 if (unlikely(!skb)) 658 return 0; 659 660 at91_poll_err_frame(dev, cf, reg_sr); 661 netif_receive_skb(skb); 662 663 dev->stats.rx_packets++; 664 dev->stats.rx_bytes += cf->can_dlc; 665 666 return 1; 667} 668 669static int at91_poll(struct napi_struct *napi, int quota) 670{ 671 struct net_device *dev = napi->dev; 672 const struct at91_priv *priv = netdev_priv(dev); 673 u32 reg_sr = at91_read(priv, AT91_SR); 674 int work_done = 0; 675 676 if (reg_sr & AT91_IRQ_MB_RX) 677 work_done += at91_poll_rx(dev, quota - work_done); 678 679 /* 680 * The error bits are clear on read, 681 * so use saved value from irq handler. 682 */ 683 reg_sr |= priv->reg_sr; 684 if (reg_sr & AT91_IRQ_ERR_FRAME) 685 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 686 687 if (work_done < quota) { 688 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 689 u32 reg_ier = AT91_IRQ_ERR_FRAME; 690 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 691 692 napi_complete(napi); 693 at91_write(priv, AT91_IER, reg_ier); 694 } 695 696 return work_done; 697} 698 699/* 700 * theory of operation: 701 * 702 * priv->tx_echo holds the number of the oldest can_frame put for 703 * transmission into the hardware, but not yet ACKed by the CAN tx 704 * complete IRQ. 705 * 706 * We iterate from priv->tx_echo to priv->tx_next and check if the 707 * packet has been transmitted, echo it back to the CAN framework. If 708 * we discover a not yet transmitted package, stop looking for more. 709 * 710 */ 711static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 712{ 713 struct at91_priv *priv = netdev_priv(dev); 714 u32 reg_msr; 715 unsigned int mb; 716 717 /* masking of reg_sr not needed, already done by at91_irq */ 718 719 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 720 mb = get_tx_echo_mb(priv); 721 722 /* no event in mailbox? */ 723 if (!(reg_sr & (1 << mb))) 724 break; 725 726 /* Disable irq for this TX mailbox */ 727 at91_write(priv, AT91_IDR, 1 << mb); 728 729 /* 730 * only echo if mailbox signals us a transfer 731 * complete (MSR_MRDY). Otherwise it's a tansfer 732 * abort. "can_bus_off()" takes care about the skbs 733 * parked in the echo queue. 734 */ 735 reg_msr = at91_read(priv, AT91_MSR(mb)); 736 if (likely(reg_msr & AT91_MSR_MRDY && 737 ~reg_msr & AT91_MSR_MABT)) { 738 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */ 739 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 740 dev->stats.tx_packets++; 741 } 742 } 743 744 /* 745 * restart queue if we don't have a wrap around but restart if 746 * we get a TX int for the last can frame directly before a 747 * wrap around. 748 */ 749 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 750 (priv->tx_echo & AT91_NEXT_MASK) == 0) 751 netif_wake_queue(dev); 752} 753 754static void at91_irq_err_state(struct net_device *dev, 755 struct can_frame *cf, enum can_state new_state) 756{ 757 struct at91_priv *priv = netdev_priv(dev); 758 u32 reg_idr, reg_ier, reg_ecr; 759 u8 tec, rec; 760 761 reg_ecr = at91_read(priv, AT91_ECR); 762 rec = reg_ecr & 0xff; 763 tec = reg_ecr >> 16; 764 765 switch (priv->can.state) { 766 case CAN_STATE_ERROR_ACTIVE: 767 /* 768 * from: ERROR_ACTIVE 769 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 770 * => : there was a warning int 771 */ 772 if (new_state >= CAN_STATE_ERROR_WARNING && 773 new_state <= CAN_STATE_BUS_OFF) { 774 dev_dbg(dev->dev.parent, "Error Warning IRQ\n"); 775 priv->can.can_stats.error_warning++; 776 777 cf->can_id |= CAN_ERR_CRTL; 778 cf->data[1] = (tec > rec) ? 779 CAN_ERR_CRTL_TX_WARNING : 780 CAN_ERR_CRTL_RX_WARNING; 781 } 782 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 783 /* 784 * from: ERROR_ACTIVE, ERROR_WARNING 785 * to : ERROR_PASSIVE, BUS_OFF 786 * => : error passive int 787 */ 788 if (new_state >= CAN_STATE_ERROR_PASSIVE && 789 new_state <= CAN_STATE_BUS_OFF) { 790 dev_dbg(dev->dev.parent, "Error Passive IRQ\n"); 791 priv->can.can_stats.error_passive++; 792 793 cf->can_id |= CAN_ERR_CRTL; 794 cf->data[1] = (tec > rec) ? 795 CAN_ERR_CRTL_TX_PASSIVE : 796 CAN_ERR_CRTL_RX_PASSIVE; 797 } 798 break; 799 case CAN_STATE_BUS_OFF: 800 /* 801 * from: BUS_OFF 802 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 803 */ 804 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 805 cf->can_id |= CAN_ERR_RESTARTED; 806 807 dev_dbg(dev->dev.parent, "restarted\n"); 808 priv->can.can_stats.restarts++; 809 810 netif_carrier_on(dev); 811 netif_wake_queue(dev); 812 } 813 break; 814 default: 815 break; 816 } 817 818 819 /* process state changes depending on the new state */ 820 switch (new_state) { 821 case CAN_STATE_ERROR_ACTIVE: 822 /* 823 * actually we want to enable AT91_IRQ_WARN here, but 824 * it screws up the system under certain 825 * circumstances. so just enable AT91_IRQ_ERRP, thus 826 * the "fallthrough" 827 */ 828 dev_dbg(dev->dev.parent, "Error Active\n"); 829 cf->can_id |= CAN_ERR_PROT; 830 cf->data[2] = CAN_ERR_PROT_ACTIVE; 831 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 832 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 833 reg_ier = AT91_IRQ_ERRP; 834 break; 835 case CAN_STATE_ERROR_PASSIVE: 836 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 837 reg_ier = AT91_IRQ_BOFF; 838 break; 839 case CAN_STATE_BUS_OFF: 840 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 841 AT91_IRQ_WARN | AT91_IRQ_BOFF; 842 reg_ier = 0; 843 844 cf->can_id |= CAN_ERR_BUSOFF; 845 846 dev_dbg(dev->dev.parent, "bus-off\n"); 847 netif_carrier_off(dev); 848 priv->can.can_stats.bus_off++; 849 850 /* turn off chip, if restart is disabled */ 851 if (!priv->can.restart_ms) { 852 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 853 return; 854 } 855 break; 856 default: 857 break; 858 } 859 860 at91_write(priv, AT91_IDR, reg_idr); 861 at91_write(priv, AT91_IER, reg_ier); 862} 863 864static void at91_irq_err(struct net_device *dev) 865{ 866 struct at91_priv *priv = netdev_priv(dev); 867 struct sk_buff *skb; 868 struct can_frame *cf; 869 enum can_state new_state; 870 u32 reg_sr; 871 872 reg_sr = at91_read(priv, AT91_SR); 873 874 /* we need to look at the unmasked reg_sr */ 875 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 876 new_state = CAN_STATE_BUS_OFF; 877 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 878 new_state = CAN_STATE_ERROR_PASSIVE; 879 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 880 new_state = CAN_STATE_ERROR_WARNING; 881 else if (likely(reg_sr & AT91_IRQ_ERRA)) 882 new_state = CAN_STATE_ERROR_ACTIVE; 883 else { 884 dev_err(dev->dev.parent, "BUG! hardware in undefined state\n"); 885 return; 886 } 887 888 /* state hasn't changed */ 889 if (likely(new_state == priv->can.state)) 890 return; 891 892 skb = alloc_can_err_skb(dev, &cf); 893 if (unlikely(!skb)) 894 return; 895 896 at91_irq_err_state(dev, cf, new_state); 897 netif_rx(skb); 898 899 dev->stats.rx_packets++; 900 dev->stats.rx_bytes += cf->can_dlc; 901 902 priv->can.state = new_state; 903} 904 905/* 906 * interrupt handler 907 */ 908static irqreturn_t at91_irq(int irq, void *dev_id) 909{ 910 struct net_device *dev = dev_id; 911 struct at91_priv *priv = netdev_priv(dev); 912 irqreturn_t handled = IRQ_NONE; 913 u32 reg_sr, reg_imr; 914 915 reg_sr = at91_read(priv, AT91_SR); 916 reg_imr = at91_read(priv, AT91_IMR); 917 918 /* Ignore masked interrupts */ 919 reg_sr &= reg_imr; 920 if (!reg_sr) 921 goto exit; 922 923 handled = IRQ_HANDLED; 924 925 /* Receive or error interrupt? -> napi */ 926 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 927 /* 928 * The error bits are clear on read, 929 * save for later use. 930 */ 931 priv->reg_sr = reg_sr; 932 at91_write(priv, AT91_IDR, 933 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 934 napi_schedule(&priv->napi); 935 } 936 937 /* Transmission complete interrupt */ 938 if (reg_sr & AT91_IRQ_MB_TX) 939 at91_irq_tx(dev, reg_sr); 940 941 at91_irq_err(dev); 942 943 exit: 944 return handled; 945} 946 947static int at91_open(struct net_device *dev) 948{ 949 struct at91_priv *priv = netdev_priv(dev); 950 int err; 951 952 clk_enable(priv->clk); 953 954 /* check or determine and set bittime */ 955 err = open_candev(dev); 956 if (err) 957 goto out; 958 959 /* register interrupt handler */ 960 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 961 dev->name, dev)) { 962 err = -EAGAIN; 963 goto out_close; 964 } 965 966 /* start chip and queuing */ 967 at91_chip_start(dev); 968 napi_enable(&priv->napi); 969 netif_start_queue(dev); 970 971 return 0; 972 973 out_close: 974 close_candev(dev); 975 out: 976 clk_disable(priv->clk); 977 978 return err; 979} 980 981/* 982 * stop CAN bus activity 983 */ 984static int at91_close(struct net_device *dev) 985{ 986 struct at91_priv *priv = netdev_priv(dev); 987 988 netif_stop_queue(dev); 989 napi_disable(&priv->napi); 990 at91_chip_stop(dev, CAN_STATE_STOPPED); 991 992 free_irq(dev->irq, dev); 993 clk_disable(priv->clk); 994 995 close_candev(dev); 996 997 return 0; 998} 999 1000static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1001{ 1002 switch (mode) { 1003 case CAN_MODE_START: 1004 at91_chip_start(dev); 1005 netif_wake_queue(dev); 1006 break; 1007 1008 default: 1009 return -EOPNOTSUPP; 1010 } 1011 1012 return 0; 1013} 1014 1015static const struct net_device_ops at91_netdev_ops = { 1016 .ndo_open = at91_open, 1017 .ndo_stop = at91_close, 1018 .ndo_start_xmit = at91_start_xmit, 1019}; 1020 1021static int __init at91_can_probe(struct platform_device *pdev) 1022{ 1023 struct net_device *dev; 1024 struct at91_priv *priv; 1025 struct resource *res; 1026 struct clk *clk; 1027 void __iomem *addr; 1028 int err, irq; 1029 1030 clk = clk_get(&pdev->dev, "can_clk"); 1031 if (IS_ERR(clk)) { 1032 dev_err(&pdev->dev, "no clock defined\n"); 1033 err = -ENODEV; 1034 goto exit; 1035 } 1036 1037 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1038 irq = platform_get_irq(pdev, 0); 1039 if (!res || irq <= 0) { 1040 err = -ENODEV; 1041 goto exit_put; 1042 } 1043 1044 if (!request_mem_region(res->start, 1045 resource_size(res), 1046 pdev->name)) { 1047 err = -EBUSY; 1048 goto exit_put; 1049 } 1050 1051 addr = ioremap_nocache(res->start, resource_size(res)); 1052 if (!addr) { 1053 err = -ENOMEM; 1054 goto exit_release; 1055 } 1056 1057 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1058 if (!dev) { 1059 err = -ENOMEM; 1060 goto exit_iounmap; 1061 } 1062 1063 dev->netdev_ops = &at91_netdev_ops; 1064 dev->irq = irq; 1065 dev->flags |= IFF_ECHO; 1066 1067 priv = netdev_priv(dev); 1068 priv->can.clock.freq = clk_get_rate(clk); 1069 priv->can.bittiming_const = &at91_bittiming_const; 1070 priv->can.do_set_bittiming = at91_set_bittiming; 1071 priv->can.do_set_mode = at91_set_mode; 1072 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1073 priv->reg_base = addr; 1074 priv->dev = dev; 1075 priv->clk = clk; 1076 priv->pdata = pdev->dev.platform_data; 1077 1078 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1079 1080 dev_set_drvdata(&pdev->dev, dev); 1081 SET_NETDEV_DEV(dev, &pdev->dev); 1082 1083 err = register_candev(dev); 1084 if (err) { 1085 dev_err(&pdev->dev, "registering netdev failed\n"); 1086 goto exit_free; 1087 } 1088 1089 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1090 priv->reg_base, dev->irq); 1091 1092 return 0; 1093 1094 exit_free: 1095 free_netdev(dev); 1096 exit_iounmap: 1097 iounmap(addr); 1098 exit_release: 1099 release_mem_region(res->start, resource_size(res)); 1100 exit_put: 1101 clk_put(clk); 1102 exit: 1103 return err; 1104} 1105 1106static int __devexit at91_can_remove(struct platform_device *pdev) 1107{ 1108 struct net_device *dev = platform_get_drvdata(pdev); 1109 struct at91_priv *priv = netdev_priv(dev); 1110 struct resource *res; 1111 1112 unregister_netdev(dev); 1113 1114 platform_set_drvdata(pdev, NULL); 1115 1116 free_netdev(dev); 1117 1118 iounmap(priv->reg_base); 1119 1120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1121 release_mem_region(res->start, resource_size(res)); 1122 1123 clk_put(priv->clk); 1124 1125 return 0; 1126} 1127 1128static struct platform_driver at91_can_driver = { 1129 .probe = at91_can_probe, 1130 .remove = __devexit_p(at91_can_remove), 1131 .driver = { 1132 .name = DRV_NAME, 1133 .owner = THIS_MODULE, 1134 }, 1135}; 1136 1137static int __init at91_can_module_init(void) 1138{ 1139 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME); 1140 return platform_driver_register(&at91_can_driver); 1141} 1142 1143static void __exit at91_can_module_exit(void) 1144{ 1145 platform_driver_unregister(&at91_can_driver); 1146 printk(KERN_INFO "%s: driver removed\n", DRV_NAME); 1147} 1148 1149module_init(at91_can_module_init); 1150module_exit(at91_can_module_exit); 1151 1152MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1153MODULE_LICENSE("GPL v2"); 1154MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver"); 1155