at91_can.c revision e14ee40bece891b5edccdd514112999ec423a448
1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * Send feedback to <socketcan-users@lists.berlios.de> 12 * 13 * 14 * Your platform definition file should specify something like: 15 * 16 * static struct at91_can_data ek_can_data = { 17 * transceiver_switch = sam9263ek_transceiver_switch, 18 * }; 19 * 20 * at91_add_device_can(&ek_can_data); 21 * 22 */ 23 24#include <linux/clk.h> 25#include <linux/errno.h> 26#include <linux/if_arp.h> 27#include <linux/init.h> 28#include <linux/interrupt.h> 29#include <linux/kernel.h> 30#include <linux/module.h> 31#include <linux/netdevice.h> 32#include <linux/platform_device.h> 33#include <linux/rtnetlink.h> 34#include <linux/skbuff.h> 35#include <linux/spinlock.h> 36#include <linux/string.h> 37#include <linux/types.h> 38 39#include <linux/can/dev.h> 40#include <linux/can/error.h> 41 42#include <mach/board.h> 43 44#define AT91_NAPI_WEIGHT 11 45 46/* 47 * RX/TX Mailbox split 48 * don't dare to touch 49 */ 50#define AT91_MB_RX_NUM 11 51#define AT91_MB_TX_SHIFT 2 52 53#define AT91_MB_RX_FIRST 1 54#define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1) 55 56#define AT91_MB_RX_MASK(i) ((1 << (i)) - 1) 57#define AT91_MB_RX_SPLIT 8 58#define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1) 59#define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \ 60 ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST)) 61 62#define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT) 63#define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1) 64#define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1) 65 66#define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT) 67#define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT) 68#define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1) 69#define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK) 70 71/* Common registers */ 72enum at91_reg { 73 AT91_MR = 0x000, 74 AT91_IER = 0x004, 75 AT91_IDR = 0x008, 76 AT91_IMR = 0x00C, 77 AT91_SR = 0x010, 78 AT91_BR = 0x014, 79 AT91_TIM = 0x018, 80 AT91_TIMESTP = 0x01C, 81 AT91_ECR = 0x020, 82 AT91_TCR = 0x024, 83 AT91_ACR = 0x028, 84}; 85 86/* Mailbox registers (0 <= i <= 15) */ 87#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 88#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 89#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 90#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 91#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 92#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 93#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 94#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 95 96/* Register bits */ 97#define AT91_MR_CANEN BIT(0) 98#define AT91_MR_LPM BIT(1) 99#define AT91_MR_ABM BIT(2) 100#define AT91_MR_OVL BIT(3) 101#define AT91_MR_TEOF BIT(4) 102#define AT91_MR_TTM BIT(5) 103#define AT91_MR_TIMFRZ BIT(6) 104#define AT91_MR_DRPT BIT(7) 105 106#define AT91_SR_RBSY BIT(29) 107 108#define AT91_MMR_PRIO_SHIFT (16) 109 110#define AT91_MID_MIDE BIT(29) 111 112#define AT91_MSR_MRTR BIT(20) 113#define AT91_MSR_MABT BIT(22) 114#define AT91_MSR_MRDY BIT(23) 115#define AT91_MSR_MMI BIT(24) 116 117#define AT91_MCR_MRTR BIT(20) 118#define AT91_MCR_MTCR BIT(23) 119 120/* Mailbox Modes */ 121enum at91_mb_mode { 122 AT91_MB_MODE_DISABLED = 0, 123 AT91_MB_MODE_RX = 1, 124 AT91_MB_MODE_RX_OVRWR = 2, 125 AT91_MB_MODE_TX = 3, 126 AT91_MB_MODE_CONSUMER = 4, 127 AT91_MB_MODE_PRODUCER = 5, 128}; 129 130/* Interrupt mask bits */ 131#define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \ 132 - (1 << AT91_MB_RX_FIRST)) 133#define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \ 134 - (1 << AT91_MB_TX_FIRST)) 135#define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX) 136 137#define AT91_IRQ_ERRA (1 << 16) 138#define AT91_IRQ_WARN (1 << 17) 139#define AT91_IRQ_ERRP (1 << 18) 140#define AT91_IRQ_BOFF (1 << 19) 141#define AT91_IRQ_SLEEP (1 << 20) 142#define AT91_IRQ_WAKEUP (1 << 21) 143#define AT91_IRQ_TOVF (1 << 22) 144#define AT91_IRQ_TSTP (1 << 23) 145#define AT91_IRQ_CERR (1 << 24) 146#define AT91_IRQ_SERR (1 << 25) 147#define AT91_IRQ_AERR (1 << 26) 148#define AT91_IRQ_FERR (1 << 27) 149#define AT91_IRQ_BERR (1 << 28) 150 151#define AT91_IRQ_ERR_ALL (0x1fff0000) 152#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 153 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 154#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 155 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 156 157#define AT91_IRQ_ALL (0x1fffffff) 158 159struct at91_priv { 160 struct can_priv can; /* must be the first member! */ 161 struct net_device *dev; 162 struct napi_struct napi; 163 164 void __iomem *reg_base; 165 166 u32 reg_sr; 167 unsigned int tx_next; 168 unsigned int tx_echo; 169 unsigned int rx_next; 170 171 struct clk *clk; 172 struct at91_can_data *pdata; 173 174 canid_t mb0_id; 175}; 176 177static struct can_bittiming_const at91_bittiming_const = { 178 .name = KBUILD_MODNAME, 179 .tseg1_min = 4, 180 .tseg1_max = 16, 181 .tseg2_min = 2, 182 .tseg2_max = 8, 183 .sjw_max = 4, 184 .brp_min = 2, 185 .brp_max = 128, 186 .brp_inc = 1, 187}; 188 189static inline int get_tx_next_mb(const struct at91_priv *priv) 190{ 191 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 192} 193 194static inline int get_tx_next_prio(const struct at91_priv *priv) 195{ 196 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf; 197} 198 199static inline int get_tx_echo_mb(const struct at91_priv *priv) 200{ 201 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST; 202} 203 204static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 205{ 206 return __raw_readl(priv->reg_base + reg); 207} 208 209static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 210 u32 value) 211{ 212 __raw_writel(value, priv->reg_base + reg); 213} 214 215static inline void set_mb_mode_prio(const struct at91_priv *priv, 216 unsigned int mb, enum at91_mb_mode mode, int prio) 217{ 218 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 219} 220 221static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 222 enum at91_mb_mode mode) 223{ 224 set_mb_mode_prio(priv, mb, mode, 0); 225} 226 227static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 228{ 229 u32 reg_mid; 230 231 if (can_id & CAN_EFF_FLAG) 232 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 233 else 234 reg_mid = (can_id & CAN_SFF_MASK) << 18; 235 236 return reg_mid; 237} 238 239/* 240 * Swtich transceiver on or off 241 */ 242static void at91_transceiver_switch(const struct at91_priv *priv, int on) 243{ 244 if (priv->pdata && priv->pdata->transceiver_switch) 245 priv->pdata->transceiver_switch(on); 246} 247 248static void at91_setup_mailboxes(struct net_device *dev) 249{ 250 struct at91_priv *priv = netdev_priv(dev); 251 unsigned int i; 252 u32 reg_mid; 253 254 /* 255 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 256 * mailbox is disabled. The next 11 mailboxes are used as a 257 * reception FIFO. The last mailbox is configured with 258 * overwrite option. The overwrite flag indicates a FIFO 259 * overflow. 260 */ 261 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 262 for (i = 0; i < AT91_MB_RX_FIRST; i++) { 263 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 264 at91_write(priv, AT91_MID(i), reg_mid); 265 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 266 } 267 268 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++) 269 set_mb_mode(priv, i, AT91_MB_MODE_RX); 270 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR); 271 272 /* reset acceptance mask and id register */ 273 for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) { 274 at91_write(priv, AT91_MAM(i), 0x0); 275 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 276 } 277 278 /* The last 4 mailboxes are used for transmitting. */ 279 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++) 280 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 281 282 /* Reset tx and rx helper pointers */ 283 priv->tx_next = priv->tx_echo = 0; 284 priv->rx_next = AT91_MB_RX_FIRST; 285} 286 287static int at91_set_bittiming(struct net_device *dev) 288{ 289 const struct at91_priv *priv = netdev_priv(dev); 290 const struct can_bittiming *bt = &priv->can.bittiming; 291 u32 reg_br; 292 293 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 294 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 295 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 296 ((bt->phase_seg2 - 1) << 0); 297 298 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 299 300 at91_write(priv, AT91_BR, reg_br); 301 302 return 0; 303} 304 305static int at91_get_berr_counter(const struct net_device *dev, 306 struct can_berr_counter *bec) 307{ 308 const struct at91_priv *priv = netdev_priv(dev); 309 u32 reg_ecr = at91_read(priv, AT91_ECR); 310 311 bec->rxerr = reg_ecr & 0xff; 312 bec->txerr = reg_ecr >> 16; 313 314 return 0; 315} 316 317static void at91_chip_start(struct net_device *dev) 318{ 319 struct at91_priv *priv = netdev_priv(dev); 320 u32 reg_mr, reg_ier; 321 322 /* disable interrupts */ 323 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 324 325 /* disable chip */ 326 reg_mr = at91_read(priv, AT91_MR); 327 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 328 329 at91_set_bittiming(dev); 330 at91_setup_mailboxes(dev); 331 at91_transceiver_switch(priv, 1); 332 333 /* enable chip */ 334 at91_write(priv, AT91_MR, AT91_MR_CANEN); 335 336 priv->can.state = CAN_STATE_ERROR_ACTIVE; 337 338 /* Enable interrupts */ 339 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 340 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 341 at91_write(priv, AT91_IER, reg_ier); 342} 343 344static void at91_chip_stop(struct net_device *dev, enum can_state state) 345{ 346 struct at91_priv *priv = netdev_priv(dev); 347 u32 reg_mr; 348 349 /* disable interrupts */ 350 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 351 352 reg_mr = at91_read(priv, AT91_MR); 353 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 354 355 at91_transceiver_switch(priv, 0); 356 priv->can.state = state; 357} 358 359/* 360 * theory of operation: 361 * 362 * According to the datasheet priority 0 is the highest priority, 15 363 * is the lowest. If two mailboxes have the same priority level the 364 * message of the mailbox with the lowest number is sent first. 365 * 366 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 367 * the next mailbox with prio 0, and so on, until all mailboxes are 368 * used. Then we start from the beginning with mailbox 369 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 370 * prio 1. When we reach the last mailbox with prio 15, we have to 371 * stop sending, waiting for all messages to be delivered, then start 372 * again with mailbox AT91_MB_TX_FIRST prio 0. 373 * 374 * We use the priv->tx_next as counter for the next transmission 375 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 376 * encode the mailbox number, the upper 4 bits the mailbox priority: 377 * 378 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) | 379 * (mb - AT91_MB_TX_FIRST); 380 * 381 */ 382static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 383{ 384 struct at91_priv *priv = netdev_priv(dev); 385 struct net_device_stats *stats = &dev->stats; 386 struct can_frame *cf = (struct can_frame *)skb->data; 387 unsigned int mb, prio; 388 u32 reg_mid, reg_mcr; 389 390 if (can_dropped_invalid_skb(dev, skb)) 391 return NETDEV_TX_OK; 392 393 mb = get_tx_next_mb(priv); 394 prio = get_tx_next_prio(priv); 395 396 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 397 netif_stop_queue(dev); 398 399 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 400 return NETDEV_TX_BUSY; 401 } 402 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 403 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 404 (cf->can_dlc << 16) | AT91_MCR_MTCR; 405 406 /* disable MB while writing ID (see datasheet) */ 407 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 408 at91_write(priv, AT91_MID(mb), reg_mid); 409 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 410 411 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 412 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 413 414 /* This triggers transmission */ 415 at91_write(priv, AT91_MCR(mb), reg_mcr); 416 417 stats->tx_bytes += cf->can_dlc; 418 419 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 420 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST); 421 422 /* 423 * we have to stop the queue and deliver all messages in case 424 * of a prio+mb counter wrap around. This is the case if 425 * tx_next buffer prio and mailbox equals 0. 426 * 427 * also stop the queue if next buffer is still in use 428 * (== not ready) 429 */ 430 priv->tx_next++; 431 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 432 AT91_MSR_MRDY) || 433 (priv->tx_next & AT91_NEXT_MASK) == 0) 434 netif_stop_queue(dev); 435 436 /* Enable interrupt for this mailbox */ 437 at91_write(priv, AT91_IER, 1 << mb); 438 439 return NETDEV_TX_OK; 440} 441 442/** 443 * at91_activate_rx_low - activate lower rx mailboxes 444 * @priv: a91 context 445 * 446 * Reenables the lower mailboxes for reception of new CAN messages 447 */ 448static inline void at91_activate_rx_low(const struct at91_priv *priv) 449{ 450 u32 mask = AT91_MB_RX_LOW_MASK; 451 at91_write(priv, AT91_TCR, mask); 452} 453 454/** 455 * at91_activate_rx_mb - reactive single rx mailbox 456 * @priv: a91 context 457 * @mb: mailbox to reactivate 458 * 459 * Reenables given mailbox for reception of new CAN messages 460 */ 461static inline void at91_activate_rx_mb(const struct at91_priv *priv, 462 unsigned int mb) 463{ 464 u32 mask = 1 << mb; 465 at91_write(priv, AT91_TCR, mask); 466} 467 468/** 469 * at91_rx_overflow_err - send error frame due to rx overflow 470 * @dev: net device 471 */ 472static void at91_rx_overflow_err(struct net_device *dev) 473{ 474 struct net_device_stats *stats = &dev->stats; 475 struct sk_buff *skb; 476 struct can_frame *cf; 477 478 netdev_dbg(dev, "RX buffer overflow\n"); 479 stats->rx_over_errors++; 480 stats->rx_errors++; 481 482 skb = alloc_can_err_skb(dev, &cf); 483 if (unlikely(!skb)) 484 return; 485 486 cf->can_id |= CAN_ERR_CRTL; 487 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 488 netif_receive_skb(skb); 489 490 stats->rx_packets++; 491 stats->rx_bytes += cf->can_dlc; 492} 493 494/** 495 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 496 * @dev: net device 497 * @mb: mailbox number to read from 498 * @cf: can frame where to store message 499 * 500 * Reads a CAN message from the given mailbox and stores data into 501 * given can frame. "mb" and "cf" must be valid. 502 */ 503static void at91_read_mb(struct net_device *dev, unsigned int mb, 504 struct can_frame *cf) 505{ 506 const struct at91_priv *priv = netdev_priv(dev); 507 u32 reg_msr, reg_mid; 508 509 reg_mid = at91_read(priv, AT91_MID(mb)); 510 if (reg_mid & AT91_MID_MIDE) 511 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 512 else 513 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 514 515 reg_msr = at91_read(priv, AT91_MSR(mb)); 516 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 517 518 if (reg_msr & AT91_MSR_MRTR) 519 cf->can_id |= CAN_RTR_FLAG; 520 else { 521 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 522 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 523 } 524 525 /* allow RX of extended frames */ 526 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 527 528 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI)) 529 at91_rx_overflow_err(dev); 530} 531 532/** 533 * at91_read_msg - read CAN message from mailbox 534 * @dev: net device 535 * @mb: mail box to read from 536 * 537 * Reads a CAN message from given mailbox, and put into linux network 538 * RX queue, does all housekeeping chores (stats, ...) 539 */ 540static void at91_read_msg(struct net_device *dev, unsigned int mb) 541{ 542 struct net_device_stats *stats = &dev->stats; 543 struct can_frame *cf; 544 struct sk_buff *skb; 545 546 skb = alloc_can_skb(dev, &cf); 547 if (unlikely(!skb)) { 548 stats->rx_dropped++; 549 return; 550 } 551 552 at91_read_mb(dev, mb, cf); 553 netif_receive_skb(skb); 554 555 stats->rx_packets++; 556 stats->rx_bytes += cf->can_dlc; 557} 558 559/** 560 * at91_poll_rx - read multiple CAN messages from mailboxes 561 * @dev: net device 562 * @quota: max number of pkgs we're allowed to receive 563 * 564 * Theory of Operation: 565 * 566 * 11 of the 16 mailboxes on the chip are reserved for RX. we split 567 * them into 2 groups. The lower group holds 7 and upper 4 mailboxes. 568 * 569 * Like it or not, but the chip always saves a received CAN message 570 * into the first free mailbox it finds (starting with the 571 * lowest). This makes it very difficult to read the messages in the 572 * right order from the chip. This is how we work around that problem: 573 * 574 * The first message goes into mb nr. 1 and issues an interrupt. All 575 * rx ints are disabled in the interrupt handler and a napi poll is 576 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 577 * receive another message). 578 * 579 * lower mbxs upper 580 * ____^______ __^__ 581 * / \ / \ 582 * +-+-+-+-+-+-+-+-++-+-+-+-+ 583 * | |x|x|x|x|x|x|x|| | | | | 584 * +-+-+-+-+-+-+-+-++-+-+-+-+ 585 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 586 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 587 * ^ 588 * | 589 * \ 590 * unused, due to chip bug 591 * 592 * The variable priv->rx_next points to the next mailbox to read a 593 * message from. As long we're in the lower mailboxes we just read the 594 * mailbox but not reenable it. 595 * 596 * With completion of the last of the lower mailboxes, we reenable the 597 * whole first group, but continue to look for filled mailboxes in the 598 * upper mailboxes. Imagine the second group like overflow mailboxes, 599 * which takes CAN messages if the lower goup is full. While in the 600 * upper group we reenable the mailbox right after reading it. Giving 601 * the chip more room to store messages. 602 * 603 * After finishing we look again in the lower group if we've still 604 * quota. 605 * 606 */ 607static int at91_poll_rx(struct net_device *dev, int quota) 608{ 609 struct at91_priv *priv = netdev_priv(dev); 610 u32 reg_sr = at91_read(priv, AT91_SR); 611 const unsigned long *addr = (unsigned long *)®_sr; 612 unsigned int mb; 613 int received = 0; 614 615 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 616 reg_sr & AT91_MB_RX_LOW_MASK) 617 netdev_info(dev, 618 "order of incoming frames cannot be guaranteed\n"); 619 620 again: 621 for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next); 622 mb < AT91_MB_RX_LAST + 1 && quota > 0; 623 reg_sr = at91_read(priv, AT91_SR), 624 mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) { 625 at91_read_msg(dev, mb); 626 627 /* reactivate mailboxes */ 628 if (mb == AT91_MB_RX_LOW_LAST) 629 /* all lower mailboxed, if just finished it */ 630 at91_activate_rx_low(priv); 631 else if (mb > AT91_MB_RX_LOW_LAST) 632 /* only the mailbox we read */ 633 at91_activate_rx_mb(priv, mb); 634 635 received++; 636 quota--; 637 } 638 639 /* upper group completed, look again in lower */ 640 if (priv->rx_next > AT91_MB_RX_LOW_LAST && 641 quota > 0 && mb > AT91_MB_RX_LAST) { 642 priv->rx_next = AT91_MB_RX_FIRST; 643 goto again; 644 } 645 646 return received; 647} 648 649static void at91_poll_err_frame(struct net_device *dev, 650 struct can_frame *cf, u32 reg_sr) 651{ 652 struct at91_priv *priv = netdev_priv(dev); 653 654 /* CRC error */ 655 if (reg_sr & AT91_IRQ_CERR) { 656 netdev_dbg(dev, "CERR irq\n"); 657 dev->stats.rx_errors++; 658 priv->can.can_stats.bus_error++; 659 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 660 } 661 662 /* Stuffing Error */ 663 if (reg_sr & AT91_IRQ_SERR) { 664 netdev_dbg(dev, "SERR irq\n"); 665 dev->stats.rx_errors++; 666 priv->can.can_stats.bus_error++; 667 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 668 cf->data[2] |= CAN_ERR_PROT_STUFF; 669 } 670 671 /* Acknowledgement Error */ 672 if (reg_sr & AT91_IRQ_AERR) { 673 netdev_dbg(dev, "AERR irq\n"); 674 dev->stats.tx_errors++; 675 cf->can_id |= CAN_ERR_ACK; 676 } 677 678 /* Form error */ 679 if (reg_sr & AT91_IRQ_FERR) { 680 netdev_dbg(dev, "FERR irq\n"); 681 dev->stats.rx_errors++; 682 priv->can.can_stats.bus_error++; 683 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 684 cf->data[2] |= CAN_ERR_PROT_FORM; 685 } 686 687 /* Bit Error */ 688 if (reg_sr & AT91_IRQ_BERR) { 689 netdev_dbg(dev, "BERR irq\n"); 690 dev->stats.tx_errors++; 691 priv->can.can_stats.bus_error++; 692 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 693 cf->data[2] |= CAN_ERR_PROT_BIT; 694 } 695} 696 697static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 698{ 699 struct sk_buff *skb; 700 struct can_frame *cf; 701 702 if (quota == 0) 703 return 0; 704 705 skb = alloc_can_err_skb(dev, &cf); 706 if (unlikely(!skb)) 707 return 0; 708 709 at91_poll_err_frame(dev, cf, reg_sr); 710 netif_receive_skb(skb); 711 712 dev->stats.rx_packets++; 713 dev->stats.rx_bytes += cf->can_dlc; 714 715 return 1; 716} 717 718static int at91_poll(struct napi_struct *napi, int quota) 719{ 720 struct net_device *dev = napi->dev; 721 const struct at91_priv *priv = netdev_priv(dev); 722 u32 reg_sr = at91_read(priv, AT91_SR); 723 int work_done = 0; 724 725 if (reg_sr & AT91_IRQ_MB_RX) 726 work_done += at91_poll_rx(dev, quota - work_done); 727 728 /* 729 * The error bits are clear on read, 730 * so use saved value from irq handler. 731 */ 732 reg_sr |= priv->reg_sr; 733 if (reg_sr & AT91_IRQ_ERR_FRAME) 734 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 735 736 if (work_done < quota) { 737 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 738 u32 reg_ier = AT91_IRQ_ERR_FRAME; 739 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next); 740 741 napi_complete(napi); 742 at91_write(priv, AT91_IER, reg_ier); 743 } 744 745 return work_done; 746} 747 748/* 749 * theory of operation: 750 * 751 * priv->tx_echo holds the number of the oldest can_frame put for 752 * transmission into the hardware, but not yet ACKed by the CAN tx 753 * complete IRQ. 754 * 755 * We iterate from priv->tx_echo to priv->tx_next and check if the 756 * packet has been transmitted, echo it back to the CAN framework. If 757 * we discover a not yet transmitted package, stop looking for more. 758 * 759 */ 760static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 761{ 762 struct at91_priv *priv = netdev_priv(dev); 763 u32 reg_msr; 764 unsigned int mb; 765 766 /* masking of reg_sr not needed, already done by at91_irq */ 767 768 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 769 mb = get_tx_echo_mb(priv); 770 771 /* no event in mailbox? */ 772 if (!(reg_sr & (1 << mb))) 773 break; 774 775 /* Disable irq for this TX mailbox */ 776 at91_write(priv, AT91_IDR, 1 << mb); 777 778 /* 779 * only echo if mailbox signals us a transfer 780 * complete (MSR_MRDY). Otherwise it's a tansfer 781 * abort. "can_bus_off()" takes care about the skbs 782 * parked in the echo queue. 783 */ 784 reg_msr = at91_read(priv, AT91_MSR(mb)); 785 if (likely(reg_msr & AT91_MSR_MRDY && 786 ~reg_msr & AT91_MSR_MABT)) { 787 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 788 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST); 789 dev->stats.tx_packets++; 790 } 791 } 792 793 /* 794 * restart queue if we don't have a wrap around but restart if 795 * we get a TX int for the last can frame directly before a 796 * wrap around. 797 */ 798 if ((priv->tx_next & AT91_NEXT_MASK) != 0 || 799 (priv->tx_echo & AT91_NEXT_MASK) == 0) 800 netif_wake_queue(dev); 801} 802 803static void at91_irq_err_state(struct net_device *dev, 804 struct can_frame *cf, enum can_state new_state) 805{ 806 struct at91_priv *priv = netdev_priv(dev); 807 u32 reg_idr = 0, reg_ier = 0; 808 struct can_berr_counter bec; 809 810 at91_get_berr_counter(dev, &bec); 811 812 switch (priv->can.state) { 813 case CAN_STATE_ERROR_ACTIVE: 814 /* 815 * from: ERROR_ACTIVE 816 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 817 * => : there was a warning int 818 */ 819 if (new_state >= CAN_STATE_ERROR_WARNING && 820 new_state <= CAN_STATE_BUS_OFF) { 821 netdev_dbg(dev, "Error Warning IRQ\n"); 822 priv->can.can_stats.error_warning++; 823 824 cf->can_id |= CAN_ERR_CRTL; 825 cf->data[1] = (bec.txerr > bec.rxerr) ? 826 CAN_ERR_CRTL_TX_WARNING : 827 CAN_ERR_CRTL_RX_WARNING; 828 } 829 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 830 /* 831 * from: ERROR_ACTIVE, ERROR_WARNING 832 * to : ERROR_PASSIVE, BUS_OFF 833 * => : error passive int 834 */ 835 if (new_state >= CAN_STATE_ERROR_PASSIVE && 836 new_state <= CAN_STATE_BUS_OFF) { 837 netdev_dbg(dev, "Error Passive IRQ\n"); 838 priv->can.can_stats.error_passive++; 839 840 cf->can_id |= CAN_ERR_CRTL; 841 cf->data[1] = (bec.txerr > bec.rxerr) ? 842 CAN_ERR_CRTL_TX_PASSIVE : 843 CAN_ERR_CRTL_RX_PASSIVE; 844 } 845 break; 846 case CAN_STATE_BUS_OFF: 847 /* 848 * from: BUS_OFF 849 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 850 */ 851 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 852 cf->can_id |= CAN_ERR_RESTARTED; 853 854 netdev_dbg(dev, "restarted\n"); 855 priv->can.can_stats.restarts++; 856 857 netif_carrier_on(dev); 858 netif_wake_queue(dev); 859 } 860 break; 861 default: 862 break; 863 } 864 865 866 /* process state changes depending on the new state */ 867 switch (new_state) { 868 case CAN_STATE_ERROR_ACTIVE: 869 /* 870 * actually we want to enable AT91_IRQ_WARN here, but 871 * it screws up the system under certain 872 * circumstances. so just enable AT91_IRQ_ERRP, thus 873 * the "fallthrough" 874 */ 875 netdev_dbg(dev, "Error Active\n"); 876 cf->can_id |= CAN_ERR_PROT; 877 cf->data[2] = CAN_ERR_PROT_ACTIVE; 878 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 879 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 880 reg_ier = AT91_IRQ_ERRP; 881 break; 882 case CAN_STATE_ERROR_PASSIVE: 883 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 884 reg_ier = AT91_IRQ_BOFF; 885 break; 886 case CAN_STATE_BUS_OFF: 887 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 888 AT91_IRQ_WARN | AT91_IRQ_BOFF; 889 reg_ier = 0; 890 891 cf->can_id |= CAN_ERR_BUSOFF; 892 893 netdev_dbg(dev, "bus-off\n"); 894 netif_carrier_off(dev); 895 priv->can.can_stats.bus_off++; 896 897 /* turn off chip, if restart is disabled */ 898 if (!priv->can.restart_ms) { 899 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 900 return; 901 } 902 break; 903 default: 904 break; 905 } 906 907 at91_write(priv, AT91_IDR, reg_idr); 908 at91_write(priv, AT91_IER, reg_ier); 909} 910 911static void at91_irq_err(struct net_device *dev) 912{ 913 struct at91_priv *priv = netdev_priv(dev); 914 struct sk_buff *skb; 915 struct can_frame *cf; 916 enum can_state new_state; 917 u32 reg_sr; 918 919 reg_sr = at91_read(priv, AT91_SR); 920 921 /* we need to look at the unmasked reg_sr */ 922 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 923 new_state = CAN_STATE_BUS_OFF; 924 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 925 new_state = CAN_STATE_ERROR_PASSIVE; 926 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 927 new_state = CAN_STATE_ERROR_WARNING; 928 else if (likely(reg_sr & AT91_IRQ_ERRA)) 929 new_state = CAN_STATE_ERROR_ACTIVE; 930 else { 931 netdev_err(dev, "BUG! hardware in undefined state\n"); 932 return; 933 } 934 935 /* state hasn't changed */ 936 if (likely(new_state == priv->can.state)) 937 return; 938 939 skb = alloc_can_err_skb(dev, &cf); 940 if (unlikely(!skb)) 941 return; 942 943 at91_irq_err_state(dev, cf, new_state); 944 netif_rx(skb); 945 946 dev->stats.rx_packets++; 947 dev->stats.rx_bytes += cf->can_dlc; 948 949 priv->can.state = new_state; 950} 951 952/* 953 * interrupt handler 954 */ 955static irqreturn_t at91_irq(int irq, void *dev_id) 956{ 957 struct net_device *dev = dev_id; 958 struct at91_priv *priv = netdev_priv(dev); 959 irqreturn_t handled = IRQ_NONE; 960 u32 reg_sr, reg_imr; 961 962 reg_sr = at91_read(priv, AT91_SR); 963 reg_imr = at91_read(priv, AT91_IMR); 964 965 /* Ignore masked interrupts */ 966 reg_sr &= reg_imr; 967 if (!reg_sr) 968 goto exit; 969 970 handled = IRQ_HANDLED; 971 972 /* Receive or error interrupt? -> napi */ 973 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) { 974 /* 975 * The error bits are clear on read, 976 * save for later use. 977 */ 978 priv->reg_sr = reg_sr; 979 at91_write(priv, AT91_IDR, 980 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME); 981 napi_schedule(&priv->napi); 982 } 983 984 /* Transmission complete interrupt */ 985 if (reg_sr & AT91_IRQ_MB_TX) 986 at91_irq_tx(dev, reg_sr); 987 988 at91_irq_err(dev); 989 990 exit: 991 return handled; 992} 993 994static int at91_open(struct net_device *dev) 995{ 996 struct at91_priv *priv = netdev_priv(dev); 997 int err; 998 999 clk_enable(priv->clk); 1000 1001 /* check or determine and set bittime */ 1002 err = open_candev(dev); 1003 if (err) 1004 goto out; 1005 1006 /* register interrupt handler */ 1007 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1008 dev->name, dev)) { 1009 err = -EAGAIN; 1010 goto out_close; 1011 } 1012 1013 /* start chip and queuing */ 1014 at91_chip_start(dev); 1015 napi_enable(&priv->napi); 1016 netif_start_queue(dev); 1017 1018 return 0; 1019 1020 out_close: 1021 close_candev(dev); 1022 out: 1023 clk_disable(priv->clk); 1024 1025 return err; 1026} 1027 1028/* 1029 * stop CAN bus activity 1030 */ 1031static int at91_close(struct net_device *dev) 1032{ 1033 struct at91_priv *priv = netdev_priv(dev); 1034 1035 netif_stop_queue(dev); 1036 napi_disable(&priv->napi); 1037 at91_chip_stop(dev, CAN_STATE_STOPPED); 1038 1039 free_irq(dev->irq, dev); 1040 clk_disable(priv->clk); 1041 1042 close_candev(dev); 1043 1044 return 0; 1045} 1046 1047static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1048{ 1049 switch (mode) { 1050 case CAN_MODE_START: 1051 at91_chip_start(dev); 1052 netif_wake_queue(dev); 1053 break; 1054 1055 default: 1056 return -EOPNOTSUPP; 1057 } 1058 1059 return 0; 1060} 1061 1062static const struct net_device_ops at91_netdev_ops = { 1063 .ndo_open = at91_open, 1064 .ndo_stop = at91_close, 1065 .ndo_start_xmit = at91_start_xmit, 1066}; 1067 1068static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1069 struct device_attribute *attr, char *buf) 1070{ 1071 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1072 1073 if (priv->mb0_id & CAN_EFF_FLAG) 1074 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1075 else 1076 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1077} 1078 1079static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1080 struct device_attribute *attr, const char *buf, size_t count) 1081{ 1082 struct net_device *ndev = to_net_dev(dev); 1083 struct at91_priv *priv = netdev_priv(ndev); 1084 unsigned long can_id; 1085 ssize_t ret; 1086 int err; 1087 1088 rtnl_lock(); 1089 1090 if (ndev->flags & IFF_UP) { 1091 ret = -EBUSY; 1092 goto out; 1093 } 1094 1095 err = strict_strtoul(buf, 0, &can_id); 1096 if (err) { 1097 ret = err; 1098 goto out; 1099 } 1100 1101 if (can_id & CAN_EFF_FLAG) 1102 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1103 else 1104 can_id &= CAN_SFF_MASK; 1105 1106 priv->mb0_id = can_id; 1107 ret = count; 1108 1109 out: 1110 rtnl_unlock(); 1111 return ret; 1112} 1113 1114static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1115 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1116 1117static struct attribute *at91_sysfs_attrs[] = { 1118 &dev_attr_mb0_id.attr, 1119 NULL, 1120}; 1121 1122static struct attribute_group at91_sysfs_attr_group = { 1123 .attrs = at91_sysfs_attrs, 1124}; 1125 1126static int __devinit at91_can_probe(struct platform_device *pdev) 1127{ 1128 struct net_device *dev; 1129 struct at91_priv *priv; 1130 struct resource *res; 1131 struct clk *clk; 1132 void __iomem *addr; 1133 int err, irq; 1134 1135 clk = clk_get(&pdev->dev, "can_clk"); 1136 if (IS_ERR(clk)) { 1137 dev_err(&pdev->dev, "no clock defined\n"); 1138 err = -ENODEV; 1139 goto exit; 1140 } 1141 1142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1143 irq = platform_get_irq(pdev, 0); 1144 if (!res || irq <= 0) { 1145 err = -ENODEV; 1146 goto exit_put; 1147 } 1148 1149 if (!request_mem_region(res->start, 1150 resource_size(res), 1151 pdev->name)) { 1152 err = -EBUSY; 1153 goto exit_put; 1154 } 1155 1156 addr = ioremap_nocache(res->start, resource_size(res)); 1157 if (!addr) { 1158 err = -ENOMEM; 1159 goto exit_release; 1160 } 1161 1162 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM); 1163 if (!dev) { 1164 err = -ENOMEM; 1165 goto exit_iounmap; 1166 } 1167 1168 dev->netdev_ops = &at91_netdev_ops; 1169 dev->irq = irq; 1170 dev->flags |= IFF_ECHO; 1171 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1172 1173 priv = netdev_priv(dev); 1174 priv->can.clock.freq = clk_get_rate(clk); 1175 priv->can.bittiming_const = &at91_bittiming_const; 1176 priv->can.do_set_mode = at91_set_mode; 1177 priv->can.do_get_berr_counter = at91_get_berr_counter; 1178 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1179 priv->reg_base = addr; 1180 priv->dev = dev; 1181 priv->clk = clk; 1182 priv->pdata = pdev->dev.platform_data; 1183 priv->mb0_id = 0x7ff; 1184 1185 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT); 1186 1187 dev_set_drvdata(&pdev->dev, dev); 1188 SET_NETDEV_DEV(dev, &pdev->dev); 1189 1190 err = register_candev(dev); 1191 if (err) { 1192 dev_err(&pdev->dev, "registering netdev failed\n"); 1193 goto exit_free; 1194 } 1195 1196 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1197 priv->reg_base, dev->irq); 1198 1199 return 0; 1200 1201 exit_free: 1202 free_candev(dev); 1203 exit_iounmap: 1204 iounmap(addr); 1205 exit_release: 1206 release_mem_region(res->start, resource_size(res)); 1207 exit_put: 1208 clk_put(clk); 1209 exit: 1210 return err; 1211} 1212 1213static int __devexit at91_can_remove(struct platform_device *pdev) 1214{ 1215 struct net_device *dev = platform_get_drvdata(pdev); 1216 struct at91_priv *priv = netdev_priv(dev); 1217 struct resource *res; 1218 1219 unregister_netdev(dev); 1220 1221 platform_set_drvdata(pdev, NULL); 1222 1223 iounmap(priv->reg_base); 1224 1225 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1226 release_mem_region(res->start, resource_size(res)); 1227 1228 clk_put(priv->clk); 1229 1230 free_candev(dev); 1231 1232 return 0; 1233} 1234 1235static struct platform_driver at91_can_driver = { 1236 .probe = at91_can_probe, 1237 .remove = __devexit_p(at91_can_remove), 1238 .driver = { 1239 .name = KBUILD_MODNAME, 1240 .owner = THIS_MODULE, 1241 }, 1242}; 1243 1244static int __init at91_can_module_init(void) 1245{ 1246 return platform_driver_register(&at91_can_driver); 1247} 1248 1249static void __exit at91_can_module_exit(void) 1250{ 1251 platform_driver_unregister(&at91_can_driver); 1252} 1253 1254module_init(at91_can_module_init); 1255module_exit(at91_can_module_exit); 1256 1257MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1258MODULE_LICENSE("GPL v2"); 1259MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1260