bfin_can.c revision 79d0d8a7d5edca459f544c2ad75088e99307795e
1/* 2 * Blackfin On-Chip CAN Driver 3 * 4 * Copyright 2004-2009 Analog Devices Inc. 5 * 6 * Enter bugs at http://blackfin.uclinux.org/ 7 * 8 * Licensed under the GPL-2 or later. 9 */ 10 11#include <linux/module.h> 12#include <linux/init.h> 13#include <linux/kernel.h> 14#include <linux/bitops.h> 15#include <linux/interrupt.h> 16#include <linux/errno.h> 17#include <linux/netdevice.h> 18#include <linux/skbuff.h> 19#include <linux/platform_device.h> 20 21#include <linux/can/dev.h> 22#include <linux/can/error.h> 23 24#include <asm/bfin_can.h> 25#include <asm/portmux.h> 26 27#define DRV_NAME "bfin_can" 28#define BFIN_CAN_TIMEOUT 100 29#define TX_ECHO_SKB_MAX 1 30 31/* 32 * bfin can private data 33 */ 34struct bfin_can_priv { 35 struct can_priv can; /* must be the first member */ 36 struct net_device *dev; 37 void __iomem *membase; 38 int rx_irq; 39 int tx_irq; 40 int err_irq; 41 unsigned short *pin_list; 42}; 43 44/* 45 * bfin can timing parameters 46 */ 47static struct can_bittiming_const bfin_can_bittiming_const = { 48 .name = DRV_NAME, 49 .tseg1_min = 1, 50 .tseg1_max = 16, 51 .tseg2_min = 1, 52 .tseg2_max = 8, 53 .sjw_max = 4, 54 /* 55 * Although the BRP field can be set to any value, it is recommended 56 * that the value be greater than or equal to 4, as restrictions 57 * apply to the bit timing configuration when BRP is less than 4. 58 */ 59 .brp_min = 4, 60 .brp_max = 1024, 61 .brp_inc = 1, 62}; 63 64static int bfin_can_set_bittiming(struct net_device *dev) 65{ 66 struct bfin_can_priv *priv = netdev_priv(dev); 67 struct bfin_can_regs __iomem *reg = priv->membase; 68 struct can_bittiming *bt = &priv->can.bittiming; 69 u16 clk, timing; 70 71 clk = bt->brp - 1; 72 timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) | 73 ((bt->phase_seg2 - 1) << 4); 74 75 /* 76 * If the SAM bit is set, the input signal is oversampled three times 77 * at the SCLK rate. 78 */ 79 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 80 timing |= SAM; 81 82 bfin_write(®->clock, clk); 83 bfin_write(®->timing, timing); 84 85 dev_info(dev->dev.parent, "setting CLOCK=0x%04x TIMING=0x%04x\n", 86 clk, timing); 87 88 return 0; 89} 90 91static void bfin_can_set_reset_mode(struct net_device *dev) 92{ 93 struct bfin_can_priv *priv = netdev_priv(dev); 94 struct bfin_can_regs __iomem *reg = priv->membase; 95 int timeout = BFIN_CAN_TIMEOUT; 96 int i; 97 98 /* disable interrupts */ 99 bfin_write(®->mbim1, 0); 100 bfin_write(®->mbim2, 0); 101 bfin_write(®->gim, 0); 102 103 /* reset can and enter configuration mode */ 104 bfin_write(®->control, SRS | CCR); 105 SSYNC(); 106 bfin_write(®->control, CCR); 107 SSYNC(); 108 while (!(bfin_read(®->control) & CCA)) { 109 udelay(10); 110 if (--timeout == 0) { 111 dev_err(dev->dev.parent, 112 "fail to enter configuration mode\n"); 113 BUG(); 114 } 115 } 116 117 /* 118 * All mailbox configurations are marked as inactive 119 * by writing to CAN Mailbox Configuration Registers 1 and 2 120 * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled 121 */ 122 bfin_write(®->mc1, 0); 123 bfin_write(®->mc2, 0); 124 125 /* Set Mailbox Direction */ 126 bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */ 127 bfin_write(®->md2, 0); /* mailbox 17-32 are TX */ 128 129 /* RECEIVE_STD_CHL */ 130 for (i = 0; i < 2; i++) { 131 bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0); 132 bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME); 133 bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0); 134 bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF); 135 bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF); 136 } 137 138 /* RECEIVE_EXT_CHL */ 139 for (i = 0; i < 2; i++) { 140 bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0); 141 bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE); 142 bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0); 143 bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF); 144 bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF); 145 } 146 147 bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16)); 148 bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); 149 SSYNC(); 150 151 priv->can.state = CAN_STATE_STOPPED; 152} 153 154static void bfin_can_set_normal_mode(struct net_device *dev) 155{ 156 struct bfin_can_priv *priv = netdev_priv(dev); 157 struct bfin_can_regs __iomem *reg = priv->membase; 158 int timeout = BFIN_CAN_TIMEOUT; 159 160 /* 161 * leave configuration mode 162 */ 163 bfin_write(®->control, bfin_read(®->control) & ~CCR); 164 165 while (bfin_read(®->status) & CCA) { 166 udelay(10); 167 if (--timeout == 0) { 168 dev_err(dev->dev.parent, 169 "fail to leave configuration mode\n"); 170 BUG(); 171 } 172 } 173 174 /* 175 * clear _All_ tx and rx interrupts 176 */ 177 bfin_write(®->mbtif1, 0xFFFF); 178 bfin_write(®->mbtif2, 0xFFFF); 179 bfin_write(®->mbrif1, 0xFFFF); 180 bfin_write(®->mbrif2, 0xFFFF); 181 182 /* 183 * clear global interrupt status register 184 */ 185 bfin_write(®->gis, 0x7FF); /* overwrites with '1' */ 186 187 /* 188 * Initialize Interrupts 189 * - set bits in the mailbox interrupt mask register 190 * - global interrupt mask 191 */ 192 bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL)); 193 bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16)); 194 195 bfin_write(®->gim, EPIM | BOIM | RMLIM); 196 SSYNC(); 197} 198 199static void bfin_can_start(struct net_device *dev) 200{ 201 struct bfin_can_priv *priv = netdev_priv(dev); 202 203 /* enter reset mode */ 204 if (priv->can.state != CAN_STATE_STOPPED) 205 bfin_can_set_reset_mode(dev); 206 207 /* leave reset mode */ 208 bfin_can_set_normal_mode(dev); 209} 210 211static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode) 212{ 213 switch (mode) { 214 case CAN_MODE_START: 215 bfin_can_start(dev); 216 if (netif_queue_stopped(dev)) 217 netif_wake_queue(dev); 218 break; 219 220 default: 221 return -EOPNOTSUPP; 222 } 223 224 return 0; 225} 226 227static int bfin_can_get_berr_counter(const struct net_device *dev, 228 struct can_berr_counter *bec) 229{ 230 struct bfin_can_priv *priv = netdev_priv(dev); 231 struct bfin_can_regs __iomem *reg = priv->membase; 232 233 u16 cec = bfin_read(®->cec); 234 235 bec->txerr = cec >> 8; 236 bec->rxerr = cec; 237 238 return 0; 239} 240 241static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev) 242{ 243 struct bfin_can_priv *priv = netdev_priv(dev); 244 struct bfin_can_regs __iomem *reg = priv->membase; 245 struct can_frame *cf = (struct can_frame *)skb->data; 246 u8 dlc = cf->can_dlc; 247 canid_t id = cf->can_id; 248 u8 *data = cf->data; 249 u16 val; 250 int i; 251 252 if (can_dropped_invalid_skb(dev, skb)) 253 return NETDEV_TX_OK; 254 255 netif_stop_queue(dev); 256 257 /* fill id */ 258 if (id & CAN_EFF_FLAG) { 259 bfin_write(®->chl[TRANSMIT_CHL].id0, id); 260 val = ((id & 0x1FFF0000) >> 16) | IDE; 261 } else 262 val = (id << 2); 263 if (id & CAN_RTR_FLAG) 264 val |= RTR; 265 bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME); 266 267 /* fill payload */ 268 for (i = 0; i < 8; i += 2) { 269 val = ((7 - i) < dlc ? (data[7 - i]) : 0) + 270 ((6 - i) < dlc ? (data[6 - i] << 8) : 0); 271 bfin_write(®->chl[TRANSMIT_CHL].data[i], val); 272 } 273 274 /* fill data length code */ 275 bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc); 276 277 can_put_echo_skb(skb, dev, 0); 278 279 /* set transmit request */ 280 bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16)); 281 282 return 0; 283} 284 285static void bfin_can_rx(struct net_device *dev, u16 isrc) 286{ 287 struct bfin_can_priv *priv = netdev_priv(dev); 288 struct net_device_stats *stats = &dev->stats; 289 struct bfin_can_regs __iomem *reg = priv->membase; 290 struct can_frame *cf; 291 struct sk_buff *skb; 292 int obj; 293 int i; 294 u16 val; 295 296 skb = alloc_can_skb(dev, &cf); 297 if (skb == NULL) 298 return; 299 300 /* get id */ 301 if (isrc & BIT(RECEIVE_EXT_CHL)) { 302 /* extended frame format (EFF) */ 303 cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1) 304 & 0x1FFF) << 16) 305 + bfin_read(®->chl[RECEIVE_EXT_CHL].id0); 306 cf->can_id |= CAN_EFF_FLAG; 307 obj = RECEIVE_EXT_CHL; 308 } else { 309 /* standard frame format (SFF) */ 310 cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1) 311 & 0x1ffc) >> 2; 312 obj = RECEIVE_STD_CHL; 313 } 314 if (bfin_read(®->chl[obj].id1) & RTR) 315 cf->can_id |= CAN_RTR_FLAG; 316 317 /* get data length code */ 318 cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF); 319 320 /* get payload */ 321 for (i = 0; i < 8; i += 2) { 322 val = bfin_read(®->chl[obj].data[i]); 323 cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0; 324 cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0; 325 } 326 327 netif_rx(skb); 328 329 stats->rx_packets++; 330 stats->rx_bytes += cf->can_dlc; 331} 332 333static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status) 334{ 335 struct bfin_can_priv *priv = netdev_priv(dev); 336 struct bfin_can_regs __iomem *reg = priv->membase; 337 struct net_device_stats *stats = &dev->stats; 338 struct can_frame *cf; 339 struct sk_buff *skb; 340 enum can_state state = priv->can.state; 341 342 skb = alloc_can_err_skb(dev, &cf); 343 if (skb == NULL) 344 return -ENOMEM; 345 346 if (isrc & RMLIS) { 347 /* data overrun interrupt */ 348 dev_dbg(dev->dev.parent, "data overrun interrupt\n"); 349 cf->can_id |= CAN_ERR_CRTL; 350 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 351 stats->rx_over_errors++; 352 stats->rx_errors++; 353 } 354 355 if (isrc & BOIS) { 356 dev_dbg(dev->dev.parent, "bus-off mode interrupt\n"); 357 state = CAN_STATE_BUS_OFF; 358 cf->can_id |= CAN_ERR_BUSOFF; 359 can_bus_off(dev); 360 } 361 362 if (isrc & EPIS) { 363 /* error passive interrupt */ 364 dev_dbg(dev->dev.parent, "error passive interrupt\n"); 365 state = CAN_STATE_ERROR_PASSIVE; 366 } 367 368 if ((isrc & EWTIS) || (isrc & EWRIS)) { 369 dev_dbg(dev->dev.parent, 370 "Error Warning Transmit/Receive Interrupt\n"); 371 state = CAN_STATE_ERROR_WARNING; 372 } 373 374 if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING || 375 state == CAN_STATE_ERROR_PASSIVE)) { 376 u16 cec = bfin_read(®->cec); 377 u8 rxerr = cec; 378 u8 txerr = cec >> 8; 379 380 cf->can_id |= CAN_ERR_CRTL; 381 if (state == CAN_STATE_ERROR_WARNING) { 382 priv->can.can_stats.error_warning++; 383 cf->data[1] = (txerr > rxerr) ? 384 CAN_ERR_CRTL_TX_WARNING : 385 CAN_ERR_CRTL_RX_WARNING; 386 } else { 387 priv->can.can_stats.error_passive++; 388 cf->data[1] = (txerr > rxerr) ? 389 CAN_ERR_CRTL_TX_PASSIVE : 390 CAN_ERR_CRTL_RX_PASSIVE; 391 } 392 } 393 394 if (status) { 395 priv->can.can_stats.bus_error++; 396 397 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 398 399 if (status & BEF) 400 cf->data[2] |= CAN_ERR_PROT_BIT; 401 else if (status & FER) 402 cf->data[2] |= CAN_ERR_PROT_FORM; 403 else if (status & SER) 404 cf->data[2] |= CAN_ERR_PROT_STUFF; 405 else 406 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 407 } 408 409 priv->can.state = state; 410 411 netif_rx(skb); 412 413 stats->rx_packets++; 414 stats->rx_bytes += cf->can_dlc; 415 416 return 0; 417} 418 419irqreturn_t bfin_can_interrupt(int irq, void *dev_id) 420{ 421 struct net_device *dev = dev_id; 422 struct bfin_can_priv *priv = netdev_priv(dev); 423 struct bfin_can_regs __iomem *reg = priv->membase; 424 struct net_device_stats *stats = &dev->stats; 425 u16 status, isrc; 426 427 if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) { 428 /* transmission complete interrupt */ 429 bfin_write(®->mbtif2, 0xFFFF); 430 stats->tx_packets++; 431 stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc); 432 can_get_echo_skb(dev, 0); 433 netif_wake_queue(dev); 434 } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) { 435 /* receive interrupt */ 436 isrc = bfin_read(®->mbrif1); 437 bfin_write(®->mbrif1, 0xFFFF); 438 bfin_can_rx(dev, isrc); 439 } else if ((irq == priv->err_irq) && bfin_read(®->gis)) { 440 /* error interrupt */ 441 isrc = bfin_read(®->gis); 442 status = bfin_read(®->esr); 443 bfin_write(®->gis, 0x7FF); 444 bfin_can_err(dev, isrc, status); 445 } else { 446 return IRQ_NONE; 447 } 448 449 return IRQ_HANDLED; 450} 451 452static int bfin_can_open(struct net_device *dev) 453{ 454 struct bfin_can_priv *priv = netdev_priv(dev); 455 int err; 456 457 /* set chip into reset mode */ 458 bfin_can_set_reset_mode(dev); 459 460 /* common open */ 461 err = open_candev(dev); 462 if (err) 463 goto exit_open; 464 465 /* register interrupt handler */ 466 err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0, 467 "bfin-can-rx", dev); 468 if (err) 469 goto exit_rx_irq; 470 err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0, 471 "bfin-can-tx", dev); 472 if (err) 473 goto exit_tx_irq; 474 err = request_irq(priv->err_irq, &bfin_can_interrupt, 0, 475 "bfin-can-err", dev); 476 if (err) 477 goto exit_err_irq; 478 479 bfin_can_start(dev); 480 481 netif_start_queue(dev); 482 483 return 0; 484 485exit_err_irq: 486 free_irq(priv->tx_irq, dev); 487exit_tx_irq: 488 free_irq(priv->rx_irq, dev); 489exit_rx_irq: 490 close_candev(dev); 491exit_open: 492 return err; 493} 494 495static int bfin_can_close(struct net_device *dev) 496{ 497 struct bfin_can_priv *priv = netdev_priv(dev); 498 499 netif_stop_queue(dev); 500 bfin_can_set_reset_mode(dev); 501 502 close_candev(dev); 503 504 free_irq(priv->rx_irq, dev); 505 free_irq(priv->tx_irq, dev); 506 free_irq(priv->err_irq, dev); 507 508 return 0; 509} 510 511struct net_device *alloc_bfin_candev(void) 512{ 513 struct net_device *dev; 514 struct bfin_can_priv *priv; 515 516 dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX); 517 if (!dev) 518 return NULL; 519 520 priv = netdev_priv(dev); 521 522 priv->dev = dev; 523 priv->can.bittiming_const = &bfin_can_bittiming_const; 524 priv->can.do_set_bittiming = bfin_can_set_bittiming; 525 priv->can.do_set_mode = bfin_can_set_mode; 526 priv->can.do_get_berr_counter = bfin_can_get_berr_counter; 527 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 528 529 return dev; 530} 531 532static const struct net_device_ops bfin_can_netdev_ops = { 533 .ndo_open = bfin_can_open, 534 .ndo_stop = bfin_can_close, 535 .ndo_start_xmit = bfin_can_start_xmit, 536}; 537 538static int __devinit bfin_can_probe(struct platform_device *pdev) 539{ 540 int err; 541 struct net_device *dev; 542 struct bfin_can_priv *priv; 543 struct resource *res_mem, *rx_irq, *tx_irq, *err_irq; 544 unsigned short *pdata; 545 546 pdata = pdev->dev.platform_data; 547 if (!pdata) { 548 dev_err(&pdev->dev, "No platform data provided!\n"); 549 err = -EINVAL; 550 goto exit; 551 } 552 553 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 554 rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 555 tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 556 err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2); 557 if (!res_mem || !rx_irq || !tx_irq || !err_irq) { 558 err = -EINVAL; 559 goto exit; 560 } 561 562 if (!request_mem_region(res_mem->start, resource_size(res_mem), 563 dev_name(&pdev->dev))) { 564 err = -EBUSY; 565 goto exit; 566 } 567 568 /* request peripheral pins */ 569 err = peripheral_request_list(pdata, dev_name(&pdev->dev)); 570 if (err) 571 goto exit_mem_release; 572 573 dev = alloc_bfin_candev(); 574 if (!dev) { 575 err = -ENOMEM; 576 goto exit_peri_pin_free; 577 } 578 579 priv = netdev_priv(dev); 580 priv->membase = (void __iomem *)res_mem->start; 581 priv->rx_irq = rx_irq->start; 582 priv->tx_irq = tx_irq->start; 583 priv->err_irq = err_irq->start; 584 priv->pin_list = pdata; 585 priv->can.clock.freq = get_sclk(); 586 587 dev_set_drvdata(&pdev->dev, dev); 588 SET_NETDEV_DEV(dev, &pdev->dev); 589 590 dev->flags |= IFF_ECHO; /* we support local echo */ 591 dev->netdev_ops = &bfin_can_netdev_ops; 592 593 bfin_can_set_reset_mode(dev); 594 595 err = register_candev(dev); 596 if (err) { 597 dev_err(&pdev->dev, "registering failed (err=%d)\n", err); 598 goto exit_candev_free; 599 } 600 601 dev_info(&pdev->dev, 602 "%s device registered" 603 "(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n", 604 DRV_NAME, (void *)priv->membase, priv->rx_irq, 605 priv->tx_irq, priv->err_irq, priv->can.clock.freq); 606 return 0; 607 608exit_candev_free: 609 free_candev(dev); 610exit_peri_pin_free: 611 peripheral_free_list(pdata); 612exit_mem_release: 613 release_mem_region(res_mem->start, resource_size(res_mem)); 614exit: 615 return err; 616} 617 618static int __devexit bfin_can_remove(struct platform_device *pdev) 619{ 620 struct net_device *dev = dev_get_drvdata(&pdev->dev); 621 struct bfin_can_priv *priv = netdev_priv(dev); 622 struct resource *res; 623 624 bfin_can_set_reset_mode(dev); 625 626 unregister_candev(dev); 627 628 dev_set_drvdata(&pdev->dev, NULL); 629 630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 631 release_mem_region(res->start, resource_size(res)); 632 633 peripheral_free_list(priv->pin_list); 634 635 free_candev(dev); 636 return 0; 637} 638 639#ifdef CONFIG_PM 640static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg) 641{ 642 struct net_device *dev = dev_get_drvdata(&pdev->dev); 643 struct bfin_can_priv *priv = netdev_priv(dev); 644 struct bfin_can_regs __iomem *reg = priv->membase; 645 int timeout = BFIN_CAN_TIMEOUT; 646 647 if (netif_running(dev)) { 648 /* enter sleep mode */ 649 bfin_write(®->control, bfin_read(®->control) | SMR); 650 SSYNC(); 651 while (!(bfin_read(®->intr) & SMACK)) { 652 udelay(10); 653 if (--timeout == 0) { 654 dev_err(dev->dev.parent, 655 "fail to enter sleep mode\n"); 656 BUG(); 657 } 658 } 659 } 660 661 return 0; 662} 663 664static int bfin_can_resume(struct platform_device *pdev) 665{ 666 struct net_device *dev = dev_get_drvdata(&pdev->dev); 667 struct bfin_can_priv *priv = netdev_priv(dev); 668 struct bfin_can_regs __iomem *reg = priv->membase; 669 670 if (netif_running(dev)) { 671 /* leave sleep mode */ 672 bfin_write(®->intr, 0); 673 SSYNC(); 674 } 675 676 return 0; 677} 678#else 679#define bfin_can_suspend NULL 680#define bfin_can_resume NULL 681#endif /* CONFIG_PM */ 682 683static struct platform_driver bfin_can_driver = { 684 .probe = bfin_can_probe, 685 .remove = __devexit_p(bfin_can_remove), 686 .suspend = bfin_can_suspend, 687 .resume = bfin_can_resume, 688 .driver = { 689 .name = DRV_NAME, 690 .owner = THIS_MODULE, 691 }, 692}; 693 694module_platform_driver(bfin_can_driver); 695 696MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>"); 697MODULE_LICENSE("GPL"); 698MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver"); 699