c_can.c revision 097aec19689d8f2f76fd0c1becacf32801ae94c7
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* status interrupt */ 149#define STATUS_INTERRUPT 0x8000 150 151/* global interrupt masks */ 152#define ENABLE_ALL_INTERRUPTS 1 153#define DISABLE_ALL_INTERRUPTS 0 154 155/* minimum timeout for checking BUSY status */ 156#define MIN_TIMEOUT_VALUE 6 157 158/* Wait for ~1 sec for INIT bit */ 159#define INIT_WAIT_MS 1000 160 161/* napi related */ 162#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 163 164/* c_can lec values */ 165enum c_can_lec_type { 166 LEC_NO_ERROR = 0, 167 LEC_STUFF_ERROR, 168 LEC_FORM_ERROR, 169 LEC_ACK_ERROR, 170 LEC_BIT1_ERROR, 171 LEC_BIT0_ERROR, 172 LEC_CRC_ERROR, 173 LEC_UNUSED, 174 LEC_MASK = LEC_UNUSED, 175}; 176 177/* 178 * c_can error types: 179 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 180 */ 181enum c_can_bus_error_types { 182 C_CAN_NO_ERROR = 0, 183 C_CAN_BUS_OFF, 184 C_CAN_ERROR_WARNING, 185 C_CAN_ERROR_PASSIVE, 186}; 187 188static const struct can_bittiming_const c_can_bittiming_const = { 189 .name = KBUILD_MODNAME, 190 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 191 .tseg1_max = 16, 192 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 193 .tseg2_max = 8, 194 .sjw_max = 4, 195 .brp_min = 1, 196 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 197 .brp_inc = 1, 198}; 199 200static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 201{ 202 if (priv->device) 203 pm_runtime_enable(priv->device); 204} 205 206static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 207{ 208 if (priv->device) 209 pm_runtime_disable(priv->device); 210} 211 212static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 213{ 214 if (priv->device) 215 pm_runtime_get_sync(priv->device); 216} 217 218static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 219{ 220 if (priv->device) 221 pm_runtime_put_sync(priv->device); 222} 223 224static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 225{ 226 if (priv->raminit) 227 priv->raminit(priv, enable); 228} 229 230static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 231{ 232 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 233 C_CAN_MSG_OBJ_TX_FIRST; 234} 235 236static inline int get_tx_echo_msg_obj(int txecho) 237{ 238 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 239} 240 241static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 242{ 243 u32 val = priv->read_reg(priv, index); 244 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 245 return val; 246} 247 248static void c_can_enable_all_interrupts(struct c_can_priv *priv, 249 int enable) 250{ 251 unsigned int cntrl_save = priv->read_reg(priv, 252 C_CAN_CTRL_REG); 253 254 if (enable) 255 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 256 else 257 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 258 259 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 260} 261 262static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 263{ 264 int count = MIN_TIMEOUT_VALUE; 265 266 while (count && priv->read_reg(priv, 267 C_CAN_IFACE(COMREQ_REG, iface)) & 268 IF_COMR_BUSY) { 269 count--; 270 udelay(1); 271 } 272 273 if (!count) 274 return 1; 275 276 return 0; 277} 278 279static inline void c_can_object_get(struct net_device *dev, 280 int iface, int objno, int mask) 281{ 282 struct c_can_priv *priv = netdev_priv(dev); 283 284 /* 285 * As per specs, after writting the message object number in the 286 * IF command request register the transfer b/w interface 287 * register and message RAM must be complete in 6 CAN-CLK 288 * period. 289 */ 290 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 291 IFX_WRITE_LOW_16BIT(mask)); 292 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 293 IFX_WRITE_LOW_16BIT(objno)); 294 295 if (c_can_msg_obj_is_busy(priv, iface)) 296 netdev_err(dev, "timed out in object get\n"); 297} 298 299static inline void c_can_object_put(struct net_device *dev, 300 int iface, int objno, int mask) 301{ 302 struct c_can_priv *priv = netdev_priv(dev); 303 304 /* 305 * As per specs, after writting the message object number in the 306 * IF command request register the transfer b/w interface 307 * register and message RAM must be complete in 6 CAN-CLK 308 * period. 309 */ 310 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 311 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 312 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 313 IFX_WRITE_LOW_16BIT(objno)); 314 315 if (c_can_msg_obj_is_busy(priv, iface)) 316 netdev_err(dev, "timed out in object put\n"); 317} 318 319static void c_can_write_msg_object(struct net_device *dev, 320 int iface, struct can_frame *frame, int objno) 321{ 322 int i; 323 u16 flags = 0; 324 unsigned int id; 325 struct c_can_priv *priv = netdev_priv(dev); 326 327 if (!(frame->can_id & CAN_RTR_FLAG)) 328 flags |= IF_ARB_TRANSMIT; 329 330 if (frame->can_id & CAN_EFF_FLAG) { 331 id = frame->can_id & CAN_EFF_MASK; 332 flags |= IF_ARB_MSGXTD; 333 } else 334 id = ((frame->can_id & CAN_SFF_MASK) << 18); 335 336 flags |= IF_ARB_MSGVAL; 337 338 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 339 IFX_WRITE_LOW_16BIT(id)); 340 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 341 IFX_WRITE_HIGH_16BIT(id)); 342 343 for (i = 0; i < frame->can_dlc; i += 2) { 344 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 345 frame->data[i] | (frame->data[i + 1] << 8)); 346 } 347 348 /* enable interrupt for this message object */ 349 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 350 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 351 frame->can_dlc); 352 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 353} 354 355static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 356 int iface, 357 int ctrl_mask) 358{ 359 int i; 360 struct c_can_priv *priv = netdev_priv(dev); 361 362 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 364 ctrl_mask & ~IF_MCONT_NEWDAT); 365 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 366 } 367} 368 369static int c_can_handle_lost_msg_obj(struct net_device *dev, 370 int iface, int objno, u32 ctrl) 371{ 372 struct net_device_stats *stats = &dev->stats; 373 struct c_can_priv *priv = netdev_priv(dev); 374 struct can_frame *frame; 375 struct sk_buff *skb; 376 377 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 378 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 379 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 380 381 /* create an error msg */ 382 skb = alloc_can_err_skb(dev, &frame); 383 if (unlikely(!skb)) 384 return 0; 385 386 frame->can_id |= CAN_ERR_CRTL; 387 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 388 stats->rx_errors++; 389 stats->rx_over_errors++; 390 391 netif_receive_skb(skb); 392 return 1; 393} 394 395static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 396{ 397 u16 flags, data; 398 int i; 399 unsigned int val; 400 struct c_can_priv *priv = netdev_priv(dev); 401 struct net_device_stats *stats = &dev->stats; 402 struct sk_buff *skb; 403 struct can_frame *frame; 404 405 skb = alloc_can_skb(dev, &frame); 406 if (!skb) { 407 stats->rx_dropped++; 408 return -ENOMEM; 409 } 410 411 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 412 413 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 414 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 415 (flags << 16); 416 417 if (flags & IF_ARB_MSGXTD) 418 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 419 else 420 frame->can_id = (val >> 18) & CAN_SFF_MASK; 421 422 if (flags & IF_ARB_TRANSMIT) 423 frame->can_id |= CAN_RTR_FLAG; 424 else { 425 for (i = 0; i < frame->can_dlc; i += 2) { 426 data = priv->read_reg(priv, 427 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 428 frame->data[i] = data; 429 frame->data[i + 1] = data >> 8; 430 } 431 } 432 433 stats->rx_packets++; 434 stats->rx_bytes += frame->can_dlc; 435 436 netif_receive_skb(skb); 437 return 0; 438} 439 440static void c_can_setup_receive_object(struct net_device *dev, int iface, 441 int objno, unsigned int mask, 442 unsigned int id, unsigned int mcont) 443{ 444 struct c_can_priv *priv = netdev_priv(dev); 445 446 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 447 IFX_WRITE_LOW_16BIT(mask)); 448 449 /* According to C_CAN documentation, the reserved bit 450 * in IFx_MASK2 register is fixed 1 451 */ 452 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 453 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 454 455 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 456 IFX_WRITE_LOW_16BIT(id)); 457 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 458 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 459 460 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 461 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 462 463 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 464 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 465} 466 467static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 468{ 469 struct c_can_priv *priv = netdev_priv(dev); 470 471 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 472 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 473 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 474 475 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 476 477 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 478 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 479} 480 481static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 482{ 483 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 484 485 /* 486 * as transmission request register's bit n-1 corresponds to 487 * message object n, we need to handle the same properly. 488 */ 489 if (val & (1 << (objno - 1))) 490 return 1; 491 492 return 0; 493} 494 495static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 496 struct net_device *dev) 497{ 498 u32 msg_obj_no; 499 struct c_can_priv *priv = netdev_priv(dev); 500 struct can_frame *frame = (struct can_frame *)skb->data; 501 502 if (can_dropped_invalid_skb(dev, skb)) 503 return NETDEV_TX_OK; 504 505 spin_lock_bh(&priv->xmit_lock); 506 msg_obj_no = get_tx_next_msg_obj(priv); 507 508 /* prepare message object for transmission */ 509 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 510 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 511 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 512 513 /* 514 * we have to stop the queue in case of a wrap around or 515 * if the next TX message object is still in use 516 */ 517 priv->tx_next++; 518 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 519 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 520 netif_stop_queue(dev); 521 spin_unlock_bh(&priv->xmit_lock); 522 523 return NETDEV_TX_OK; 524} 525 526static int c_can_wait_for_ctrl_init(struct net_device *dev, 527 struct c_can_priv *priv, u32 init) 528{ 529 int retry = 0; 530 531 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 532 udelay(10); 533 if (retry++ > 1000) { 534 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 535 return -EIO; 536 } 537 } 538 return 0; 539} 540 541static int c_can_set_bittiming(struct net_device *dev) 542{ 543 unsigned int reg_btr, reg_brpe, ctrl_save; 544 u8 brp, brpe, sjw, tseg1, tseg2; 545 u32 ten_bit_brp; 546 struct c_can_priv *priv = netdev_priv(dev); 547 const struct can_bittiming *bt = &priv->can.bittiming; 548 int res; 549 550 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 551 ten_bit_brp = bt->brp - 1; 552 brp = ten_bit_brp & BTR_BRP_MASK; 553 brpe = ten_bit_brp >> 6; 554 555 sjw = bt->sjw - 1; 556 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 557 tseg2 = bt->phase_seg2 - 1; 558 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 559 (tseg2 << BTR_TSEG2_SHIFT); 560 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 561 562 netdev_info(dev, 563 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 564 565 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 566 ctrl_save &= ~CONTROL_INIT; 567 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 568 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 569 if (res) 570 return res; 571 572 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 573 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 574 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 575 576 return c_can_wait_for_ctrl_init(dev, priv, 0); 577} 578 579/* 580 * Configure C_CAN message objects for Tx and Rx purposes: 581 * C_CAN provides a total of 32 message objects that can be configured 582 * either for Tx or Rx purposes. Here the first 16 message objects are used as 583 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 584 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 585 * See user guide document for further details on configuring message 586 * objects. 587 */ 588static void c_can_configure_msg_objects(struct net_device *dev) 589{ 590 int i; 591 592 /* first invalidate all message objects */ 593 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 594 c_can_inval_msg_object(dev, IF_RX, i); 595 596 /* setup receive message objects */ 597 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 598 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 599 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 600 601 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 602 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 603} 604 605/* 606 * Configure C_CAN chip: 607 * - enable/disable auto-retransmission 608 * - set operating mode 609 * - configure message objects 610 */ 611static int c_can_chip_config(struct net_device *dev) 612{ 613 struct c_can_priv *priv = netdev_priv(dev); 614 615 /* enable automatic retransmission */ 616 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 617 618 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 619 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 620 /* loopback + silent mode : useful for hot self-test */ 621 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 622 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 623 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 624 /* loopback mode : useful for self-test function */ 625 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 626 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 627 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 628 /* silent mode : bus-monitoring mode */ 629 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 630 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 631 } 632 633 /* configure message objects */ 634 c_can_configure_msg_objects(dev); 635 636 /* set a `lec` value so that we can check for updates later */ 637 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 638 639 /* set bittiming params */ 640 return c_can_set_bittiming(dev); 641} 642 643static int c_can_start(struct net_device *dev) 644{ 645 struct c_can_priv *priv = netdev_priv(dev); 646 int err; 647 648 /* basic c_can configuration */ 649 err = c_can_chip_config(dev); 650 if (err) 651 return err; 652 653 priv->can.state = CAN_STATE_ERROR_ACTIVE; 654 655 /* reset tx helper pointers */ 656 priv->tx_next = priv->tx_echo = 0; 657 658 return 0; 659} 660 661static void c_can_stop(struct net_device *dev) 662{ 663 struct c_can_priv *priv = netdev_priv(dev); 664 665 /* disable all interrupts */ 666 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 667 668 /* set the state as STOPPED */ 669 priv->can.state = CAN_STATE_STOPPED; 670} 671 672static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 673{ 674 struct c_can_priv *priv = netdev_priv(dev); 675 int err; 676 677 switch (mode) { 678 case CAN_MODE_START: 679 err = c_can_start(dev); 680 if (err) 681 return err; 682 netif_wake_queue(dev); 683 /* enable status change, error and module interrupts */ 684 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 685 break; 686 default: 687 return -EOPNOTSUPP; 688 } 689 690 return 0; 691} 692 693static int __c_can_get_berr_counter(const struct net_device *dev, 694 struct can_berr_counter *bec) 695{ 696 unsigned int reg_err_counter; 697 struct c_can_priv *priv = netdev_priv(dev); 698 699 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 700 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 701 ERR_CNT_REC_SHIFT; 702 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 703 704 return 0; 705} 706 707static int c_can_get_berr_counter(const struct net_device *dev, 708 struct can_berr_counter *bec) 709{ 710 struct c_can_priv *priv = netdev_priv(dev); 711 int err; 712 713 c_can_pm_runtime_get_sync(priv); 714 err = __c_can_get_berr_counter(dev, bec); 715 c_can_pm_runtime_put_sync(priv); 716 717 return err; 718} 719 720/* 721 * priv->tx_echo holds the number of the oldest can_frame put for 722 * transmission into the hardware, but not yet ACKed by the CAN tx 723 * complete IRQ. 724 * 725 * We iterate from priv->tx_echo to priv->tx_next and check if the 726 * packet has been transmitted, echo it back to the CAN framework. 727 * If we discover a not yet transmitted packet, stop looking for more. 728 */ 729static void c_can_do_tx(struct net_device *dev) 730{ 731 struct c_can_priv *priv = netdev_priv(dev); 732 struct net_device_stats *stats = &dev->stats; 733 u32 val, obj, pkts = 0, bytes = 0; 734 735 spin_lock_bh(&priv->xmit_lock); 736 737 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 738 obj = get_tx_echo_msg_obj(priv->tx_echo); 739 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 740 741 if (val & (1 << (obj - 1))) 742 break; 743 744 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 745 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 746 pkts++; 747 c_can_inval_msg_object(dev, IF_TX, obj); 748 } 749 750 /* restart queue if wrap-up or if queue stalled on last pkt */ 751 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 752 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 753 netif_wake_queue(dev); 754 755 spin_unlock_bh(&priv->xmit_lock); 756 757 if (pkts) { 758 stats->tx_bytes += bytes; 759 stats->tx_packets += pkts; 760 can_led_event(dev, CAN_LED_EVENT_TX); 761 } 762} 763 764/* 765 * If we have a gap in the pending bits, that means we either 766 * raced with the hardware or failed to readout all upper 767 * objects in the last run due to quota limit. 768 */ 769static u32 c_can_adjust_pending(u32 pend) 770{ 771 u32 weight, lasts; 772 773 if (pend == RECEIVE_OBJECT_BITS) 774 return pend; 775 776 /* 777 * If the last set bit is larger than the number of pending 778 * bits we have a gap. 779 */ 780 weight = hweight32(pend); 781 lasts = fls(pend); 782 783 /* If the bits are linear, nothing to do */ 784 if (lasts == weight) 785 return pend; 786 787 /* 788 * Find the first set bit after the gap. We walk backwards 789 * from the last set bit. 790 */ 791 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 792 793 return pend & ~((1 << lasts) - 1); 794} 795 796static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 797 u32 pend, int quota) 798{ 799 u32 pkts = 0, ctrl, obj, mcmd; 800 801 while ((obj = ffs(pend)) && quota > 0) { 802 pend &= ~BIT(obj - 1); 803 804 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 805 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 806 807 c_can_object_get(dev, IF_RX, obj, mcmd); 808 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 809 810 if (ctrl & IF_MCONT_MSGLST) { 811 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 812 813 pkts += n; 814 quota -= n; 815 continue; 816 } 817 818 /* 819 * This really should not happen, but this covers some 820 * odd HW behaviour. Do not remove that unless you 821 * want to brick your machine. 822 */ 823 if (!(ctrl & IF_MCONT_NEWDAT)) 824 continue; 825 826 /* read the data from the message object */ 827 c_can_read_msg_object(dev, IF_RX, ctrl); 828 829 if (obj == C_CAN_MSG_RX_LOW_LAST) 830 /* activate all lower message objects */ 831 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 832 833 pkts++; 834 quota--; 835 } 836 837 return pkts; 838} 839 840/* 841 * theory of operation: 842 * 843 * c_can core saves a received CAN message into the first free message 844 * object it finds free (starting with the lowest). Bits NEWDAT and 845 * INTPND are set for this message object indicating that a new message 846 * has arrived. To work-around this issue, we keep two groups of message 847 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 848 * 849 * To ensure in-order frame reception we use the following 850 * approach while re-activating a message object to receive further 851 * frames: 852 * - if the current message object number is lower than 853 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 854 * the INTPND bit. 855 * - if the current message object number is equal to 856 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 857 * receive message objects. 858 * - if the current message object number is greater than 859 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 860 * only this message object. 861 */ 862static int c_can_do_rx_poll(struct net_device *dev, int quota) 863{ 864 struct c_can_priv *priv = netdev_priv(dev); 865 u32 pkts = 0, pend = 0, toread, n; 866 867 /* 868 * It is faster to read only one 16bit register. This is only possible 869 * for a maximum number of 16 objects. 870 */ 871 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 872 "Implementation does not support more message objects than 16"); 873 874 while (quota > 0) { 875 if (!pend) { 876 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 877 if (!pend) 878 break; 879 /* 880 * If the pending field has a gap, handle the 881 * bits above the gap first. 882 */ 883 toread = c_can_adjust_pending(pend); 884 } else { 885 toread = pend; 886 } 887 /* Remove the bits from pend */ 888 pend &= ~toread; 889 /* Read the objects */ 890 n = c_can_read_objects(dev, priv, toread, quota); 891 pkts += n; 892 quota -= n; 893 } 894 895 if (pkts) 896 can_led_event(dev, CAN_LED_EVENT_RX); 897 898 return pkts; 899} 900 901static int c_can_handle_state_change(struct net_device *dev, 902 enum c_can_bus_error_types error_type) 903{ 904 unsigned int reg_err_counter; 905 unsigned int rx_err_passive; 906 struct c_can_priv *priv = netdev_priv(dev); 907 struct net_device_stats *stats = &dev->stats; 908 struct can_frame *cf; 909 struct sk_buff *skb; 910 struct can_berr_counter bec; 911 912 switch (error_type) { 913 case C_CAN_ERROR_WARNING: 914 /* error warning state */ 915 priv->can.can_stats.error_warning++; 916 priv->can.state = CAN_STATE_ERROR_WARNING; 917 break; 918 case C_CAN_ERROR_PASSIVE: 919 /* error passive state */ 920 priv->can.can_stats.error_passive++; 921 priv->can.state = CAN_STATE_ERROR_PASSIVE; 922 break; 923 case C_CAN_BUS_OFF: 924 /* bus-off state */ 925 priv->can.state = CAN_STATE_BUS_OFF; 926 can_bus_off(dev); 927 break; 928 default: 929 break; 930 } 931 932 /* propagate the error condition to the CAN stack */ 933 skb = alloc_can_err_skb(dev, &cf); 934 if (unlikely(!skb)) 935 return 0; 936 937 __c_can_get_berr_counter(dev, &bec); 938 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 939 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 940 ERR_CNT_RP_SHIFT; 941 942 switch (error_type) { 943 case C_CAN_ERROR_WARNING: 944 /* error warning state */ 945 cf->can_id |= CAN_ERR_CRTL; 946 cf->data[1] = (bec.txerr > bec.rxerr) ? 947 CAN_ERR_CRTL_TX_WARNING : 948 CAN_ERR_CRTL_RX_WARNING; 949 cf->data[6] = bec.txerr; 950 cf->data[7] = bec.rxerr; 951 952 break; 953 case C_CAN_ERROR_PASSIVE: 954 /* error passive state */ 955 cf->can_id |= CAN_ERR_CRTL; 956 if (rx_err_passive) 957 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 958 if (bec.txerr > 127) 959 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 960 961 cf->data[6] = bec.txerr; 962 cf->data[7] = bec.rxerr; 963 break; 964 case C_CAN_BUS_OFF: 965 /* bus-off state */ 966 cf->can_id |= CAN_ERR_BUSOFF; 967 can_bus_off(dev); 968 break; 969 default: 970 break; 971 } 972 973 stats->rx_packets++; 974 stats->rx_bytes += cf->can_dlc; 975 netif_receive_skb(skb); 976 977 return 1; 978} 979 980static int c_can_handle_bus_err(struct net_device *dev, 981 enum c_can_lec_type lec_type) 982{ 983 struct c_can_priv *priv = netdev_priv(dev); 984 struct net_device_stats *stats = &dev->stats; 985 struct can_frame *cf; 986 struct sk_buff *skb; 987 988 /* 989 * early exit if no lec update or no error. 990 * no lec update means that no CAN bus event has been detected 991 * since CPU wrote 0x7 value to status reg. 992 */ 993 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 994 return 0; 995 996 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 997 return 0; 998 999 /* propagate the error condition to the CAN stack */ 1000 skb = alloc_can_err_skb(dev, &cf); 1001 if (unlikely(!skb)) 1002 return 0; 1003 1004 /* 1005 * check for 'last error code' which tells us the 1006 * type of the last error to occur on the CAN bus 1007 */ 1008 1009 /* common for all type of bus errors */ 1010 priv->can.can_stats.bus_error++; 1011 stats->rx_errors++; 1012 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1013 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1014 1015 switch (lec_type) { 1016 case LEC_STUFF_ERROR: 1017 netdev_dbg(dev, "stuff error\n"); 1018 cf->data[2] |= CAN_ERR_PROT_STUFF; 1019 break; 1020 case LEC_FORM_ERROR: 1021 netdev_dbg(dev, "form error\n"); 1022 cf->data[2] |= CAN_ERR_PROT_FORM; 1023 break; 1024 case LEC_ACK_ERROR: 1025 netdev_dbg(dev, "ack error\n"); 1026 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1027 CAN_ERR_PROT_LOC_ACK_DEL); 1028 break; 1029 case LEC_BIT1_ERROR: 1030 netdev_dbg(dev, "bit1 error\n"); 1031 cf->data[2] |= CAN_ERR_PROT_BIT1; 1032 break; 1033 case LEC_BIT0_ERROR: 1034 netdev_dbg(dev, "bit0 error\n"); 1035 cf->data[2] |= CAN_ERR_PROT_BIT0; 1036 break; 1037 case LEC_CRC_ERROR: 1038 netdev_dbg(dev, "CRC error\n"); 1039 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1040 CAN_ERR_PROT_LOC_CRC_DEL); 1041 break; 1042 default: 1043 break; 1044 } 1045 1046 /* set a `lec` value so that we can check for updates later */ 1047 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1048 1049 stats->rx_packets++; 1050 stats->rx_bytes += cf->can_dlc; 1051 netif_receive_skb(skb); 1052 return 1; 1053} 1054 1055static int c_can_poll(struct napi_struct *napi, int quota) 1056{ 1057 u16 irqstatus; 1058 int work_done = 0; 1059 struct net_device *dev = napi->dev; 1060 struct c_can_priv *priv = netdev_priv(dev); 1061 1062 irqstatus = priv->irqstatus; 1063 if (!irqstatus) 1064 goto end; 1065 1066 /* status events have the highest priority */ 1067 if (irqstatus == STATUS_INTERRUPT) { 1068 priv->current_status = priv->read_reg(priv, 1069 C_CAN_STS_REG); 1070 1071 /* handle Tx/Rx events */ 1072 if (priv->current_status & STATUS_TXOK) 1073 priv->write_reg(priv, C_CAN_STS_REG, 1074 priv->current_status & ~STATUS_TXOK); 1075 1076 if (priv->current_status & STATUS_RXOK) 1077 priv->write_reg(priv, C_CAN_STS_REG, 1078 priv->current_status & ~STATUS_RXOK); 1079 1080 /* handle state changes */ 1081 if ((priv->current_status & STATUS_EWARN) && 1082 (!(priv->last_status & STATUS_EWARN))) { 1083 netdev_dbg(dev, "entered error warning state\n"); 1084 work_done += c_can_handle_state_change(dev, 1085 C_CAN_ERROR_WARNING); 1086 } 1087 if ((priv->current_status & STATUS_EPASS) && 1088 (!(priv->last_status & STATUS_EPASS))) { 1089 netdev_dbg(dev, "entered error passive state\n"); 1090 work_done += c_can_handle_state_change(dev, 1091 C_CAN_ERROR_PASSIVE); 1092 } 1093 if ((priv->current_status & STATUS_BOFF) && 1094 (!(priv->last_status & STATUS_BOFF))) { 1095 netdev_dbg(dev, "entered bus off state\n"); 1096 work_done += c_can_handle_state_change(dev, 1097 C_CAN_BUS_OFF); 1098 goto end; 1099 } 1100 1101 /* handle bus recovery events */ 1102 if ((!(priv->current_status & STATUS_BOFF)) && 1103 (priv->last_status & STATUS_BOFF)) { 1104 netdev_dbg(dev, "left bus off state\n"); 1105 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1106 } 1107 if ((!(priv->current_status & STATUS_EPASS)) && 1108 (priv->last_status & STATUS_EPASS)) { 1109 netdev_dbg(dev, "left error passive state\n"); 1110 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1111 } 1112 1113 priv->last_status = priv->current_status; 1114 1115 /* handle lec errors on the bus */ 1116 work_done += c_can_handle_bus_err(dev, 1117 priv->current_status & LEC_MASK); 1118 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1119 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1120 /* handle events corresponding to receive message objects */ 1121 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1122 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1123 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1124 /* handle events corresponding to transmit message objects */ 1125 c_can_do_tx(dev); 1126 } 1127 1128end: 1129 if (work_done < quota) { 1130 napi_complete(napi); 1131 /* enable all IRQs if we are not in bus off state */ 1132 if (priv->can.state != CAN_STATE_BUS_OFF) 1133 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1134 } 1135 1136 return work_done; 1137} 1138 1139static irqreturn_t c_can_isr(int irq, void *dev_id) 1140{ 1141 struct net_device *dev = (struct net_device *)dev_id; 1142 struct c_can_priv *priv = netdev_priv(dev); 1143 1144 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1145 if (!priv->irqstatus) 1146 return IRQ_NONE; 1147 1148 /* disable all interrupts and schedule the NAPI */ 1149 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1150 napi_schedule(&priv->napi); 1151 1152 return IRQ_HANDLED; 1153} 1154 1155static int c_can_open(struct net_device *dev) 1156{ 1157 int err; 1158 struct c_can_priv *priv = netdev_priv(dev); 1159 1160 c_can_pm_runtime_get_sync(priv); 1161 c_can_reset_ram(priv, true); 1162 1163 /* open the can device */ 1164 err = open_candev(dev); 1165 if (err) { 1166 netdev_err(dev, "failed to open can device\n"); 1167 goto exit_open_fail; 1168 } 1169 1170 /* register interrupt handler */ 1171 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1172 dev); 1173 if (err < 0) { 1174 netdev_err(dev, "failed to request interrupt\n"); 1175 goto exit_irq_fail; 1176 } 1177 1178 /* start the c_can controller */ 1179 err = c_can_start(dev); 1180 if (err) 1181 goto exit_start_fail; 1182 1183 can_led_event(dev, CAN_LED_EVENT_OPEN); 1184 1185 napi_enable(&priv->napi); 1186 /* enable status change, error and module interrupts */ 1187 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1188 netif_start_queue(dev); 1189 1190 return 0; 1191 1192exit_start_fail: 1193 free_irq(dev->irq, dev); 1194exit_irq_fail: 1195 close_candev(dev); 1196exit_open_fail: 1197 c_can_reset_ram(priv, false); 1198 c_can_pm_runtime_put_sync(priv); 1199 return err; 1200} 1201 1202static int c_can_close(struct net_device *dev) 1203{ 1204 struct c_can_priv *priv = netdev_priv(dev); 1205 1206 netif_stop_queue(dev); 1207 napi_disable(&priv->napi); 1208 c_can_stop(dev); 1209 free_irq(dev->irq, dev); 1210 close_candev(dev); 1211 1212 c_can_reset_ram(priv, false); 1213 c_can_pm_runtime_put_sync(priv); 1214 1215 can_led_event(dev, CAN_LED_EVENT_STOP); 1216 1217 return 0; 1218} 1219 1220struct net_device *alloc_c_can_dev(void) 1221{ 1222 struct net_device *dev; 1223 struct c_can_priv *priv; 1224 1225 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1226 if (!dev) 1227 return NULL; 1228 1229 priv = netdev_priv(dev); 1230 spin_lock_init(&priv->xmit_lock); 1231 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1232 1233 priv->dev = dev; 1234 priv->can.bittiming_const = &c_can_bittiming_const; 1235 priv->can.do_set_mode = c_can_set_mode; 1236 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1237 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1238 CAN_CTRLMODE_LISTENONLY | 1239 CAN_CTRLMODE_BERR_REPORTING; 1240 1241 return dev; 1242} 1243EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1244 1245#ifdef CONFIG_PM 1246int c_can_power_down(struct net_device *dev) 1247{ 1248 u32 val; 1249 unsigned long time_out; 1250 struct c_can_priv *priv = netdev_priv(dev); 1251 1252 if (!(dev->flags & IFF_UP)) 1253 return 0; 1254 1255 WARN_ON(priv->type != BOSCH_D_CAN); 1256 1257 /* set PDR value so the device goes to power down mode */ 1258 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1259 val |= CONTROL_EX_PDR; 1260 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1261 1262 /* Wait for the PDA bit to get set */ 1263 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1264 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1265 time_after(time_out, jiffies)) 1266 cpu_relax(); 1267 1268 if (time_after(jiffies, time_out)) 1269 return -ETIMEDOUT; 1270 1271 c_can_stop(dev); 1272 1273 c_can_reset_ram(priv, false); 1274 c_can_pm_runtime_put_sync(priv); 1275 1276 return 0; 1277} 1278EXPORT_SYMBOL_GPL(c_can_power_down); 1279 1280int c_can_power_up(struct net_device *dev) 1281{ 1282 u32 val; 1283 unsigned long time_out; 1284 struct c_can_priv *priv = netdev_priv(dev); 1285 int ret; 1286 1287 if (!(dev->flags & IFF_UP)) 1288 return 0; 1289 1290 WARN_ON(priv->type != BOSCH_D_CAN); 1291 1292 c_can_pm_runtime_get_sync(priv); 1293 c_can_reset_ram(priv, true); 1294 1295 /* Clear PDR and INIT bits */ 1296 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1297 val &= ~CONTROL_EX_PDR; 1298 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1299 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1300 val &= ~CONTROL_INIT; 1301 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1302 1303 /* Wait for the PDA bit to get clear */ 1304 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1305 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1306 time_after(time_out, jiffies)) 1307 cpu_relax(); 1308 1309 if (time_after(jiffies, time_out)) 1310 return -ETIMEDOUT; 1311 1312 ret = c_can_start(dev); 1313 if (!ret) 1314 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1315 1316 return ret; 1317} 1318EXPORT_SYMBOL_GPL(c_can_power_up); 1319#endif 1320 1321void free_c_can_dev(struct net_device *dev) 1322{ 1323 struct c_can_priv *priv = netdev_priv(dev); 1324 1325 netif_napi_del(&priv->napi); 1326 free_candev(dev); 1327} 1328EXPORT_SYMBOL_GPL(free_c_can_dev); 1329 1330static const struct net_device_ops c_can_netdev_ops = { 1331 .ndo_open = c_can_open, 1332 .ndo_stop = c_can_close, 1333 .ndo_start_xmit = c_can_start_xmit, 1334 .ndo_change_mtu = can_change_mtu, 1335}; 1336 1337int register_c_can_dev(struct net_device *dev) 1338{ 1339 struct c_can_priv *priv = netdev_priv(dev); 1340 int err; 1341 1342 c_can_pm_runtime_enable(priv); 1343 1344 dev->flags |= IFF_ECHO; /* we support local echo */ 1345 dev->netdev_ops = &c_can_netdev_ops; 1346 1347 err = register_candev(dev); 1348 if (err) 1349 c_can_pm_runtime_disable(priv); 1350 else 1351 devm_can_led_init(dev); 1352 1353 return err; 1354} 1355EXPORT_SYMBOL_GPL(register_c_can_dev); 1356 1357void unregister_c_can_dev(struct net_device *dev) 1358{ 1359 struct c_can_priv *priv = netdev_priv(dev); 1360 1361 unregister_candev(dev); 1362 1363 c_can_pm_runtime_disable(priv); 1364} 1365EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1366 1367MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1368MODULE_LICENSE("GPL v2"); 1369MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1370