c_can.c revision 1da394d889b4110bda954813ef32601c06118376
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42#include <linux/can/led.h> 43 44#include "c_can.h" 45 46/* Number of interface registers */ 47#define IF_ENUM_REG_LEN 11 48#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 49 50/* control extension register D_CAN specific */ 51#define CONTROL_EX_PDR BIT(8) 52 53/* control register */ 54#define CONTROL_TEST BIT(7) 55#define CONTROL_CCE BIT(6) 56#define CONTROL_DISABLE_AR BIT(5) 57#define CONTROL_ENABLE_AR (0 << 5) 58#define CONTROL_EIE BIT(3) 59#define CONTROL_SIE BIT(2) 60#define CONTROL_IE BIT(1) 61#define CONTROL_INIT BIT(0) 62 63/* test register */ 64#define TEST_RX BIT(7) 65#define TEST_TX1 BIT(6) 66#define TEST_TX2 BIT(5) 67#define TEST_LBACK BIT(4) 68#define TEST_SILENT BIT(3) 69#define TEST_BASIC BIT(2) 70 71/* status register */ 72#define STATUS_PDA BIT(10) 73#define STATUS_BOFF BIT(7) 74#define STATUS_EWARN BIT(6) 75#define STATUS_EPASS BIT(5) 76#define STATUS_RXOK BIT(4) 77#define STATUS_TXOK BIT(3) 78 79/* error counter register */ 80#define ERR_CNT_TEC_MASK 0xff 81#define ERR_CNT_TEC_SHIFT 0 82#define ERR_CNT_REC_SHIFT 8 83#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 84#define ERR_CNT_RP_SHIFT 15 85#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 86 87/* bit-timing register */ 88#define BTR_BRP_MASK 0x3f 89#define BTR_BRP_SHIFT 0 90#define BTR_SJW_SHIFT 6 91#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 92#define BTR_TSEG1_SHIFT 8 93#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 94#define BTR_TSEG2_SHIFT 12 95#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 96 97/* brp extension register */ 98#define BRP_EXT_BRPE_MASK 0x0f 99#define BRP_EXT_BRPE_SHIFT 0 100 101/* IFx command request */ 102#define IF_COMR_BUSY BIT(15) 103 104/* IFx command mask */ 105#define IF_COMM_WR BIT(7) 106#define IF_COMM_MASK BIT(6) 107#define IF_COMM_ARB BIT(5) 108#define IF_COMM_CONTROL BIT(4) 109#define IF_COMM_CLR_INT_PND BIT(3) 110#define IF_COMM_TXRQST BIT(2) 111#define IF_COMM_DATAA BIT(1) 112#define IF_COMM_DATAB BIT(0) 113#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 114 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 115 IF_COMM_DATAA | IF_COMM_DATAB) 116 117/* For the low buffers we clear the interrupt bit, but keep newdat */ 118#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ 119 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ 120 IF_COMM_DATAA | IF_COMM_DATAB) 121 122/* For the high buffers we clear the interrupt bit and newdat */ 123#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_TXRQST) 124 125/* IFx arbitration */ 126#define IF_ARB_MSGVAL BIT(15) 127#define IF_ARB_MSGXTD BIT(14) 128#define IF_ARB_TRANSMIT BIT(13) 129 130/* IFx message control */ 131#define IF_MCONT_NEWDAT BIT(15) 132#define IF_MCONT_MSGLST BIT(14) 133#define IF_MCONT_INTPND BIT(13) 134#define IF_MCONT_UMASK BIT(12) 135#define IF_MCONT_TXIE BIT(11) 136#define IF_MCONT_RXIE BIT(10) 137#define IF_MCONT_RMTEN BIT(9) 138#define IF_MCONT_TXRQST BIT(8) 139#define IF_MCONT_EOB BIT(7) 140#define IF_MCONT_DLC_MASK 0xf 141 142/* 143 * Use IF1 for RX and IF2 for TX 144 */ 145#define IF_RX 0 146#define IF_TX 1 147 148/* status interrupt */ 149#define STATUS_INTERRUPT 0x8000 150 151/* global interrupt masks */ 152#define ENABLE_ALL_INTERRUPTS 1 153#define DISABLE_ALL_INTERRUPTS 0 154 155/* minimum timeout for checking BUSY status */ 156#define MIN_TIMEOUT_VALUE 6 157 158/* Wait for ~1 sec for INIT bit */ 159#define INIT_WAIT_MS 1000 160 161/* napi related */ 162#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 163 164/* c_can lec values */ 165enum c_can_lec_type { 166 LEC_NO_ERROR = 0, 167 LEC_STUFF_ERROR, 168 LEC_FORM_ERROR, 169 LEC_ACK_ERROR, 170 LEC_BIT1_ERROR, 171 LEC_BIT0_ERROR, 172 LEC_CRC_ERROR, 173 LEC_UNUSED, 174 LEC_MASK = LEC_UNUSED, 175}; 176 177/* 178 * c_can error types: 179 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 180 */ 181enum c_can_bus_error_types { 182 C_CAN_NO_ERROR = 0, 183 C_CAN_BUS_OFF, 184 C_CAN_ERROR_WARNING, 185 C_CAN_ERROR_PASSIVE, 186}; 187 188static const struct can_bittiming_const c_can_bittiming_const = { 189 .name = KBUILD_MODNAME, 190 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 191 .tseg1_max = 16, 192 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 193 .tseg2_max = 8, 194 .sjw_max = 4, 195 .brp_min = 1, 196 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 197 .brp_inc = 1, 198}; 199 200static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 201{ 202 if (priv->device) 203 pm_runtime_enable(priv->device); 204} 205 206static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 207{ 208 if (priv->device) 209 pm_runtime_disable(priv->device); 210} 211 212static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 213{ 214 if (priv->device) 215 pm_runtime_get_sync(priv->device); 216} 217 218static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 219{ 220 if (priv->device) 221 pm_runtime_put_sync(priv->device); 222} 223 224static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 225{ 226 if (priv->raminit) 227 priv->raminit(priv, enable); 228} 229 230static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 231{ 232 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 233 C_CAN_MSG_OBJ_TX_FIRST; 234} 235 236static inline int get_tx_echo_msg_obj(int txecho) 237{ 238 return (txecho & C_CAN_NEXT_MSG_OBJ_MASK) + C_CAN_MSG_OBJ_TX_FIRST; 239} 240 241static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 242{ 243 u32 val = priv->read_reg(priv, index); 244 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 245 return val; 246} 247 248static void c_can_enable_all_interrupts(struct c_can_priv *priv, 249 int enable) 250{ 251 unsigned int cntrl_save = priv->read_reg(priv, 252 C_CAN_CTRL_REG); 253 254 if (enable) 255 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 256 else 257 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 258 259 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 260} 261 262static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 263{ 264 int count = MIN_TIMEOUT_VALUE; 265 266 while (count && priv->read_reg(priv, 267 C_CAN_IFACE(COMREQ_REG, iface)) & 268 IF_COMR_BUSY) { 269 count--; 270 udelay(1); 271 } 272 273 if (!count) 274 return 1; 275 276 return 0; 277} 278 279static inline void c_can_object_get(struct net_device *dev, 280 int iface, int objno, int mask) 281{ 282 struct c_can_priv *priv = netdev_priv(dev); 283 284 /* 285 * As per specs, after writting the message object number in the 286 * IF command request register the transfer b/w interface 287 * register and message RAM must be complete in 6 CAN-CLK 288 * period. 289 */ 290 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 291 IFX_WRITE_LOW_16BIT(mask)); 292 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 293 IFX_WRITE_LOW_16BIT(objno)); 294 295 if (c_can_msg_obj_is_busy(priv, iface)) 296 netdev_err(dev, "timed out in object get\n"); 297} 298 299static inline void c_can_object_put(struct net_device *dev, 300 int iface, int objno, int mask) 301{ 302 struct c_can_priv *priv = netdev_priv(dev); 303 304 /* 305 * As per specs, after writting the message object number in the 306 * IF command request register the transfer b/w interface 307 * register and message RAM must be complete in 6 CAN-CLK 308 * period. 309 */ 310 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 311 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 312 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 313 IFX_WRITE_LOW_16BIT(objno)); 314 315 if (c_can_msg_obj_is_busy(priv, iface)) 316 netdev_err(dev, "timed out in object put\n"); 317} 318 319static void c_can_write_msg_object(struct net_device *dev, 320 int iface, struct can_frame *frame, int objno) 321{ 322 int i; 323 u16 flags = 0; 324 unsigned int id; 325 struct c_can_priv *priv = netdev_priv(dev); 326 327 if (!(frame->can_id & CAN_RTR_FLAG)) 328 flags |= IF_ARB_TRANSMIT; 329 330 if (frame->can_id & CAN_EFF_FLAG) { 331 id = frame->can_id & CAN_EFF_MASK; 332 flags |= IF_ARB_MSGXTD; 333 } else 334 id = ((frame->can_id & CAN_SFF_MASK) << 18); 335 336 flags |= IF_ARB_MSGVAL; 337 338 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 339 IFX_WRITE_LOW_16BIT(id)); 340 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 341 IFX_WRITE_HIGH_16BIT(id)); 342 343 for (i = 0; i < frame->can_dlc; i += 2) { 344 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 345 frame->data[i] | (frame->data[i + 1] << 8)); 346 } 347 348 /* enable interrupt for this message object */ 349 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 350 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 351 frame->can_dlc); 352 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 353} 354 355static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 356 int iface, 357 int ctrl_mask) 358{ 359 int i; 360 struct c_can_priv *priv = netdev_priv(dev); 361 362 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 363 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 364 ctrl_mask & ~IF_MCONT_NEWDAT); 365 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 366 } 367} 368 369static int c_can_handle_lost_msg_obj(struct net_device *dev, 370 int iface, int objno, u32 ctrl) 371{ 372 struct net_device_stats *stats = &dev->stats; 373 struct c_can_priv *priv = netdev_priv(dev); 374 struct can_frame *frame; 375 struct sk_buff *skb; 376 377 ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); 378 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); 379 c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); 380 381 stats->rx_errors++; 382 stats->rx_over_errors++; 383 384 /* create an error msg */ 385 skb = alloc_can_err_skb(dev, &frame); 386 if (unlikely(!skb)) 387 return 0; 388 389 frame->can_id |= CAN_ERR_CRTL; 390 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 391 392 netif_receive_skb(skb); 393 return 1; 394} 395 396static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 397{ 398 u16 flags, data; 399 int i; 400 unsigned int val; 401 struct c_can_priv *priv = netdev_priv(dev); 402 struct net_device_stats *stats = &dev->stats; 403 struct sk_buff *skb; 404 struct can_frame *frame; 405 406 skb = alloc_can_skb(dev, &frame); 407 if (!skb) { 408 stats->rx_dropped++; 409 return -ENOMEM; 410 } 411 412 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 413 414 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 415 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 416 (flags << 16); 417 418 if (flags & IF_ARB_MSGXTD) 419 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 420 else 421 frame->can_id = (val >> 18) & CAN_SFF_MASK; 422 423 if (flags & IF_ARB_TRANSMIT) 424 frame->can_id |= CAN_RTR_FLAG; 425 else { 426 for (i = 0; i < frame->can_dlc; i += 2) { 427 data = priv->read_reg(priv, 428 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 429 frame->data[i] = data; 430 frame->data[i + 1] = data >> 8; 431 } 432 } 433 434 stats->rx_packets++; 435 stats->rx_bytes += frame->can_dlc; 436 437 netif_receive_skb(skb); 438 return 0; 439} 440 441static void c_can_setup_receive_object(struct net_device *dev, int iface, 442 int objno, unsigned int mask, 443 unsigned int id, unsigned int mcont) 444{ 445 struct c_can_priv *priv = netdev_priv(dev); 446 447 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 448 IFX_WRITE_LOW_16BIT(mask)); 449 450 /* According to C_CAN documentation, the reserved bit 451 * in IFx_MASK2 register is fixed 1 452 */ 453 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 454 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 455 456 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 457 IFX_WRITE_LOW_16BIT(id)); 458 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 459 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 460 461 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 462 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 463 464 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 465 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 466} 467 468static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 469{ 470 struct c_can_priv *priv = netdev_priv(dev); 471 472 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 473 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 474 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 475 476 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 477 478 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 479 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 480} 481 482static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 483{ 484 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 485 486 /* 487 * as transmission request register's bit n-1 corresponds to 488 * message object n, we need to handle the same properly. 489 */ 490 if (val & (1 << (objno - 1))) 491 return 1; 492 493 return 0; 494} 495 496static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 497 struct net_device *dev) 498{ 499 u32 msg_obj_no; 500 struct c_can_priv *priv = netdev_priv(dev); 501 struct can_frame *frame = (struct can_frame *)skb->data; 502 503 if (can_dropped_invalid_skb(dev, skb)) 504 return NETDEV_TX_OK; 505 506 spin_lock_bh(&priv->xmit_lock); 507 msg_obj_no = get_tx_next_msg_obj(priv); 508 509 /* prepare message object for transmission */ 510 c_can_write_msg_object(dev, IF_TX, frame, msg_obj_no); 511 priv->dlc[msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST] = frame->can_dlc; 512 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 513 514 /* 515 * we have to stop the queue in case of a wrap around or 516 * if the next TX message object is still in use 517 */ 518 priv->tx_next++; 519 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 520 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 521 netif_stop_queue(dev); 522 spin_unlock_bh(&priv->xmit_lock); 523 524 return NETDEV_TX_OK; 525} 526 527static int c_can_wait_for_ctrl_init(struct net_device *dev, 528 struct c_can_priv *priv, u32 init) 529{ 530 int retry = 0; 531 532 while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { 533 udelay(10); 534 if (retry++ > 1000) { 535 netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); 536 return -EIO; 537 } 538 } 539 return 0; 540} 541 542static int c_can_set_bittiming(struct net_device *dev) 543{ 544 unsigned int reg_btr, reg_brpe, ctrl_save; 545 u8 brp, brpe, sjw, tseg1, tseg2; 546 u32 ten_bit_brp; 547 struct c_can_priv *priv = netdev_priv(dev); 548 const struct can_bittiming *bt = &priv->can.bittiming; 549 int res; 550 551 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 552 ten_bit_brp = bt->brp - 1; 553 brp = ten_bit_brp & BTR_BRP_MASK; 554 brpe = ten_bit_brp >> 6; 555 556 sjw = bt->sjw - 1; 557 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 558 tseg2 = bt->phase_seg2 - 1; 559 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 560 (tseg2 << BTR_TSEG2_SHIFT); 561 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 562 563 netdev_info(dev, 564 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 565 566 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 567 ctrl_save &= ~CONTROL_INIT; 568 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); 569 res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); 570 if (res) 571 return res; 572 573 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 574 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 575 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 576 577 return c_can_wait_for_ctrl_init(dev, priv, 0); 578} 579 580/* 581 * Configure C_CAN message objects for Tx and Rx purposes: 582 * C_CAN provides a total of 32 message objects that can be configured 583 * either for Tx or Rx purposes. Here the first 16 message objects are used as 584 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 585 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 586 * See user guide document for further details on configuring message 587 * objects. 588 */ 589static void c_can_configure_msg_objects(struct net_device *dev) 590{ 591 int i; 592 593 /* first invalidate all message objects */ 594 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 595 c_can_inval_msg_object(dev, IF_RX, i); 596 597 /* setup receive message objects */ 598 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 599 c_can_setup_receive_object(dev, IF_RX, i, 0, 0, 600 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 601 602 c_can_setup_receive_object(dev, IF_RX, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 603 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 604} 605 606/* 607 * Configure C_CAN chip: 608 * - enable/disable auto-retransmission 609 * - set operating mode 610 * - configure message objects 611 */ 612static int c_can_chip_config(struct net_device *dev) 613{ 614 struct c_can_priv *priv = netdev_priv(dev); 615 616 /* enable automatic retransmission */ 617 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); 618 619 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 620 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 621 /* loopback + silent mode : useful for hot self-test */ 622 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 623 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); 624 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 625 /* loopback mode : useful for self-test function */ 626 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 627 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 628 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 629 /* silent mode : bus-monitoring mode */ 630 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); 631 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 632 } 633 634 /* configure message objects */ 635 c_can_configure_msg_objects(dev); 636 637 /* set a `lec` value so that we can check for updates later */ 638 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 639 640 /* set bittiming params */ 641 return c_can_set_bittiming(dev); 642} 643 644static int c_can_start(struct net_device *dev) 645{ 646 struct c_can_priv *priv = netdev_priv(dev); 647 int err; 648 649 /* basic c_can configuration */ 650 err = c_can_chip_config(dev); 651 if (err) 652 return err; 653 654 priv->can.state = CAN_STATE_ERROR_ACTIVE; 655 656 /* reset tx helper pointers */ 657 priv->tx_next = priv->tx_echo = 0; 658 659 return 0; 660} 661 662static void c_can_stop(struct net_device *dev) 663{ 664 struct c_can_priv *priv = netdev_priv(dev); 665 666 /* disable all interrupts */ 667 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 668 669 /* set the state as STOPPED */ 670 priv->can.state = CAN_STATE_STOPPED; 671} 672 673static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 674{ 675 struct c_can_priv *priv = netdev_priv(dev); 676 int err; 677 678 switch (mode) { 679 case CAN_MODE_START: 680 err = c_can_start(dev); 681 if (err) 682 return err; 683 netif_wake_queue(dev); 684 /* enable status change, error and module interrupts */ 685 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 686 break; 687 default: 688 return -EOPNOTSUPP; 689 } 690 691 return 0; 692} 693 694static int __c_can_get_berr_counter(const struct net_device *dev, 695 struct can_berr_counter *bec) 696{ 697 unsigned int reg_err_counter; 698 struct c_can_priv *priv = netdev_priv(dev); 699 700 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 701 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 702 ERR_CNT_REC_SHIFT; 703 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 704 705 return 0; 706} 707 708static int c_can_get_berr_counter(const struct net_device *dev, 709 struct can_berr_counter *bec) 710{ 711 struct c_can_priv *priv = netdev_priv(dev); 712 int err; 713 714 c_can_pm_runtime_get_sync(priv); 715 err = __c_can_get_berr_counter(dev, bec); 716 c_can_pm_runtime_put_sync(priv); 717 718 return err; 719} 720 721/* 722 * priv->tx_echo holds the number of the oldest can_frame put for 723 * transmission into the hardware, but not yet ACKed by the CAN tx 724 * complete IRQ. 725 * 726 * We iterate from priv->tx_echo to priv->tx_next and check if the 727 * packet has been transmitted, echo it back to the CAN framework. 728 * If we discover a not yet transmitted packet, stop looking for more. 729 */ 730static void c_can_do_tx(struct net_device *dev) 731{ 732 struct c_can_priv *priv = netdev_priv(dev); 733 struct net_device_stats *stats = &dev->stats; 734 u32 val, obj, pkts = 0, bytes = 0; 735 736 spin_lock_bh(&priv->xmit_lock); 737 738 for (; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 739 obj = get_tx_echo_msg_obj(priv->tx_echo); 740 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 741 742 if (val & (1 << (obj - 1))) 743 break; 744 745 can_get_echo_skb(dev, obj - C_CAN_MSG_OBJ_TX_FIRST); 746 bytes += priv->dlc[obj - C_CAN_MSG_OBJ_TX_FIRST]; 747 pkts++; 748 c_can_inval_msg_object(dev, IF_TX, obj); 749 } 750 751 /* restart queue if wrap-up or if queue stalled on last pkt */ 752 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 753 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 754 netif_wake_queue(dev); 755 756 spin_unlock_bh(&priv->xmit_lock); 757 758 if (pkts) { 759 stats->tx_bytes += bytes; 760 stats->tx_packets += pkts; 761 can_led_event(dev, CAN_LED_EVENT_TX); 762 } 763} 764 765/* 766 * If we have a gap in the pending bits, that means we either 767 * raced with the hardware or failed to readout all upper 768 * objects in the last run due to quota limit. 769 */ 770static u32 c_can_adjust_pending(u32 pend) 771{ 772 u32 weight, lasts; 773 774 if (pend == RECEIVE_OBJECT_BITS) 775 return pend; 776 777 /* 778 * If the last set bit is larger than the number of pending 779 * bits we have a gap. 780 */ 781 weight = hweight32(pend); 782 lasts = fls(pend); 783 784 /* If the bits are linear, nothing to do */ 785 if (lasts == weight) 786 return pend; 787 788 /* 789 * Find the first set bit after the gap. We walk backwards 790 * from the last set bit. 791 */ 792 for (lasts--; pend & (1 << (lasts - 1)); lasts--); 793 794 return pend & ~((1 << lasts) - 1); 795} 796 797static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, 798 u32 pend, int quota) 799{ 800 u32 pkts = 0, ctrl, obj, mcmd; 801 802 while ((obj = ffs(pend)) && quota > 0) { 803 pend &= ~BIT(obj - 1); 804 805 mcmd = obj < C_CAN_MSG_RX_LOW_LAST ? 806 IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; 807 808 c_can_object_get(dev, IF_RX, obj, mcmd); 809 ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); 810 811 if (ctrl & IF_MCONT_MSGLST) { 812 int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); 813 814 pkts += n; 815 quota -= n; 816 continue; 817 } 818 819 /* 820 * This really should not happen, but this covers some 821 * odd HW behaviour. Do not remove that unless you 822 * want to brick your machine. 823 */ 824 if (!(ctrl & IF_MCONT_NEWDAT)) 825 continue; 826 827 /* read the data from the message object */ 828 c_can_read_msg_object(dev, IF_RX, ctrl); 829 830 if (obj == C_CAN_MSG_RX_LOW_LAST) 831 /* activate all lower message objects */ 832 c_can_activate_all_lower_rx_msg_obj(dev, IF_RX, ctrl); 833 834 pkts++; 835 quota--; 836 } 837 838 return pkts; 839} 840 841/* 842 * theory of operation: 843 * 844 * c_can core saves a received CAN message into the first free message 845 * object it finds free (starting with the lowest). Bits NEWDAT and 846 * INTPND are set for this message object indicating that a new message 847 * has arrived. To work-around this issue, we keep two groups of message 848 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 849 * 850 * To ensure in-order frame reception we use the following 851 * approach while re-activating a message object to receive further 852 * frames: 853 * - if the current message object number is lower than 854 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 855 * the INTPND bit. 856 * - if the current message object number is equal to 857 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 858 * receive message objects. 859 * - if the current message object number is greater than 860 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 861 * only this message object. 862 */ 863static int c_can_do_rx_poll(struct net_device *dev, int quota) 864{ 865 struct c_can_priv *priv = netdev_priv(dev); 866 u32 pkts = 0, pend = 0, toread, n; 867 868 /* 869 * It is faster to read only one 16bit register. This is only possible 870 * for a maximum number of 16 objects. 871 */ 872 BUILD_BUG_ON_MSG(C_CAN_MSG_OBJ_RX_LAST > 16, 873 "Implementation does not support more message objects than 16"); 874 875 while (quota > 0) { 876 if (!pend) { 877 pend = priv->read_reg(priv, C_CAN_INTPND1_REG); 878 if (!pend) 879 break; 880 /* 881 * If the pending field has a gap, handle the 882 * bits above the gap first. 883 */ 884 toread = c_can_adjust_pending(pend); 885 } else { 886 toread = pend; 887 } 888 /* Remove the bits from pend */ 889 pend &= ~toread; 890 /* Read the objects */ 891 n = c_can_read_objects(dev, priv, toread, quota); 892 pkts += n; 893 quota -= n; 894 } 895 896 if (pkts) 897 can_led_event(dev, CAN_LED_EVENT_RX); 898 899 return pkts; 900} 901 902static int c_can_handle_state_change(struct net_device *dev, 903 enum c_can_bus_error_types error_type) 904{ 905 unsigned int reg_err_counter; 906 unsigned int rx_err_passive; 907 struct c_can_priv *priv = netdev_priv(dev); 908 struct net_device_stats *stats = &dev->stats; 909 struct can_frame *cf; 910 struct sk_buff *skb; 911 struct can_berr_counter bec; 912 913 switch (error_type) { 914 case C_CAN_ERROR_WARNING: 915 /* error warning state */ 916 priv->can.can_stats.error_warning++; 917 priv->can.state = CAN_STATE_ERROR_WARNING; 918 break; 919 case C_CAN_ERROR_PASSIVE: 920 /* error passive state */ 921 priv->can.can_stats.error_passive++; 922 priv->can.state = CAN_STATE_ERROR_PASSIVE; 923 break; 924 case C_CAN_BUS_OFF: 925 /* bus-off state */ 926 priv->can.state = CAN_STATE_BUS_OFF; 927 can_bus_off(dev); 928 break; 929 default: 930 break; 931 } 932 933 /* propagate the error condition to the CAN stack */ 934 skb = alloc_can_err_skb(dev, &cf); 935 if (unlikely(!skb)) 936 return 0; 937 938 __c_can_get_berr_counter(dev, &bec); 939 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 940 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 941 ERR_CNT_RP_SHIFT; 942 943 switch (error_type) { 944 case C_CAN_ERROR_WARNING: 945 /* error warning state */ 946 cf->can_id |= CAN_ERR_CRTL; 947 cf->data[1] = (bec.txerr > bec.rxerr) ? 948 CAN_ERR_CRTL_TX_WARNING : 949 CAN_ERR_CRTL_RX_WARNING; 950 cf->data[6] = bec.txerr; 951 cf->data[7] = bec.rxerr; 952 953 break; 954 case C_CAN_ERROR_PASSIVE: 955 /* error passive state */ 956 cf->can_id |= CAN_ERR_CRTL; 957 if (rx_err_passive) 958 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 959 if (bec.txerr > 127) 960 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 961 962 cf->data[6] = bec.txerr; 963 cf->data[7] = bec.rxerr; 964 break; 965 case C_CAN_BUS_OFF: 966 /* bus-off state */ 967 cf->can_id |= CAN_ERR_BUSOFF; 968 can_bus_off(dev); 969 break; 970 default: 971 break; 972 } 973 974 stats->rx_packets++; 975 stats->rx_bytes += cf->can_dlc; 976 netif_receive_skb(skb); 977 978 return 1; 979} 980 981static int c_can_handle_bus_err(struct net_device *dev, 982 enum c_can_lec_type lec_type) 983{ 984 struct c_can_priv *priv = netdev_priv(dev); 985 struct net_device_stats *stats = &dev->stats; 986 struct can_frame *cf; 987 struct sk_buff *skb; 988 989 /* 990 * early exit if no lec update or no error. 991 * no lec update means that no CAN bus event has been detected 992 * since CPU wrote 0x7 value to status reg. 993 */ 994 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 995 return 0; 996 997 if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 998 return 0; 999 1000 /* common for all type of bus errors */ 1001 priv->can.can_stats.bus_error++; 1002 stats->rx_errors++; 1003 1004 /* propagate the error condition to the CAN stack */ 1005 skb = alloc_can_err_skb(dev, &cf); 1006 if (unlikely(!skb)) 1007 return 0; 1008 1009 /* 1010 * check for 'last error code' which tells us the 1011 * type of the last error to occur on the CAN bus 1012 */ 1013 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1014 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 1015 1016 switch (lec_type) { 1017 case LEC_STUFF_ERROR: 1018 netdev_dbg(dev, "stuff error\n"); 1019 cf->data[2] |= CAN_ERR_PROT_STUFF; 1020 break; 1021 case LEC_FORM_ERROR: 1022 netdev_dbg(dev, "form error\n"); 1023 cf->data[2] |= CAN_ERR_PROT_FORM; 1024 break; 1025 case LEC_ACK_ERROR: 1026 netdev_dbg(dev, "ack error\n"); 1027 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 1028 CAN_ERR_PROT_LOC_ACK_DEL); 1029 break; 1030 case LEC_BIT1_ERROR: 1031 netdev_dbg(dev, "bit1 error\n"); 1032 cf->data[2] |= CAN_ERR_PROT_BIT1; 1033 break; 1034 case LEC_BIT0_ERROR: 1035 netdev_dbg(dev, "bit0 error\n"); 1036 cf->data[2] |= CAN_ERR_PROT_BIT0; 1037 break; 1038 case LEC_CRC_ERROR: 1039 netdev_dbg(dev, "CRC error\n"); 1040 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 1041 CAN_ERR_PROT_LOC_CRC_DEL); 1042 break; 1043 default: 1044 break; 1045 } 1046 1047 /* set a `lec` value so that we can check for updates later */ 1048 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 1049 1050 stats->rx_packets++; 1051 stats->rx_bytes += cf->can_dlc; 1052 netif_receive_skb(skb); 1053 return 1; 1054} 1055 1056static int c_can_poll(struct napi_struct *napi, int quota) 1057{ 1058 u16 irqstatus; 1059 int work_done = 0; 1060 struct net_device *dev = napi->dev; 1061 struct c_can_priv *priv = netdev_priv(dev); 1062 1063 irqstatus = priv->irqstatus; 1064 if (!irqstatus) 1065 goto end; 1066 1067 /* status events have the highest priority */ 1068 if (irqstatus == STATUS_INTERRUPT) { 1069 priv->current_status = priv->read_reg(priv, 1070 C_CAN_STS_REG); 1071 1072 /* handle Tx/Rx events */ 1073 if (priv->current_status & STATUS_TXOK) 1074 priv->write_reg(priv, C_CAN_STS_REG, 1075 priv->current_status & ~STATUS_TXOK); 1076 1077 if (priv->current_status & STATUS_RXOK) 1078 priv->write_reg(priv, C_CAN_STS_REG, 1079 priv->current_status & ~STATUS_RXOK); 1080 1081 /* handle state changes */ 1082 if ((priv->current_status & STATUS_EWARN) && 1083 (!(priv->last_status & STATUS_EWARN))) { 1084 netdev_dbg(dev, "entered error warning state\n"); 1085 work_done += c_can_handle_state_change(dev, 1086 C_CAN_ERROR_WARNING); 1087 } 1088 if ((priv->current_status & STATUS_EPASS) && 1089 (!(priv->last_status & STATUS_EPASS))) { 1090 netdev_dbg(dev, "entered error passive state\n"); 1091 work_done += c_can_handle_state_change(dev, 1092 C_CAN_ERROR_PASSIVE); 1093 } 1094 if ((priv->current_status & STATUS_BOFF) && 1095 (!(priv->last_status & STATUS_BOFF))) { 1096 netdev_dbg(dev, "entered bus off state\n"); 1097 work_done += c_can_handle_state_change(dev, 1098 C_CAN_BUS_OFF); 1099 goto end; 1100 } 1101 1102 /* handle bus recovery events */ 1103 if ((!(priv->current_status & STATUS_BOFF)) && 1104 (priv->last_status & STATUS_BOFF)) { 1105 netdev_dbg(dev, "left bus off state\n"); 1106 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1107 } 1108 if ((!(priv->current_status & STATUS_EPASS)) && 1109 (priv->last_status & STATUS_EPASS)) { 1110 netdev_dbg(dev, "left error passive state\n"); 1111 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1112 } 1113 1114 priv->last_status = priv->current_status; 1115 1116 /* handle lec errors on the bus */ 1117 work_done += c_can_handle_bus_err(dev, 1118 priv->current_status & LEC_MASK); 1119 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1120 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1121 /* handle events corresponding to receive message objects */ 1122 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1123 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1124 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1125 /* handle events corresponding to transmit message objects */ 1126 c_can_do_tx(dev); 1127 } 1128 1129end: 1130 if (work_done < quota) { 1131 napi_complete(napi); 1132 /* enable all IRQs if we are not in bus off state */ 1133 if (priv->can.state != CAN_STATE_BUS_OFF) 1134 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1135 } 1136 1137 return work_done; 1138} 1139 1140static irqreturn_t c_can_isr(int irq, void *dev_id) 1141{ 1142 struct net_device *dev = (struct net_device *)dev_id; 1143 struct c_can_priv *priv = netdev_priv(dev); 1144 1145 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1146 if (!priv->irqstatus) 1147 return IRQ_NONE; 1148 1149 /* disable all interrupts and schedule the NAPI */ 1150 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1151 napi_schedule(&priv->napi); 1152 1153 return IRQ_HANDLED; 1154} 1155 1156static int c_can_open(struct net_device *dev) 1157{ 1158 int err; 1159 struct c_can_priv *priv = netdev_priv(dev); 1160 1161 c_can_pm_runtime_get_sync(priv); 1162 c_can_reset_ram(priv, true); 1163 1164 /* open the can device */ 1165 err = open_candev(dev); 1166 if (err) { 1167 netdev_err(dev, "failed to open can device\n"); 1168 goto exit_open_fail; 1169 } 1170 1171 /* register interrupt handler */ 1172 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1173 dev); 1174 if (err < 0) { 1175 netdev_err(dev, "failed to request interrupt\n"); 1176 goto exit_irq_fail; 1177 } 1178 1179 /* start the c_can controller */ 1180 err = c_can_start(dev); 1181 if (err) 1182 goto exit_start_fail; 1183 1184 can_led_event(dev, CAN_LED_EVENT_OPEN); 1185 1186 napi_enable(&priv->napi); 1187 /* enable status change, error and module interrupts */ 1188 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1189 netif_start_queue(dev); 1190 1191 return 0; 1192 1193exit_start_fail: 1194 free_irq(dev->irq, dev); 1195exit_irq_fail: 1196 close_candev(dev); 1197exit_open_fail: 1198 c_can_reset_ram(priv, false); 1199 c_can_pm_runtime_put_sync(priv); 1200 return err; 1201} 1202 1203static int c_can_close(struct net_device *dev) 1204{ 1205 struct c_can_priv *priv = netdev_priv(dev); 1206 1207 netif_stop_queue(dev); 1208 napi_disable(&priv->napi); 1209 c_can_stop(dev); 1210 free_irq(dev->irq, dev); 1211 close_candev(dev); 1212 1213 c_can_reset_ram(priv, false); 1214 c_can_pm_runtime_put_sync(priv); 1215 1216 can_led_event(dev, CAN_LED_EVENT_STOP); 1217 1218 return 0; 1219} 1220 1221struct net_device *alloc_c_can_dev(void) 1222{ 1223 struct net_device *dev; 1224 struct c_can_priv *priv; 1225 1226 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1227 if (!dev) 1228 return NULL; 1229 1230 priv = netdev_priv(dev); 1231 spin_lock_init(&priv->xmit_lock); 1232 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1233 1234 priv->dev = dev; 1235 priv->can.bittiming_const = &c_can_bittiming_const; 1236 priv->can.do_set_mode = c_can_set_mode; 1237 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1238 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1239 CAN_CTRLMODE_LISTENONLY | 1240 CAN_CTRLMODE_BERR_REPORTING; 1241 1242 return dev; 1243} 1244EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1245 1246#ifdef CONFIG_PM 1247int c_can_power_down(struct net_device *dev) 1248{ 1249 u32 val; 1250 unsigned long time_out; 1251 struct c_can_priv *priv = netdev_priv(dev); 1252 1253 if (!(dev->flags & IFF_UP)) 1254 return 0; 1255 1256 WARN_ON(priv->type != BOSCH_D_CAN); 1257 1258 /* set PDR value so the device goes to power down mode */ 1259 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1260 val |= CONTROL_EX_PDR; 1261 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1262 1263 /* Wait for the PDA bit to get set */ 1264 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1265 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1266 time_after(time_out, jiffies)) 1267 cpu_relax(); 1268 1269 if (time_after(jiffies, time_out)) 1270 return -ETIMEDOUT; 1271 1272 c_can_stop(dev); 1273 1274 c_can_reset_ram(priv, false); 1275 c_can_pm_runtime_put_sync(priv); 1276 1277 return 0; 1278} 1279EXPORT_SYMBOL_GPL(c_can_power_down); 1280 1281int c_can_power_up(struct net_device *dev) 1282{ 1283 u32 val; 1284 unsigned long time_out; 1285 struct c_can_priv *priv = netdev_priv(dev); 1286 int ret; 1287 1288 if (!(dev->flags & IFF_UP)) 1289 return 0; 1290 1291 WARN_ON(priv->type != BOSCH_D_CAN); 1292 1293 c_can_pm_runtime_get_sync(priv); 1294 c_can_reset_ram(priv, true); 1295 1296 /* Clear PDR and INIT bits */ 1297 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1298 val &= ~CONTROL_EX_PDR; 1299 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1300 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1301 val &= ~CONTROL_INIT; 1302 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1303 1304 /* Wait for the PDA bit to get clear */ 1305 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1306 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1307 time_after(time_out, jiffies)) 1308 cpu_relax(); 1309 1310 if (time_after(jiffies, time_out)) 1311 return -ETIMEDOUT; 1312 1313 ret = c_can_start(dev); 1314 if (!ret) 1315 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1316 1317 return ret; 1318} 1319EXPORT_SYMBOL_GPL(c_can_power_up); 1320#endif 1321 1322void free_c_can_dev(struct net_device *dev) 1323{ 1324 struct c_can_priv *priv = netdev_priv(dev); 1325 1326 netif_napi_del(&priv->napi); 1327 free_candev(dev); 1328} 1329EXPORT_SYMBOL_GPL(free_c_can_dev); 1330 1331static const struct net_device_ops c_can_netdev_ops = { 1332 .ndo_open = c_can_open, 1333 .ndo_stop = c_can_close, 1334 .ndo_start_xmit = c_can_start_xmit, 1335 .ndo_change_mtu = can_change_mtu, 1336}; 1337 1338int register_c_can_dev(struct net_device *dev) 1339{ 1340 struct c_can_priv *priv = netdev_priv(dev); 1341 int err; 1342 1343 c_can_pm_runtime_enable(priv); 1344 1345 dev->flags |= IFF_ECHO; /* we support local echo */ 1346 dev->netdev_ops = &c_can_netdev_ops; 1347 1348 err = register_candev(dev); 1349 if (err) 1350 c_can_pm_runtime_disable(priv); 1351 else 1352 devm_can_led_init(dev); 1353 1354 return err; 1355} 1356EXPORT_SYMBOL_GPL(register_c_can_dev); 1357 1358void unregister_c_can_dev(struct net_device *dev) 1359{ 1360 struct c_can_priv *priv = netdev_priv(dev); 1361 1362 unregister_candev(dev); 1363 1364 c_can_pm_runtime_disable(priv); 1365} 1366EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1367 1368MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1369MODULE_LICENSE("GPL v2"); 1370MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1371