c_can.c revision 2bd3bc4e8472424f1a6009825397639a8968920a
1/* 2 * CAN bus driver for Bosch C_CAN controller 3 * 4 * Copyright (C) 2010 ST Microelectronics 5 * Bhupesh Sharma <bhupesh.sharma@st.com> 6 * 7 * Borrowed heavily from the C_CAN driver originally written by: 8 * Copyright (C) 2007 9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de> 10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch> 11 * 12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver 13 * written by: 14 * Copyright 15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de> 17 * 18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. 19 * Bosch C_CAN user manual can be obtained from: 20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ 21 * users_manual_c_can.pdf 22 * 23 * This file is licensed under the terms of the GNU General Public 24 * License version 2. This program is licensed "as is" without any 25 * warranty of any kind, whether express or implied. 26 */ 27 28#include <linux/kernel.h> 29#include <linux/module.h> 30#include <linux/interrupt.h> 31#include <linux/delay.h> 32#include <linux/netdevice.h> 33#include <linux/if_arp.h> 34#include <linux/if_ether.h> 35#include <linux/list.h> 36#include <linux/io.h> 37#include <linux/pm_runtime.h> 38 39#include <linux/can.h> 40#include <linux/can/dev.h> 41#include <linux/can/error.h> 42 43#include "c_can.h" 44 45/* Number of interface registers */ 46#define IF_ENUM_REG_LEN 11 47#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) 48 49/* control extension register D_CAN specific */ 50#define CONTROL_EX_PDR BIT(8) 51 52/* control register */ 53#define CONTROL_TEST BIT(7) 54#define CONTROL_CCE BIT(6) 55#define CONTROL_DISABLE_AR BIT(5) 56#define CONTROL_ENABLE_AR (0 << 5) 57#define CONTROL_EIE BIT(3) 58#define CONTROL_SIE BIT(2) 59#define CONTROL_IE BIT(1) 60#define CONTROL_INIT BIT(0) 61 62/* test register */ 63#define TEST_RX BIT(7) 64#define TEST_TX1 BIT(6) 65#define TEST_TX2 BIT(5) 66#define TEST_LBACK BIT(4) 67#define TEST_SILENT BIT(3) 68#define TEST_BASIC BIT(2) 69 70/* status register */ 71#define STATUS_PDA BIT(10) 72#define STATUS_BOFF BIT(7) 73#define STATUS_EWARN BIT(6) 74#define STATUS_EPASS BIT(5) 75#define STATUS_RXOK BIT(4) 76#define STATUS_TXOK BIT(3) 77 78/* error counter register */ 79#define ERR_CNT_TEC_MASK 0xff 80#define ERR_CNT_TEC_SHIFT 0 81#define ERR_CNT_REC_SHIFT 8 82#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) 83#define ERR_CNT_RP_SHIFT 15 84#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) 85 86/* bit-timing register */ 87#define BTR_BRP_MASK 0x3f 88#define BTR_BRP_SHIFT 0 89#define BTR_SJW_SHIFT 6 90#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) 91#define BTR_TSEG1_SHIFT 8 92#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) 93#define BTR_TSEG2_SHIFT 12 94#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) 95 96/* brp extension register */ 97#define BRP_EXT_BRPE_MASK 0x0f 98#define BRP_EXT_BRPE_SHIFT 0 99 100/* IFx command request */ 101#define IF_COMR_BUSY BIT(15) 102 103/* IFx command mask */ 104#define IF_COMM_WR BIT(7) 105#define IF_COMM_MASK BIT(6) 106#define IF_COMM_ARB BIT(5) 107#define IF_COMM_CONTROL BIT(4) 108#define IF_COMM_CLR_INT_PND BIT(3) 109#define IF_COMM_TXRQST BIT(2) 110#define IF_COMM_DATAA BIT(1) 111#define IF_COMM_DATAB BIT(0) 112#define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \ 113 IF_COMM_CONTROL | IF_COMM_TXRQST | \ 114 IF_COMM_DATAA | IF_COMM_DATAB) 115 116/* IFx arbitration */ 117#define IF_ARB_MSGVAL BIT(15) 118#define IF_ARB_MSGXTD BIT(14) 119#define IF_ARB_TRANSMIT BIT(13) 120 121/* IFx message control */ 122#define IF_MCONT_NEWDAT BIT(15) 123#define IF_MCONT_MSGLST BIT(14) 124#define IF_MCONT_CLR_MSGLST (0 << 14) 125#define IF_MCONT_INTPND BIT(13) 126#define IF_MCONT_UMASK BIT(12) 127#define IF_MCONT_TXIE BIT(11) 128#define IF_MCONT_RXIE BIT(10) 129#define IF_MCONT_RMTEN BIT(9) 130#define IF_MCONT_TXRQST BIT(8) 131#define IF_MCONT_EOB BIT(7) 132#define IF_MCONT_DLC_MASK 0xf 133 134/* 135 * IFx register masks: 136 * allow easy operation on 16-bit registers when the 137 * argument is 32-bit instead 138 */ 139#define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF) 140#define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16) 141 142/* message object split */ 143#define C_CAN_NO_OF_OBJECTS 32 144#define C_CAN_MSG_OBJ_RX_NUM 16 145#define C_CAN_MSG_OBJ_TX_NUM 16 146 147#define C_CAN_MSG_OBJ_RX_FIRST 1 148#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \ 149 C_CAN_MSG_OBJ_RX_NUM - 1) 150 151#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1) 152#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \ 153 C_CAN_MSG_OBJ_TX_NUM - 1) 154 155#define C_CAN_MSG_OBJ_RX_SPLIT 9 156#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1) 157 158#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1) 159#define RECEIVE_OBJECT_BITS 0x0000ffff 160 161/* status interrupt */ 162#define STATUS_INTERRUPT 0x8000 163 164/* global interrupt masks */ 165#define ENABLE_ALL_INTERRUPTS 1 166#define DISABLE_ALL_INTERRUPTS 0 167 168/* minimum timeout for checking BUSY status */ 169#define MIN_TIMEOUT_VALUE 6 170 171/* Wait for ~1 sec for INIT bit */ 172#define INIT_WAIT_MS 1000 173 174/* napi related */ 175#define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM 176 177/* c_can lec values */ 178enum c_can_lec_type { 179 LEC_NO_ERROR = 0, 180 LEC_STUFF_ERROR, 181 LEC_FORM_ERROR, 182 LEC_ACK_ERROR, 183 LEC_BIT1_ERROR, 184 LEC_BIT0_ERROR, 185 LEC_CRC_ERROR, 186 LEC_UNUSED, 187}; 188 189/* 190 * c_can error types: 191 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported 192 */ 193enum c_can_bus_error_types { 194 C_CAN_NO_ERROR = 0, 195 C_CAN_BUS_OFF, 196 C_CAN_ERROR_WARNING, 197 C_CAN_ERROR_PASSIVE, 198}; 199 200static const struct can_bittiming_const c_can_bittiming_const = { 201 .name = KBUILD_MODNAME, 202 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ 203 .tseg1_max = 16, 204 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ 205 .tseg2_max = 8, 206 .sjw_max = 4, 207 .brp_min = 1, 208 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ 209 .brp_inc = 1, 210}; 211 212static inline void c_can_pm_runtime_enable(const struct c_can_priv *priv) 213{ 214 if (priv->device) 215 pm_runtime_enable(priv->device); 216} 217 218static inline void c_can_pm_runtime_disable(const struct c_can_priv *priv) 219{ 220 if (priv->device) 221 pm_runtime_disable(priv->device); 222} 223 224static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) 225{ 226 if (priv->device) 227 pm_runtime_get_sync(priv->device); 228} 229 230static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) 231{ 232 if (priv->device) 233 pm_runtime_put_sync(priv->device); 234} 235 236static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) 237{ 238 if (priv->raminit) 239 priv->raminit(priv, enable); 240} 241 242static inline int get_tx_next_msg_obj(const struct c_can_priv *priv) 243{ 244 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) + 245 C_CAN_MSG_OBJ_TX_FIRST; 246} 247 248static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv) 249{ 250 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) + 251 C_CAN_MSG_OBJ_TX_FIRST; 252} 253 254static u32 c_can_read_reg32(struct c_can_priv *priv, enum reg index) 255{ 256 u32 val = priv->read_reg(priv, index); 257 val |= ((u32) priv->read_reg(priv, index + 1)) << 16; 258 return val; 259} 260 261static void c_can_enable_all_interrupts(struct c_can_priv *priv, 262 int enable) 263{ 264 unsigned int cntrl_save = priv->read_reg(priv, 265 C_CAN_CTRL_REG); 266 267 if (enable) 268 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE); 269 else 270 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE); 271 272 priv->write_reg(priv, C_CAN_CTRL_REG, cntrl_save); 273} 274 275static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface) 276{ 277 int count = MIN_TIMEOUT_VALUE; 278 279 while (count && priv->read_reg(priv, 280 C_CAN_IFACE(COMREQ_REG, iface)) & 281 IF_COMR_BUSY) { 282 count--; 283 udelay(1); 284 } 285 286 if (!count) 287 return 1; 288 289 return 0; 290} 291 292static inline void c_can_object_get(struct net_device *dev, 293 int iface, int objno, int mask) 294{ 295 struct c_can_priv *priv = netdev_priv(dev); 296 297 /* 298 * As per specs, after writting the message object number in the 299 * IF command request register the transfer b/w interface 300 * register and message RAM must be complete in 6 CAN-CLK 301 * period. 302 */ 303 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 304 IFX_WRITE_LOW_16BIT(mask)); 305 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 306 IFX_WRITE_LOW_16BIT(objno)); 307 308 if (c_can_msg_obj_is_busy(priv, iface)) 309 netdev_err(dev, "timed out in object get\n"); 310} 311 312static inline void c_can_object_put(struct net_device *dev, 313 int iface, int objno, int mask) 314{ 315 struct c_can_priv *priv = netdev_priv(dev); 316 317 /* 318 * As per specs, after writting the message object number in the 319 * IF command request register the transfer b/w interface 320 * register and message RAM must be complete in 6 CAN-CLK 321 * period. 322 */ 323 priv->write_reg(priv, C_CAN_IFACE(COMMSK_REG, iface), 324 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask))); 325 priv->write_reg(priv, C_CAN_IFACE(COMREQ_REG, iface), 326 IFX_WRITE_LOW_16BIT(objno)); 327 328 if (c_can_msg_obj_is_busy(priv, iface)) 329 netdev_err(dev, "timed out in object put\n"); 330} 331 332static void c_can_write_msg_object(struct net_device *dev, 333 int iface, struct can_frame *frame, int objno) 334{ 335 int i; 336 u16 flags = 0; 337 unsigned int id; 338 struct c_can_priv *priv = netdev_priv(dev); 339 340 if (!(frame->can_id & CAN_RTR_FLAG)) 341 flags |= IF_ARB_TRANSMIT; 342 343 if (frame->can_id & CAN_EFF_FLAG) { 344 id = frame->can_id & CAN_EFF_MASK; 345 flags |= IF_ARB_MSGXTD; 346 } else 347 id = ((frame->can_id & CAN_SFF_MASK) << 18); 348 349 flags |= IF_ARB_MSGVAL; 350 351 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 352 IFX_WRITE_LOW_16BIT(id)); 353 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), flags | 354 IFX_WRITE_HIGH_16BIT(id)); 355 356 for (i = 0; i < frame->can_dlc; i += 2) { 357 priv->write_reg(priv, C_CAN_IFACE(DATA1_REG, iface) + i / 2, 358 frame->data[i] | (frame->data[i + 1] << 8)); 359 } 360 361 /* enable interrupt for this message object */ 362 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 363 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB | 364 frame->can_dlc); 365 c_can_object_put(dev, iface, objno, IF_COMM_ALL); 366} 367 368static inline void c_can_mark_rx_msg_obj(struct net_device *dev, 369 int iface, int ctrl_mask, 370 int obj) 371{ 372 struct c_can_priv *priv = netdev_priv(dev); 373 374 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 375 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND)); 376 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 377 378} 379 380static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev, 381 int iface, 382 int ctrl_mask) 383{ 384 int i; 385 struct c_can_priv *priv = netdev_priv(dev); 386 387 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) { 388 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 389 ctrl_mask & ~(IF_MCONT_MSGLST | 390 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 391 c_can_object_put(dev, iface, i, IF_COMM_CONTROL); 392 } 393} 394 395static inline void c_can_activate_rx_msg_obj(struct net_device *dev, 396 int iface, int ctrl_mask, 397 int obj) 398{ 399 struct c_can_priv *priv = netdev_priv(dev); 400 401 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 402 ctrl_mask & ~(IF_MCONT_MSGLST | 403 IF_MCONT_INTPND | IF_MCONT_NEWDAT)); 404 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL); 405} 406 407static void c_can_handle_lost_msg_obj(struct net_device *dev, 408 int iface, int objno) 409{ 410 struct c_can_priv *priv = netdev_priv(dev); 411 struct net_device_stats *stats = &dev->stats; 412 struct sk_buff *skb; 413 struct can_frame *frame; 414 415 netdev_err(dev, "msg lost in buffer %d\n", objno); 416 417 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 418 419 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 420 IF_MCONT_CLR_MSGLST); 421 422 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL); 423 424 /* create an error msg */ 425 skb = alloc_can_err_skb(dev, &frame); 426 if (unlikely(!skb)) 427 return; 428 429 frame->can_id |= CAN_ERR_CRTL; 430 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 431 stats->rx_errors++; 432 stats->rx_over_errors++; 433 434 netif_receive_skb(skb); 435} 436 437static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl) 438{ 439 u16 flags, data; 440 int i; 441 unsigned int val; 442 struct c_can_priv *priv = netdev_priv(dev); 443 struct net_device_stats *stats = &dev->stats; 444 struct sk_buff *skb; 445 struct can_frame *frame; 446 447 skb = alloc_can_skb(dev, &frame); 448 if (!skb) { 449 stats->rx_dropped++; 450 return -ENOMEM; 451 } 452 453 frame->can_dlc = get_can_dlc(ctrl & 0x0F); 454 455 flags = priv->read_reg(priv, C_CAN_IFACE(ARB2_REG, iface)); 456 val = priv->read_reg(priv, C_CAN_IFACE(ARB1_REG, iface)) | 457 (flags << 16); 458 459 if (flags & IF_ARB_MSGXTD) 460 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG; 461 else 462 frame->can_id = (val >> 18) & CAN_SFF_MASK; 463 464 if (flags & IF_ARB_TRANSMIT) 465 frame->can_id |= CAN_RTR_FLAG; 466 else { 467 for (i = 0; i < frame->can_dlc; i += 2) { 468 data = priv->read_reg(priv, 469 C_CAN_IFACE(DATA1_REG, iface) + i / 2); 470 frame->data[i] = data; 471 frame->data[i + 1] = data >> 8; 472 } 473 } 474 475 netif_receive_skb(skb); 476 477 stats->rx_packets++; 478 stats->rx_bytes += frame->can_dlc; 479 480 return 0; 481} 482 483static void c_can_setup_receive_object(struct net_device *dev, int iface, 484 int objno, unsigned int mask, 485 unsigned int id, unsigned int mcont) 486{ 487 struct c_can_priv *priv = netdev_priv(dev); 488 489 priv->write_reg(priv, C_CAN_IFACE(MASK1_REG, iface), 490 IFX_WRITE_LOW_16BIT(mask)); 491 492 /* According to C_CAN documentation, the reserved bit 493 * in IFx_MASK2 register is fixed 1 494 */ 495 priv->write_reg(priv, C_CAN_IFACE(MASK2_REG, iface), 496 IFX_WRITE_HIGH_16BIT(mask) | BIT(13)); 497 498 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 499 IFX_WRITE_LOW_16BIT(id)); 500 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 501 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id))); 502 503 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); 504 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST); 505 506 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 507 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 508} 509 510static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno) 511{ 512 struct c_can_priv *priv = netdev_priv(dev); 513 514 priv->write_reg(priv, C_CAN_IFACE(ARB1_REG, iface), 0); 515 priv->write_reg(priv, C_CAN_IFACE(ARB2_REG, iface), 0); 516 priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); 517 518 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL); 519 520 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno, 521 c_can_read_reg32(priv, C_CAN_MSGVAL1_REG)); 522} 523 524static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno) 525{ 526 int val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 527 528 /* 529 * as transmission request register's bit n-1 corresponds to 530 * message object n, we need to handle the same properly. 531 */ 532 if (val & (1 << (objno - 1))) 533 return 1; 534 535 return 0; 536} 537 538static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, 539 struct net_device *dev) 540{ 541 u32 msg_obj_no; 542 struct c_can_priv *priv = netdev_priv(dev); 543 struct can_frame *frame = (struct can_frame *)skb->data; 544 545 if (can_dropped_invalid_skb(dev, skb)) 546 return NETDEV_TX_OK; 547 548 msg_obj_no = get_tx_next_msg_obj(priv); 549 550 /* prepare message object for transmission */ 551 c_can_write_msg_object(dev, 0, frame, msg_obj_no); 552 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 553 554 /* 555 * we have to stop the queue in case of a wrap around or 556 * if the next TX message object is still in use 557 */ 558 priv->tx_next++; 559 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) || 560 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0) 561 netif_stop_queue(dev); 562 563 return NETDEV_TX_OK; 564} 565 566static int c_can_set_bittiming(struct net_device *dev) 567{ 568 unsigned int reg_btr, reg_brpe, ctrl_save; 569 u8 brp, brpe, sjw, tseg1, tseg2; 570 u32 ten_bit_brp; 571 struct c_can_priv *priv = netdev_priv(dev); 572 const struct can_bittiming *bt = &priv->can.bittiming; 573 574 /* c_can provides a 6-bit brp and 4-bit brpe fields */ 575 ten_bit_brp = bt->brp - 1; 576 brp = ten_bit_brp & BTR_BRP_MASK; 577 brpe = ten_bit_brp >> 6; 578 579 sjw = bt->sjw - 1; 580 tseg1 = bt->prop_seg + bt->phase_seg1 - 1; 581 tseg2 = bt->phase_seg2 - 1; 582 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | 583 (tseg2 << BTR_TSEG2_SHIFT); 584 reg_brpe = brpe & BRP_EXT_BRPE_MASK; 585 586 netdev_info(dev, 587 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); 588 589 ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); 590 priv->write_reg(priv, C_CAN_CTRL_REG, 591 ctrl_save | CONTROL_CCE | CONTROL_INIT); 592 priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); 593 priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); 594 priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); 595 596 return 0; 597} 598 599/* 600 * Configure C_CAN message objects for Tx and Rx purposes: 601 * C_CAN provides a total of 32 message objects that can be configured 602 * either for Tx or Rx purposes. Here the first 16 message objects are used as 603 * a reception FIFO. The end of reception FIFO is signified by the EoB bit 604 * being SET. The remaining 16 message objects are kept aside for Tx purposes. 605 * See user guide document for further details on configuring message 606 * objects. 607 */ 608static void c_can_configure_msg_objects(struct net_device *dev) 609{ 610 int i; 611 612 /* first invalidate all message objects */ 613 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++) 614 c_can_inval_msg_object(dev, 0, i); 615 616 /* setup receive message objects */ 617 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++) 618 c_can_setup_receive_object(dev, 0, i, 0, 0, 619 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB); 620 621 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0, 622 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK); 623} 624 625/* 626 * Configure C_CAN chip: 627 * - enable/disable auto-retransmission 628 * - set operating mode 629 * - configure message objects 630 */ 631static void c_can_chip_config(struct net_device *dev) 632{ 633 struct c_can_priv *priv = netdev_priv(dev); 634 635 /* enable automatic retransmission */ 636 priv->write_reg(priv, C_CAN_CTRL_REG, 637 CONTROL_ENABLE_AR); 638 639 if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && 640 (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { 641 /* loopback + silent mode : useful for hot self-test */ 642 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 643 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 644 priv->write_reg(priv, C_CAN_TEST_REG, 645 TEST_LBACK | TEST_SILENT); 646 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 647 /* loopback mode : useful for self-test function */ 648 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 649 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 650 priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); 651 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { 652 /* silent mode : bus-monitoring mode */ 653 priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_EIE | 654 CONTROL_SIE | CONTROL_IE | CONTROL_TEST); 655 priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); 656 } else 657 /* normal mode*/ 658 priv->write_reg(priv, C_CAN_CTRL_REG, 659 CONTROL_EIE | CONTROL_SIE | CONTROL_IE); 660 661 /* configure message objects */ 662 c_can_configure_msg_objects(dev); 663 664 /* set a `lec` value so that we can check for updates later */ 665 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 666 667 /* set bittiming params */ 668 c_can_set_bittiming(dev); 669} 670 671static void c_can_start(struct net_device *dev) 672{ 673 struct c_can_priv *priv = netdev_priv(dev); 674 675 /* basic c_can configuration */ 676 c_can_chip_config(dev); 677 678 priv->can.state = CAN_STATE_ERROR_ACTIVE; 679 680 /* reset tx helper pointers */ 681 priv->tx_next = priv->tx_echo = 0; 682 683 /* enable status change, error and module interrupts */ 684 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 685} 686 687static void c_can_stop(struct net_device *dev) 688{ 689 struct c_can_priv *priv = netdev_priv(dev); 690 691 /* disable all interrupts */ 692 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 693 694 /* set the state as STOPPED */ 695 priv->can.state = CAN_STATE_STOPPED; 696} 697 698static int c_can_set_mode(struct net_device *dev, enum can_mode mode) 699{ 700 switch (mode) { 701 case CAN_MODE_START: 702 c_can_start(dev); 703 netif_wake_queue(dev); 704 break; 705 default: 706 return -EOPNOTSUPP; 707 } 708 709 return 0; 710} 711 712static int c_can_get_berr_counter(const struct net_device *dev, 713 struct can_berr_counter *bec) 714{ 715 unsigned int reg_err_counter; 716 struct c_can_priv *priv = netdev_priv(dev); 717 718 c_can_pm_runtime_get_sync(priv); 719 720 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 721 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> 722 ERR_CNT_REC_SHIFT; 723 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; 724 725 c_can_pm_runtime_put_sync(priv); 726 727 return 0; 728} 729 730/* 731 * theory of operation: 732 * 733 * priv->tx_echo holds the number of the oldest can_frame put for 734 * transmission into the hardware, but not yet ACKed by the CAN tx 735 * complete IRQ. 736 * 737 * We iterate from priv->tx_echo to priv->tx_next and check if the 738 * packet has been transmitted, echo it back to the CAN framework. 739 * If we discover a not yet transmitted packet, stop looking for more. 740 */ 741static void c_can_do_tx(struct net_device *dev) 742{ 743 u32 val; 744 u32 msg_obj_no; 745 struct c_can_priv *priv = netdev_priv(dev); 746 struct net_device_stats *stats = &dev->stats; 747 748 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 749 msg_obj_no = get_tx_echo_msg_obj(priv); 750 val = c_can_read_reg32(priv, C_CAN_TXRQST1_REG); 751 if (!(val & (1 << (msg_obj_no - 1)))) { 752 can_get_echo_skb(dev, 753 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST); 754 stats->tx_bytes += priv->read_reg(priv, 755 C_CAN_IFACE(MSGCTRL_REG, 0)) 756 & IF_MCONT_DLC_MASK; 757 stats->tx_packets++; 758 c_can_inval_msg_object(dev, 0, msg_obj_no); 759 } else { 760 break; 761 } 762 } 763 764 /* restart queue if wrap-up or if queue stalled on last pkt */ 765 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) || 766 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0)) 767 netif_wake_queue(dev); 768} 769 770/* 771 * theory of operation: 772 * 773 * c_can core saves a received CAN message into the first free message 774 * object it finds free (starting with the lowest). Bits NEWDAT and 775 * INTPND are set for this message object indicating that a new message 776 * has arrived. To work-around this issue, we keep two groups of message 777 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT. 778 * 779 * To ensure in-order frame reception we use the following 780 * approach while re-activating a message object to receive further 781 * frames: 782 * - if the current message object number is lower than 783 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing 784 * the INTPND bit. 785 * - if the current message object number is equal to 786 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower 787 * receive message objects. 788 * - if the current message object number is greater than 789 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of 790 * only this message object. 791 */ 792static int c_can_do_rx_poll(struct net_device *dev, int quota) 793{ 794 u32 num_rx_pkts = 0; 795 unsigned int msg_obj, msg_ctrl_save; 796 struct c_can_priv *priv = netdev_priv(dev); 797 u32 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG); 798 799 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST; 800 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0; 801 val = c_can_read_reg32(priv, C_CAN_INTPND1_REG), 802 msg_obj++) { 803 /* 804 * as interrupt pending register's bit n-1 corresponds to 805 * message object n, we need to handle the same properly. 806 */ 807 if (val & (1 << (msg_obj - 1))) { 808 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL & 809 ~IF_COMM_TXRQST); 810 msg_ctrl_save = priv->read_reg(priv, 811 C_CAN_IFACE(MSGCTRL_REG, 0)); 812 813 if (msg_ctrl_save & IF_MCONT_EOB) 814 return num_rx_pkts; 815 816 if (msg_ctrl_save & IF_MCONT_MSGLST) { 817 c_can_handle_lost_msg_obj(dev, 0, msg_obj); 818 num_rx_pkts++; 819 quota--; 820 continue; 821 } 822 823 if (!(msg_ctrl_save & IF_MCONT_NEWDAT)) 824 continue; 825 826 /* read the data from the message object */ 827 c_can_read_msg_object(dev, 0, msg_ctrl_save); 828 829 if (msg_obj < C_CAN_MSG_RX_LOW_LAST) 830 c_can_mark_rx_msg_obj(dev, 0, 831 msg_ctrl_save, msg_obj); 832 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST) 833 /* activate this msg obj */ 834 c_can_activate_rx_msg_obj(dev, 0, 835 msg_ctrl_save, msg_obj); 836 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST) 837 /* activate all lower message objects */ 838 c_can_activate_all_lower_rx_msg_obj(dev, 839 0, msg_ctrl_save); 840 841 num_rx_pkts++; 842 quota--; 843 } 844 } 845 846 return num_rx_pkts; 847} 848 849static inline int c_can_has_and_handle_berr(struct c_can_priv *priv) 850{ 851 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) && 852 (priv->current_status & LEC_UNUSED); 853} 854 855static int c_can_handle_state_change(struct net_device *dev, 856 enum c_can_bus_error_types error_type) 857{ 858 unsigned int reg_err_counter; 859 unsigned int rx_err_passive; 860 struct c_can_priv *priv = netdev_priv(dev); 861 struct net_device_stats *stats = &dev->stats; 862 struct can_frame *cf; 863 struct sk_buff *skb; 864 struct can_berr_counter bec; 865 866 /* propagate the error condition to the CAN stack */ 867 skb = alloc_can_err_skb(dev, &cf); 868 if (unlikely(!skb)) 869 return 0; 870 871 c_can_get_berr_counter(dev, &bec); 872 reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); 873 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> 874 ERR_CNT_RP_SHIFT; 875 876 switch (error_type) { 877 case C_CAN_ERROR_WARNING: 878 /* error warning state */ 879 priv->can.can_stats.error_warning++; 880 priv->can.state = CAN_STATE_ERROR_WARNING; 881 cf->can_id |= CAN_ERR_CRTL; 882 cf->data[1] = (bec.txerr > bec.rxerr) ? 883 CAN_ERR_CRTL_TX_WARNING : 884 CAN_ERR_CRTL_RX_WARNING; 885 cf->data[6] = bec.txerr; 886 cf->data[7] = bec.rxerr; 887 888 break; 889 case C_CAN_ERROR_PASSIVE: 890 /* error passive state */ 891 priv->can.can_stats.error_passive++; 892 priv->can.state = CAN_STATE_ERROR_PASSIVE; 893 cf->can_id |= CAN_ERR_CRTL; 894 if (rx_err_passive) 895 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; 896 if (bec.txerr > 127) 897 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; 898 899 cf->data[6] = bec.txerr; 900 cf->data[7] = bec.rxerr; 901 break; 902 case C_CAN_BUS_OFF: 903 /* bus-off state */ 904 priv->can.state = CAN_STATE_BUS_OFF; 905 cf->can_id |= CAN_ERR_BUSOFF; 906 /* 907 * disable all interrupts in bus-off mode to ensure that 908 * the CPU is not hogged down 909 */ 910 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 911 can_bus_off(dev); 912 break; 913 default: 914 break; 915 } 916 917 netif_receive_skb(skb); 918 stats->rx_packets++; 919 stats->rx_bytes += cf->can_dlc; 920 921 return 1; 922} 923 924static int c_can_handle_bus_err(struct net_device *dev, 925 enum c_can_lec_type lec_type) 926{ 927 struct c_can_priv *priv = netdev_priv(dev); 928 struct net_device_stats *stats = &dev->stats; 929 struct can_frame *cf; 930 struct sk_buff *skb; 931 932 /* 933 * early exit if no lec update or no error. 934 * no lec update means that no CAN bus event has been detected 935 * since CPU wrote 0x7 value to status reg. 936 */ 937 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) 938 return 0; 939 940 /* propagate the error condition to the CAN stack */ 941 skb = alloc_can_err_skb(dev, &cf); 942 if (unlikely(!skb)) 943 return 0; 944 945 /* 946 * check for 'last error code' which tells us the 947 * type of the last error to occur on the CAN bus 948 */ 949 950 /* common for all type of bus errors */ 951 priv->can.can_stats.bus_error++; 952 stats->rx_errors++; 953 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 954 cf->data[2] |= CAN_ERR_PROT_UNSPEC; 955 956 switch (lec_type) { 957 case LEC_STUFF_ERROR: 958 netdev_dbg(dev, "stuff error\n"); 959 cf->data[2] |= CAN_ERR_PROT_STUFF; 960 break; 961 case LEC_FORM_ERROR: 962 netdev_dbg(dev, "form error\n"); 963 cf->data[2] |= CAN_ERR_PROT_FORM; 964 break; 965 case LEC_ACK_ERROR: 966 netdev_dbg(dev, "ack error\n"); 967 cf->data[3] |= (CAN_ERR_PROT_LOC_ACK | 968 CAN_ERR_PROT_LOC_ACK_DEL); 969 break; 970 case LEC_BIT1_ERROR: 971 netdev_dbg(dev, "bit1 error\n"); 972 cf->data[2] |= CAN_ERR_PROT_BIT1; 973 break; 974 case LEC_BIT0_ERROR: 975 netdev_dbg(dev, "bit0 error\n"); 976 cf->data[2] |= CAN_ERR_PROT_BIT0; 977 break; 978 case LEC_CRC_ERROR: 979 netdev_dbg(dev, "CRC error\n"); 980 cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ | 981 CAN_ERR_PROT_LOC_CRC_DEL); 982 break; 983 default: 984 break; 985 } 986 987 /* set a `lec` value so that we can check for updates later */ 988 priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); 989 990 netif_receive_skb(skb); 991 stats->rx_packets++; 992 stats->rx_bytes += cf->can_dlc; 993 994 return 1; 995} 996 997static int c_can_poll(struct napi_struct *napi, int quota) 998{ 999 u16 irqstatus; 1000 int lec_type = 0; 1001 int work_done = 0; 1002 struct net_device *dev = napi->dev; 1003 struct c_can_priv *priv = netdev_priv(dev); 1004 1005 irqstatus = priv->irqstatus; 1006 if (!irqstatus) 1007 goto end; 1008 1009 /* status events have the highest priority */ 1010 if (irqstatus == STATUS_INTERRUPT) { 1011 priv->current_status = priv->read_reg(priv, 1012 C_CAN_STS_REG); 1013 1014 /* handle Tx/Rx events */ 1015 if (priv->current_status & STATUS_TXOK) 1016 priv->write_reg(priv, C_CAN_STS_REG, 1017 priv->current_status & ~STATUS_TXOK); 1018 1019 if (priv->current_status & STATUS_RXOK) 1020 priv->write_reg(priv, C_CAN_STS_REG, 1021 priv->current_status & ~STATUS_RXOK); 1022 1023 /* handle state changes */ 1024 if ((priv->current_status & STATUS_EWARN) && 1025 (!(priv->last_status & STATUS_EWARN))) { 1026 netdev_dbg(dev, "entered error warning state\n"); 1027 work_done += c_can_handle_state_change(dev, 1028 C_CAN_ERROR_WARNING); 1029 } 1030 if ((priv->current_status & STATUS_EPASS) && 1031 (!(priv->last_status & STATUS_EPASS))) { 1032 netdev_dbg(dev, "entered error passive state\n"); 1033 work_done += c_can_handle_state_change(dev, 1034 C_CAN_ERROR_PASSIVE); 1035 } 1036 if ((priv->current_status & STATUS_BOFF) && 1037 (!(priv->last_status & STATUS_BOFF))) { 1038 netdev_dbg(dev, "entered bus off state\n"); 1039 work_done += c_can_handle_state_change(dev, 1040 C_CAN_BUS_OFF); 1041 } 1042 1043 /* handle bus recovery events */ 1044 if ((!(priv->current_status & STATUS_BOFF)) && 1045 (priv->last_status & STATUS_BOFF)) { 1046 netdev_dbg(dev, "left bus off state\n"); 1047 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1048 } 1049 if ((!(priv->current_status & STATUS_EPASS)) && 1050 (priv->last_status & STATUS_EPASS)) { 1051 netdev_dbg(dev, "left error passive state\n"); 1052 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1053 } 1054 1055 priv->last_status = priv->current_status; 1056 1057 /* handle lec errors on the bus */ 1058 lec_type = c_can_has_and_handle_berr(priv); 1059 if (lec_type) 1060 work_done += c_can_handle_bus_err(dev, lec_type); 1061 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) && 1062 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) { 1063 /* handle events corresponding to receive message objects */ 1064 work_done += c_can_do_rx_poll(dev, (quota - work_done)); 1065 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) && 1066 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) { 1067 /* handle events corresponding to transmit message objects */ 1068 c_can_do_tx(dev); 1069 } 1070 1071end: 1072 if (work_done < quota) { 1073 napi_complete(napi); 1074 /* enable all IRQs */ 1075 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS); 1076 } 1077 1078 return work_done; 1079} 1080 1081static irqreturn_t c_can_isr(int irq, void *dev_id) 1082{ 1083 struct net_device *dev = (struct net_device *)dev_id; 1084 struct c_can_priv *priv = netdev_priv(dev); 1085 1086 priv->irqstatus = priv->read_reg(priv, C_CAN_INT_REG); 1087 if (!priv->irqstatus) 1088 return IRQ_NONE; 1089 1090 /* disable all interrupts and schedule the NAPI */ 1091 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS); 1092 napi_schedule(&priv->napi); 1093 1094 return IRQ_HANDLED; 1095} 1096 1097static int c_can_open(struct net_device *dev) 1098{ 1099 int err; 1100 struct c_can_priv *priv = netdev_priv(dev); 1101 1102 c_can_pm_runtime_get_sync(priv); 1103 c_can_reset_ram(priv, true); 1104 1105 /* open the can device */ 1106 err = open_candev(dev); 1107 if (err) { 1108 netdev_err(dev, "failed to open can device\n"); 1109 goto exit_open_fail; 1110 } 1111 1112 /* register interrupt handler */ 1113 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, 1114 dev); 1115 if (err < 0) { 1116 netdev_err(dev, "failed to request interrupt\n"); 1117 goto exit_irq_fail; 1118 } 1119 1120 napi_enable(&priv->napi); 1121 1122 /* start the c_can controller */ 1123 c_can_start(dev); 1124 1125 netif_start_queue(dev); 1126 1127 return 0; 1128 1129exit_irq_fail: 1130 close_candev(dev); 1131exit_open_fail: 1132 c_can_reset_ram(priv, false); 1133 c_can_pm_runtime_put_sync(priv); 1134 return err; 1135} 1136 1137static int c_can_close(struct net_device *dev) 1138{ 1139 struct c_can_priv *priv = netdev_priv(dev); 1140 1141 netif_stop_queue(dev); 1142 napi_disable(&priv->napi); 1143 c_can_stop(dev); 1144 free_irq(dev->irq, dev); 1145 close_candev(dev); 1146 1147 c_can_reset_ram(priv, false); 1148 c_can_pm_runtime_put_sync(priv); 1149 1150 return 0; 1151} 1152 1153struct net_device *alloc_c_can_dev(void) 1154{ 1155 struct net_device *dev; 1156 struct c_can_priv *priv; 1157 1158 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM); 1159 if (!dev) 1160 return NULL; 1161 1162 priv = netdev_priv(dev); 1163 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT); 1164 1165 priv->dev = dev; 1166 priv->can.bittiming_const = &c_can_bittiming_const; 1167 priv->can.do_set_mode = c_can_set_mode; 1168 priv->can.do_get_berr_counter = c_can_get_berr_counter; 1169 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 1170 CAN_CTRLMODE_LISTENONLY | 1171 CAN_CTRLMODE_BERR_REPORTING; 1172 1173 return dev; 1174} 1175EXPORT_SYMBOL_GPL(alloc_c_can_dev); 1176 1177#ifdef CONFIG_PM 1178int c_can_power_down(struct net_device *dev) 1179{ 1180 u32 val; 1181 unsigned long time_out; 1182 struct c_can_priv *priv = netdev_priv(dev); 1183 1184 if (!(dev->flags & IFF_UP)) 1185 return 0; 1186 1187 WARN_ON(priv->type != BOSCH_D_CAN); 1188 1189 /* set PDR value so the device goes to power down mode */ 1190 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1191 val |= CONTROL_EX_PDR; 1192 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1193 1194 /* Wait for the PDA bit to get set */ 1195 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1196 while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1197 time_after(time_out, jiffies)) 1198 cpu_relax(); 1199 1200 if (time_after(jiffies, time_out)) 1201 return -ETIMEDOUT; 1202 1203 c_can_stop(dev); 1204 1205 c_can_reset_ram(priv, false); 1206 c_can_pm_runtime_put_sync(priv); 1207 1208 return 0; 1209} 1210EXPORT_SYMBOL_GPL(c_can_power_down); 1211 1212int c_can_power_up(struct net_device *dev) 1213{ 1214 u32 val; 1215 unsigned long time_out; 1216 struct c_can_priv *priv = netdev_priv(dev); 1217 1218 if (!(dev->flags & IFF_UP)) 1219 return 0; 1220 1221 WARN_ON(priv->type != BOSCH_D_CAN); 1222 1223 c_can_pm_runtime_get_sync(priv); 1224 c_can_reset_ram(priv, true); 1225 1226 /* Clear PDR and INIT bits */ 1227 val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); 1228 val &= ~CONTROL_EX_PDR; 1229 priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); 1230 val = priv->read_reg(priv, C_CAN_CTRL_REG); 1231 val &= ~CONTROL_INIT; 1232 priv->write_reg(priv, C_CAN_CTRL_REG, val); 1233 1234 /* Wait for the PDA bit to get clear */ 1235 time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); 1236 while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && 1237 time_after(time_out, jiffies)) 1238 cpu_relax(); 1239 1240 if (time_after(jiffies, time_out)) 1241 return -ETIMEDOUT; 1242 1243 c_can_start(dev); 1244 1245 return 0; 1246} 1247EXPORT_SYMBOL_GPL(c_can_power_up); 1248#endif 1249 1250void free_c_can_dev(struct net_device *dev) 1251{ 1252 free_candev(dev); 1253} 1254EXPORT_SYMBOL_GPL(free_c_can_dev); 1255 1256static const struct net_device_ops c_can_netdev_ops = { 1257 .ndo_open = c_can_open, 1258 .ndo_stop = c_can_close, 1259 .ndo_start_xmit = c_can_start_xmit, 1260}; 1261 1262int register_c_can_dev(struct net_device *dev) 1263{ 1264 struct c_can_priv *priv = netdev_priv(dev); 1265 int err; 1266 1267 c_can_pm_runtime_enable(priv); 1268 1269 dev->flags |= IFF_ECHO; /* we support local echo */ 1270 dev->netdev_ops = &c_can_netdev_ops; 1271 1272 err = register_candev(dev); 1273 if (err) 1274 c_can_pm_runtime_disable(priv); 1275 1276 return err; 1277} 1278EXPORT_SYMBOL_GPL(register_c_can_dev); 1279 1280void unregister_c_can_dev(struct net_device *dev) 1281{ 1282 struct c_can_priv *priv = netdev_priv(dev); 1283 1284 unregister_candev(dev); 1285 1286 c_can_pm_runtime_disable(priv); 1287} 1288EXPORT_SYMBOL_GPL(unregister_c_can_dev); 1289 1290MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>"); 1291MODULE_LICENSE("GPL v2"); 1292MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); 1293